1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCFixupKinds.h" 11 #include "MCTargetDesc/PPCMCTargetDesc.h" 12 #include "llvm/BinaryFormat/ELF.h" 13 #include "llvm/BinaryFormat/MachO.h" 14 #include "llvm/MC/MCAsmBackend.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCELFObjectWriter.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCMachObjectWriter.h" 19 #include "llvm/MC/MCObjectWriter.h" 20 #include "llvm/MC/MCSectionMachO.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MC/MCSymbolELF.h" 23 #include "llvm/MC/MCValue.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 using namespace llvm; 27 28 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { 29 switch (Kind) { 30 default: 31 llvm_unreachable("Unknown fixup kind!"); 32 case FK_Data_1: 33 case FK_Data_2: 34 case FK_Data_4: 35 case FK_Data_8: 36 case PPC::fixup_ppc_nofixup: 37 return Value; 38 case PPC::fixup_ppc_brcond14: 39 case PPC::fixup_ppc_brcond14abs: 40 return Value & 0xfffc; 41 case PPC::fixup_ppc_br24: 42 case PPC::fixup_ppc_br24abs: 43 return Value & 0x3fffffc; 44 case PPC::fixup_ppc_half16: 45 return Value & 0xffff; 46 case PPC::fixup_ppc_half16ds: 47 return Value & 0xfffc; 48 } 49 } 50 51 static unsigned getFixupKindNumBytes(unsigned Kind) { 52 switch (Kind) { 53 default: 54 llvm_unreachable("Unknown fixup kind!"); 55 case FK_Data_1: 56 return 1; 57 case FK_Data_2: 58 case PPC::fixup_ppc_half16: 59 case PPC::fixup_ppc_half16ds: 60 return 2; 61 case FK_Data_4: 62 case PPC::fixup_ppc_brcond14: 63 case PPC::fixup_ppc_brcond14abs: 64 case PPC::fixup_ppc_br24: 65 case PPC::fixup_ppc_br24abs: 66 return 4; 67 case FK_Data_8: 68 return 8; 69 case PPC::fixup_ppc_nofixup: 70 return 0; 71 } 72 } 73 74 namespace { 75 76 class PPCAsmBackend : public MCAsmBackend { 77 const Target &TheTarget; 78 bool IsLittleEndian; 79 public: 80 PPCAsmBackend(const Target &T, bool isLittle) : MCAsmBackend(), TheTarget(T), 81 IsLittleEndian(isLittle) {} 82 83 unsigned getNumFixupKinds() const override { 84 return PPC::NumTargetFixupKinds; 85 } 86 87 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 88 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = { 89 // name offset bits flags 90 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, 92 { "fixup_ppc_br24abs", 6, 24, 0 }, 93 { "fixup_ppc_brcond14abs", 16, 14, 0 }, 94 { "fixup_ppc_half16", 0, 16, 0 }, 95 { "fixup_ppc_half16ds", 0, 14, 0 }, 96 { "fixup_ppc_nofixup", 0, 0, 0 } 97 }; 98 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = { 99 // name offset bits flags 100 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel }, 101 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel }, 102 { "fixup_ppc_br24abs", 2, 24, 0 }, 103 { "fixup_ppc_brcond14abs", 2, 14, 0 }, 104 { "fixup_ppc_half16", 0, 16, 0 }, 105 { "fixup_ppc_half16ds", 2, 14, 0 }, 106 { "fixup_ppc_nofixup", 0, 0, 0 } 107 }; 108 109 if (Kind < FirstTargetFixupKind) 110 return MCAsmBackend::getFixupKindInfo(Kind); 111 112 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 113 "Invalid kind!"); 114 return (IsLittleEndian? InfosLE : InfosBE)[Kind - FirstTargetFixupKind]; 115 } 116 117 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 118 const MCValue &Target, MutableArrayRef<char> Data, 119 uint64_t Value, bool IsResolved) const override { 120 Value = adjustFixupValue(Fixup.getKind(), Value); 121 if (!Value) return; // Doesn't change encoding. 122 123 unsigned Offset = Fixup.getOffset(); 124 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 125 126 // For each byte of the fragment that the fixup touches, mask in the bits 127 // from the fixup value. The Value has been "split up" into the appropriate 128 // bitfields above. 129 for (unsigned i = 0; i != NumBytes; ++i) { 130 unsigned Idx = IsLittleEndian ? i : (NumBytes - 1 - i); 131 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); 132 } 133 } 134 135 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 136 const MCValue &Target) override { 137 switch ((PPC::Fixups)Fixup.getKind()) { 138 default: 139 return false; 140 case PPC::fixup_ppc_br24: 141 case PPC::fixup_ppc_br24abs: 142 // If the target symbol has a local entry point we must not attempt 143 // to resolve the fixup directly. Emit a relocation and leave 144 // resolution of the final target address to the linker. 145 if (const MCSymbolRefExpr *A = Target.getSymA()) { 146 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) { 147 // The "other" values are stored in the last 6 bits of the second 148 // byte. The traditional defines for STO values assume the full byte 149 // and thus the shift to pack it. 150 unsigned Other = S->getOther() << 2; 151 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0) 152 return true; 153 } 154 } 155 return false; 156 } 157 } 158 159 bool mayNeedRelaxation(const MCInst &Inst) const override { 160 // FIXME. 161 return false; 162 } 163 164 bool fixupNeedsRelaxation(const MCFixup &Fixup, 165 uint64_t Value, 166 const MCRelaxableFragment *DF, 167 const MCAsmLayout &Layout) const override { 168 // FIXME. 169 llvm_unreachable("relaxInstruction() unimplemented"); 170 } 171 172 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 173 MCInst &Res) const override { 174 // FIXME. 175 llvm_unreachable("relaxInstruction() unimplemented"); 176 } 177 178 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const override { 179 uint64_t NumNops = Count / 4; 180 for (uint64_t i = 0; i != NumNops; ++i) 181 OW->write32(0x60000000); 182 183 OW->WriteZeros(Count % 4); 184 185 return true; 186 } 187 188 unsigned getPointerSize() const { 189 StringRef Name = TheTarget.getName(); 190 if (Name == "ppc64" || Name == "ppc64le") return 8; 191 assert(Name == "ppc32" && "Unknown target name!"); 192 return 4; 193 } 194 195 bool isLittleEndian() const { 196 return IsLittleEndian; 197 } 198 }; 199 } // end anonymous namespace 200 201 202 // FIXME: This should be in a separate file. 203 namespace { 204 class DarwinPPCAsmBackend : public PPCAsmBackend { 205 public: 206 DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, false) { } 207 208 std::unique_ptr<MCObjectWriter> 209 createObjectWriter(raw_pwrite_stream &OS) const override { 210 bool is64 = getPointerSize() == 8; 211 return createPPCMachObjectWriter( 212 OS, 213 /*Is64Bit=*/is64, 214 (is64 ? MachO::CPU_TYPE_POWERPC64 : MachO::CPU_TYPE_POWERPC), 215 MachO::CPU_SUBTYPE_POWERPC_ALL); 216 } 217 }; 218 219 class ELFPPCAsmBackend : public PPCAsmBackend { 220 uint8_t OSABI; 221 public: 222 ELFPPCAsmBackend(const Target &T, bool IsLittleEndian, uint8_t OSABI) : 223 PPCAsmBackend(T, IsLittleEndian), OSABI(OSABI) { } 224 225 std::unique_ptr<MCObjectWriter> 226 createObjectWriter(raw_pwrite_stream &OS) const override { 227 bool is64 = getPointerSize() == 8; 228 return createPPCELFObjectWriter(OS, is64, isLittleEndian(), OSABI); 229 } 230 }; 231 232 } // end anonymous namespace 233 234 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, 235 const MCSubtargetInfo &STI, 236 const MCRegisterInfo &MRI, 237 const MCTargetOptions &Options) { 238 const Triple &TT = STI.getTargetTriple(); 239 if (TT.isOSDarwin()) 240 return new DarwinPPCAsmBackend(T); 241 242 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 243 bool IsLittleEndian = TT.getArch() == Triple::ppc64le; 244 return new ELFPPCAsmBackend(T, IsLittleEndian, OSABI); 245 } 246