1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCFixupKinds.h" 11 #include "MCTargetDesc/PPCMCTargetDesc.h" 12 #include "llvm/BinaryFormat/ELF.h" 13 #include "llvm/BinaryFormat/MachO.h" 14 #include "llvm/MC/MCAsmBackend.h" 15 #include "llvm/MC/MCAssembler.h" 16 #include "llvm/MC/MCELFObjectWriter.h" 17 #include "llvm/MC/MCFixupKindInfo.h" 18 #include "llvm/MC/MCMachObjectWriter.h" 19 #include "llvm/MC/MCObjectWriter.h" 20 #include "llvm/MC/MCSectionMachO.h" 21 #include "llvm/MC/MCSubtargetInfo.h" 22 #include "llvm/MC/MCSymbolELF.h" 23 #include "llvm/MC/MCValue.h" 24 #include "llvm/Support/ErrorHandling.h" 25 #include "llvm/Support/TargetRegistry.h" 26 using namespace llvm; 27 28 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { 29 switch (Kind) { 30 default: 31 llvm_unreachable("Unknown fixup kind!"); 32 case FK_Data_1: 33 case FK_Data_2: 34 case FK_Data_4: 35 case FK_Data_8: 36 case PPC::fixup_ppc_nofixup: 37 return Value; 38 case PPC::fixup_ppc_brcond14: 39 case PPC::fixup_ppc_brcond14abs: 40 return Value & 0xfffc; 41 case PPC::fixup_ppc_br24: 42 case PPC::fixup_ppc_br24abs: 43 return Value & 0x3fffffc; 44 case PPC::fixup_ppc_half16: 45 return Value & 0xffff; 46 case PPC::fixup_ppc_half16ds: 47 return Value & 0xfffc; 48 } 49 } 50 51 static unsigned getFixupKindNumBytes(unsigned Kind) { 52 switch (Kind) { 53 default: 54 llvm_unreachable("Unknown fixup kind!"); 55 case FK_Data_1: 56 return 1; 57 case FK_Data_2: 58 case PPC::fixup_ppc_half16: 59 case PPC::fixup_ppc_half16ds: 60 return 2; 61 case FK_Data_4: 62 case PPC::fixup_ppc_brcond14: 63 case PPC::fixup_ppc_brcond14abs: 64 case PPC::fixup_ppc_br24: 65 case PPC::fixup_ppc_br24abs: 66 return 4; 67 case FK_Data_8: 68 return 8; 69 case PPC::fixup_ppc_nofixup: 70 return 0; 71 } 72 } 73 74 namespace { 75 76 class PPCAsmBackend : public MCAsmBackend { 77 const Target &TheTarget; 78 public: 79 PPCAsmBackend(const Target &T, support::endianness Endian) 80 : MCAsmBackend(Endian), TheTarget(T) {} 81 82 unsigned getNumFixupKinds() const override { 83 return PPC::NumTargetFixupKinds; 84 } 85 86 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 87 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = { 88 // name offset bits flags 89 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, 91 { "fixup_ppc_br24abs", 6, 24, 0 }, 92 { "fixup_ppc_brcond14abs", 16, 14, 0 }, 93 { "fixup_ppc_half16", 0, 16, 0 }, 94 { "fixup_ppc_half16ds", 0, 14, 0 }, 95 { "fixup_ppc_nofixup", 0, 0, 0 } 96 }; 97 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = { 98 // name offset bits flags 99 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel }, 100 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel }, 101 { "fixup_ppc_br24abs", 2, 24, 0 }, 102 { "fixup_ppc_brcond14abs", 2, 14, 0 }, 103 { "fixup_ppc_half16", 0, 16, 0 }, 104 { "fixup_ppc_half16ds", 2, 14, 0 }, 105 { "fixup_ppc_nofixup", 0, 0, 0 } 106 }; 107 108 if (Kind < FirstTargetFixupKind) 109 return MCAsmBackend::getFixupKindInfo(Kind); 110 111 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 112 "Invalid kind!"); 113 return (Endian == support::little 114 ? InfosLE 115 : InfosBE)[Kind - FirstTargetFixupKind]; 116 } 117 118 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 119 const MCValue &Target, MutableArrayRef<char> Data, 120 uint64_t Value, bool IsResolved) const override { 121 Value = adjustFixupValue(Fixup.getKind(), Value); 122 if (!Value) return; // Doesn't change encoding. 123 124 unsigned Offset = Fixup.getOffset(); 125 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 126 127 // For each byte of the fragment that the fixup touches, mask in the bits 128 // from the fixup value. The Value has been "split up" into the appropriate 129 // bitfields above. 130 for (unsigned i = 0; i != NumBytes; ++i) { 131 unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i); 132 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); 133 } 134 } 135 136 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 137 const MCValue &Target) override { 138 switch ((PPC::Fixups)Fixup.getKind()) { 139 default: 140 return false; 141 case PPC::fixup_ppc_br24: 142 case PPC::fixup_ppc_br24abs: 143 // If the target symbol has a local entry point we must not attempt 144 // to resolve the fixup directly. Emit a relocation and leave 145 // resolution of the final target address to the linker. 146 if (const MCSymbolRefExpr *A = Target.getSymA()) { 147 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) { 148 // The "other" values are stored in the last 6 bits of the second 149 // byte. The traditional defines for STO values assume the full byte 150 // and thus the shift to pack it. 151 unsigned Other = S->getOther() << 2; 152 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0) 153 return true; 154 } 155 } 156 return false; 157 } 158 } 159 160 bool mayNeedRelaxation(const MCInst &Inst) const override { 161 // FIXME. 162 return false; 163 } 164 165 bool fixupNeedsRelaxation(const MCFixup &Fixup, 166 uint64_t Value, 167 const MCRelaxableFragment *DF, 168 const MCAsmLayout &Layout) const override { 169 // FIXME. 170 llvm_unreachable("relaxInstruction() unimplemented"); 171 } 172 173 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 174 MCInst &Res) const override { 175 // FIXME. 176 llvm_unreachable("relaxInstruction() unimplemented"); 177 } 178 179 bool writeNopData(raw_ostream &OS, uint64_t Count) const override { 180 uint64_t NumNops = Count / 4; 181 for (uint64_t i = 0; i != NumNops; ++i) 182 support::endian::write<uint32_t>(OS, 0x60000000, Endian); 183 184 OS.write_zeros(Count % 4); 185 186 return true; 187 } 188 189 unsigned getPointerSize() const { 190 StringRef Name = TheTarget.getName(); 191 if (Name == "ppc64" || Name == "ppc64le") return 8; 192 assert(Name == "ppc32" && "Unknown target name!"); 193 return 4; 194 } 195 }; 196 } // end anonymous namespace 197 198 199 // FIXME: This should be in a separate file. 200 namespace { 201 class DarwinPPCAsmBackend : public PPCAsmBackend { 202 public: 203 DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, support::big) { } 204 205 std::unique_ptr<MCObjectTargetWriter> 206 createObjectTargetWriter() const override { 207 bool is64 = getPointerSize() == 8; 208 return createPPCMachObjectWriter( 209 /*Is64Bit=*/is64, 210 (is64 ? MachO::CPU_TYPE_POWERPC64 : MachO::CPU_TYPE_POWERPC), 211 MachO::CPU_SUBTYPE_POWERPC_ALL); 212 } 213 }; 214 215 class ELFPPCAsmBackend : public PPCAsmBackend { 216 uint8_t OSABI; 217 public: 218 ELFPPCAsmBackend(const Target &T, support::endianness Endian, 219 uint8_t OSABI) 220 : PPCAsmBackend(T, Endian), OSABI(OSABI) {} 221 222 std::unique_ptr<MCObjectTargetWriter> 223 createObjectTargetWriter() const override { 224 bool is64 = getPointerSize() == 8; 225 return createPPCELFObjectWriter(is64, OSABI); 226 } 227 }; 228 229 } // end anonymous namespace 230 231 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, 232 const MCSubtargetInfo &STI, 233 const MCRegisterInfo &MRI, 234 const MCTargetOptions &Options) { 235 const Triple &TT = STI.getTargetTriple(); 236 if (TT.isOSDarwin()) 237 return new DarwinPPCAsmBackend(T); 238 239 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 240 bool IsLittleEndian = TT.getArch() == Triple::ppc64le; 241 return new ELFPPCAsmBackend( 242 T, IsLittleEndian ? support::little : support::big, OSABI); 243 } 244