1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "MCTargetDesc/PPCFixupKinds.h" 12 #include "llvm/MC/MCAsmBackend.h" 13 #include "llvm/MC/MCELFObjectWriter.h" 14 #include "llvm/MC/MCFixupKindInfo.h" 15 #include "llvm/MC/MCMachObjectWriter.h" 16 #include "llvm/MC/MCObjectWriter.h" 17 #include "llvm/MC/MCSectionMachO.h" 18 #include "llvm/MC/MCValue.h" 19 #include "llvm/Object/MachOFormat.h" 20 #include "llvm/Support/ELF.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/TargetRegistry.h" 23 using namespace llvm; 24 25 static unsigned adjustFixupValue(unsigned Kind, uint64_t Value) { 26 switch (Kind) { 27 default: 28 llvm_unreachable("Unknown fixup kind!"); 29 case FK_Data_1: 30 case FK_Data_2: 31 case FK_Data_4: 32 case FK_Data_8: 33 case PPC::fixup_ppc_tlsreg: 34 case PPC::fixup_ppc_nofixup: 35 return Value; 36 case PPC::fixup_ppc_brcond14: 37 return Value & 0xfffc; 38 case PPC::fixup_ppc_br24: 39 return Value & 0x3fffffc; 40 #if 0 41 case PPC::fixup_ppc_hi16: 42 return (Value >> 16) & 0xffff; 43 #endif 44 case PPC::fixup_ppc_ha16: 45 return ((Value >> 16) + ((Value & 0x8000) ? 1 : 0)) & 0xffff; 46 case PPC::fixup_ppc_lo16: 47 return Value & 0xffff; 48 case PPC::fixup_ppc_lo16_ds: 49 return Value & 0xfffc; 50 } 51 } 52 53 namespace { 54 class PPCMachObjectWriter : public MCMachObjectTargetWriter { 55 public: 56 PPCMachObjectWriter(bool Is64Bit, uint32_t CPUType, 57 uint32_t CPUSubtype) 58 : MCMachObjectTargetWriter(Is64Bit, CPUType, CPUSubtype) {} 59 60 void RecordRelocation(MachObjectWriter *Writer, 61 const MCAssembler &Asm, const MCAsmLayout &Layout, 62 const MCFragment *Fragment, const MCFixup &Fixup, 63 MCValue Target, uint64_t &FixedValue) { 64 llvm_unreachable("Relocation emission for MachO/PPC unimplemented!"); 65 } 66 }; 67 68 class PPCAsmBackend : public MCAsmBackend { 69 const Target &TheTarget; 70 public: 71 PPCAsmBackend(const Target &T) : MCAsmBackend(), TheTarget(T) {} 72 73 unsigned getNumFixupKinds() const { return PPC::NumTargetFixupKinds; } 74 75 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const { 76 const static MCFixupKindInfo Infos[PPC::NumTargetFixupKinds] = { 77 // name offset bits flags 78 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, 79 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, 80 { "fixup_ppc_lo16", 16, 16, 0 }, 81 { "fixup_ppc_ha16", 16, 16, 0 }, 82 { "fixup_ppc_lo16_ds", 16, 14, 0 }, 83 { "fixup_ppc_tlsreg", 0, 0, 0 }, 84 { "fixup_ppc_nofixup", 0, 0, 0 } 85 }; 86 87 if (Kind < FirstTargetFixupKind) 88 return MCAsmBackend::getFixupKindInfo(Kind); 89 90 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 91 "Invalid kind!"); 92 return Infos[Kind - FirstTargetFixupKind]; 93 } 94 95 void applyFixup(const MCFixup &Fixup, char *Data, unsigned DataSize, 96 uint64_t Value) const { 97 Value = adjustFixupValue(Fixup.getKind(), Value); 98 if (!Value) return; // Doesn't change encoding. 99 100 unsigned Offset = Fixup.getOffset(); 101 102 // For each byte of the fragment that the fixup touches, mask in the bits 103 // from the fixup value. The Value has been "split up" into the appropriate 104 // bitfields above. 105 for (unsigned i = 0; i != 4; ++i) 106 Data[Offset + i] |= uint8_t((Value >> ((4 - i - 1)*8)) & 0xff); 107 } 108 109 bool mayNeedRelaxation(const MCInst &Inst) const { 110 // FIXME. 111 return false; 112 } 113 114 bool fixupNeedsRelaxation(const MCFixup &Fixup, 115 uint64_t Value, 116 const MCRelaxableFragment *DF, 117 const MCAsmLayout &Layout) const { 118 // FIXME. 119 llvm_unreachable("relaxInstruction() unimplemented"); 120 } 121 122 123 void relaxInstruction(const MCInst &Inst, MCInst &Res) const { 124 // FIXME. 125 llvm_unreachable("relaxInstruction() unimplemented"); 126 } 127 128 bool writeNopData(uint64_t Count, MCObjectWriter *OW) const { 129 // FIXME: Zero fill for now. That's not right, but at least will get the 130 // section size right. 131 for (uint64_t i = 0; i != Count; ++i) 132 OW->Write8(0); 133 return true; 134 } 135 136 unsigned getPointerSize() const { 137 StringRef Name = TheTarget.getName(); 138 if (Name == "ppc64") return 8; 139 assert(Name == "ppc32" && "Unknown target name!"); 140 return 4; 141 } 142 }; 143 } // end anonymous namespace 144 145 146 // FIXME: This should be in a separate file. 147 namespace { 148 class DarwinPPCAsmBackend : public PPCAsmBackend { 149 public: 150 DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T) { } 151 152 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 153 bool is64 = getPointerSize() == 8; 154 return createMachObjectWriter(new PPCMachObjectWriter( 155 /*Is64Bit=*/is64, 156 (is64 ? object::mach::CTM_PowerPC64 : 157 object::mach::CTM_PowerPC), 158 object::mach::CSPPC_ALL), 159 OS, /*IsLittleEndian=*/false); 160 } 161 162 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 163 return false; 164 } 165 }; 166 167 class ELFPPCAsmBackend : public PPCAsmBackend { 168 uint8_t OSABI; 169 public: 170 ELFPPCAsmBackend(const Target &T, uint8_t OSABI) : 171 PPCAsmBackend(T), OSABI(OSABI) { } 172 173 174 MCObjectWriter *createObjectWriter(raw_ostream &OS) const { 175 bool is64 = getPointerSize() == 8; 176 return createPPCELFObjectWriter(OS, is64, OSABI); 177 } 178 179 virtual bool doesSectionRequireSymbols(const MCSection &Section) const { 180 return false; 181 } 182 }; 183 184 } // end anonymous namespace 185 186 187 188 189 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, StringRef TT, StringRef CPU) { 190 if (Triple(TT).isOSDarwin()) 191 return new DarwinPPCAsmBackend(T); 192 193 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(Triple(TT).getOS()); 194 return new ELFPPCAsmBackend(T, OSABI); 195 } 196