1 //===-- PPCAsmBackend.cpp - PPC Assembler Backend -------------------------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCFixupKinds.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "llvm/BinaryFormat/ELF.h" 12 #include "llvm/BinaryFormat/MachO.h" 13 #include "llvm/MC/MCAsmBackend.h" 14 #include "llvm/MC/MCAssembler.h" 15 #include "llvm/MC/MCELFObjectWriter.h" 16 #include "llvm/MC/MCFixupKindInfo.h" 17 #include "llvm/MC/MCMachObjectWriter.h" 18 #include "llvm/MC/MCObjectWriter.h" 19 #include "llvm/MC/MCSectionMachO.h" 20 #include "llvm/MC/MCSubtargetInfo.h" 21 #include "llvm/MC/MCSymbolELF.h" 22 #include "llvm/MC/MCValue.h" 23 #include "llvm/Support/ErrorHandling.h" 24 #include "llvm/Support/TargetRegistry.h" 25 using namespace llvm; 26 27 static uint64_t adjustFixupValue(unsigned Kind, uint64_t Value) { 28 switch (Kind) { 29 default: 30 llvm_unreachable("Unknown fixup kind!"); 31 case FK_Data_1: 32 case FK_Data_2: 33 case FK_Data_4: 34 case FK_Data_8: 35 case PPC::fixup_ppc_nofixup: 36 return Value; 37 case PPC::fixup_ppc_brcond14: 38 case PPC::fixup_ppc_brcond14abs: 39 return Value & 0xfffc; 40 case PPC::fixup_ppc_br24: 41 case PPC::fixup_ppc_br24abs: 42 return Value & 0x3fffffc; 43 case PPC::fixup_ppc_half16: 44 return Value & 0xffff; 45 case PPC::fixup_ppc_half16ds: 46 return Value & 0xfffc; 47 } 48 } 49 50 static unsigned getFixupKindNumBytes(unsigned Kind) { 51 switch (Kind) { 52 default: 53 llvm_unreachable("Unknown fixup kind!"); 54 case FK_Data_1: 55 return 1; 56 case FK_Data_2: 57 case PPC::fixup_ppc_half16: 58 case PPC::fixup_ppc_half16ds: 59 return 2; 60 case FK_Data_4: 61 case PPC::fixup_ppc_brcond14: 62 case PPC::fixup_ppc_brcond14abs: 63 case PPC::fixup_ppc_br24: 64 case PPC::fixup_ppc_br24abs: 65 return 4; 66 case FK_Data_8: 67 return 8; 68 case PPC::fixup_ppc_nofixup: 69 return 0; 70 } 71 } 72 73 namespace { 74 75 class PPCAsmBackend : public MCAsmBackend { 76 const Target &TheTarget; 77 public: 78 PPCAsmBackend(const Target &T, support::endianness Endian) 79 : MCAsmBackend(Endian), TheTarget(T) {} 80 81 unsigned getNumFixupKinds() const override { 82 return PPC::NumTargetFixupKinds; 83 } 84 85 const MCFixupKindInfo &getFixupKindInfo(MCFixupKind Kind) const override { 86 const static MCFixupKindInfo InfosBE[PPC::NumTargetFixupKinds] = { 87 // name offset bits flags 88 { "fixup_ppc_br24", 6, 24, MCFixupKindInfo::FKF_IsPCRel }, 89 { "fixup_ppc_brcond14", 16, 14, MCFixupKindInfo::FKF_IsPCRel }, 90 { "fixup_ppc_br24abs", 6, 24, 0 }, 91 { "fixup_ppc_brcond14abs", 16, 14, 0 }, 92 { "fixup_ppc_half16", 0, 16, 0 }, 93 { "fixup_ppc_half16ds", 0, 14, 0 }, 94 { "fixup_ppc_nofixup", 0, 0, 0 } 95 }; 96 const static MCFixupKindInfo InfosLE[PPC::NumTargetFixupKinds] = { 97 // name offset bits flags 98 { "fixup_ppc_br24", 2, 24, MCFixupKindInfo::FKF_IsPCRel }, 99 { "fixup_ppc_brcond14", 2, 14, MCFixupKindInfo::FKF_IsPCRel }, 100 { "fixup_ppc_br24abs", 2, 24, 0 }, 101 { "fixup_ppc_brcond14abs", 2, 14, 0 }, 102 { "fixup_ppc_half16", 0, 16, 0 }, 103 { "fixup_ppc_half16ds", 2, 14, 0 }, 104 { "fixup_ppc_nofixup", 0, 0, 0 } 105 }; 106 107 if (Kind < FirstTargetFixupKind) 108 return MCAsmBackend::getFixupKindInfo(Kind); 109 110 assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() && 111 "Invalid kind!"); 112 return (Endian == support::little 113 ? InfosLE 114 : InfosBE)[Kind - FirstTargetFixupKind]; 115 } 116 117 void applyFixup(const MCAssembler &Asm, const MCFixup &Fixup, 118 const MCValue &Target, MutableArrayRef<char> Data, 119 uint64_t Value, bool IsResolved, 120 const MCSubtargetInfo *STI) const override { 121 Value = adjustFixupValue(Fixup.getKind(), Value); 122 if (!Value) return; // Doesn't change encoding. 123 124 unsigned Offset = Fixup.getOffset(); 125 unsigned NumBytes = getFixupKindNumBytes(Fixup.getKind()); 126 127 // For each byte of the fragment that the fixup touches, mask in the bits 128 // from the fixup value. The Value has been "split up" into the appropriate 129 // bitfields above. 130 for (unsigned i = 0; i != NumBytes; ++i) { 131 unsigned Idx = Endian == support::little ? i : (NumBytes - 1 - i); 132 Data[Offset + i] |= uint8_t((Value >> (Idx * 8)) & 0xff); 133 } 134 } 135 136 bool shouldForceRelocation(const MCAssembler &Asm, const MCFixup &Fixup, 137 const MCValue &Target) override { 138 switch ((PPC::Fixups)Fixup.getKind()) { 139 default: 140 return false; 141 case PPC::fixup_ppc_br24: 142 case PPC::fixup_ppc_br24abs: 143 // If the target symbol has a local entry point we must not attempt 144 // to resolve the fixup directly. Emit a relocation and leave 145 // resolution of the final target address to the linker. 146 if (const MCSymbolRefExpr *A = Target.getSymA()) { 147 if (const auto *S = dyn_cast<MCSymbolELF>(&A->getSymbol())) { 148 // The "other" values are stored in the last 6 bits of the second 149 // byte. The traditional defines for STO values assume the full byte 150 // and thus the shift to pack it. 151 unsigned Other = S->getOther() << 2; 152 if ((Other & ELF::STO_PPC64_LOCAL_MASK) != 0) 153 return true; 154 } 155 } 156 return false; 157 } 158 } 159 160 bool mayNeedRelaxation(const MCInst &Inst, 161 const MCSubtargetInfo &STI) const override { 162 // FIXME. 163 return false; 164 } 165 166 bool fixupNeedsRelaxation(const MCFixup &Fixup, 167 uint64_t Value, 168 const MCRelaxableFragment *DF, 169 const MCAsmLayout &Layout) const override { 170 // FIXME. 171 llvm_unreachable("relaxInstruction() unimplemented"); 172 } 173 174 void relaxInstruction(const MCInst &Inst, const MCSubtargetInfo &STI, 175 MCInst &Res) const override { 176 // FIXME. 177 llvm_unreachable("relaxInstruction() unimplemented"); 178 } 179 180 bool writeNopData(raw_ostream &OS, uint64_t Count) const override { 181 uint64_t NumNops = Count / 4; 182 for (uint64_t i = 0; i != NumNops; ++i) 183 support::endian::write<uint32_t>(OS, 0x60000000, Endian); 184 185 OS.write_zeros(Count % 4); 186 187 return true; 188 } 189 190 unsigned getPointerSize() const { 191 StringRef Name = TheTarget.getName(); 192 if (Name == "ppc64" || Name == "ppc64le") return 8; 193 assert(Name == "ppc32" && "Unknown target name!"); 194 return 4; 195 } 196 }; 197 } // end anonymous namespace 198 199 200 // FIXME: This should be in a separate file. 201 namespace { 202 class DarwinPPCAsmBackend : public PPCAsmBackend { 203 public: 204 DarwinPPCAsmBackend(const Target &T) : PPCAsmBackend(T, support::big) { } 205 206 std::unique_ptr<MCObjectTargetWriter> 207 createObjectTargetWriter() const override { 208 bool is64 = getPointerSize() == 8; 209 return createPPCMachObjectWriter( 210 /*Is64Bit=*/is64, 211 (is64 ? MachO::CPU_TYPE_POWERPC64 : MachO::CPU_TYPE_POWERPC), 212 MachO::CPU_SUBTYPE_POWERPC_ALL); 213 } 214 }; 215 216 class ELFPPCAsmBackend : public PPCAsmBackend { 217 uint8_t OSABI; 218 public: 219 ELFPPCAsmBackend(const Target &T, support::endianness Endian, 220 uint8_t OSABI) 221 : PPCAsmBackend(T, Endian), OSABI(OSABI) {} 222 223 std::unique_ptr<MCObjectTargetWriter> 224 createObjectTargetWriter() const override { 225 bool is64 = getPointerSize() == 8; 226 return createPPCELFObjectWriter(is64, OSABI); 227 } 228 }; 229 230 } // end anonymous namespace 231 232 MCAsmBackend *llvm::createPPCAsmBackend(const Target &T, 233 const MCSubtargetInfo &STI, 234 const MCRegisterInfo &MRI, 235 const MCTargetOptions &Options) { 236 const Triple &TT = STI.getTargetTriple(); 237 if (TT.isOSDarwin()) 238 return new DarwinPPCAsmBackend(T); 239 240 uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TT.getOS()); 241 bool IsLittleEndian = TT.getArch() == Triple::ppc64le; 242 return new ELFPPCAsmBackend( 243 T, IsLittleEndian ? support::little : support::big, OSABI); 244 } 245