1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===//
2 //
3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
4 // See https://llvm.org/LICENSE.txt for license information.
5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
6 //
7 //===----------------------------------------------------------------------===//
8 
9 #include "MCTargetDesc/PPCMCTargetDesc.h"
10 #include "TargetInfo/PowerPCTargetInfo.h"
11 #include "llvm/MC/MCDisassembler/MCDisassembler.h"
12 #include "llvm/MC/MCFixedLenDisassembler.h"
13 #include "llvm/MC/MCInst.h"
14 #include "llvm/MC/MCSubtargetInfo.h"
15 #include "llvm/Support/Endian.h"
16 #include "llvm/Support/TargetRegistry.h"
17 
18 using namespace llvm;
19 
20 DEFINE_PPC_REGCLASSES;
21 
22 #define DEBUG_TYPE "ppc-disassembler"
23 
24 typedef MCDisassembler::DecodeStatus DecodeStatus;
25 
26 namespace {
27 class PPCDisassembler : public MCDisassembler {
28   bool IsLittleEndian;
29 
30 public:
31   PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx,
32                   bool IsLittleEndian)
33       : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {}
34 
35   DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size,
36                               ArrayRef<uint8_t> Bytes, uint64_t Address,
37                               raw_ostream &CStream) const override;
38 };
39 } // end anonymous namespace
40 
41 static MCDisassembler *createPPCDisassembler(const Target &T,
42                                              const MCSubtargetInfo &STI,
43                                              MCContext &Ctx) {
44   return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false);
45 }
46 
47 static MCDisassembler *createPPCLEDisassembler(const Target &T,
48                                                const MCSubtargetInfo &STI,
49                                                MCContext &Ctx) {
50   return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true);
51 }
52 
53 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCDisassembler() {
54   // Register the disassembler for each target.
55   TargetRegistry::RegisterMCDisassembler(getThePPC32Target(),
56                                          createPPCDisassembler);
57   TargetRegistry::RegisterMCDisassembler(getThePPC64Target(),
58                                          createPPCDisassembler);
59   TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(),
60                                          createPPCLEDisassembler);
61 }
62 
63 static DecodeStatus decodeCondBrTarget(MCInst &Inst, unsigned Imm,
64                                        uint64_t /*Address*/,
65                                        const void * /*Decoder*/) {
66   Inst.addOperand(MCOperand::createImm(SignExtend32<14>(Imm)));
67   return MCDisassembler::Success;
68 }
69 
70 static DecodeStatus decodeDirectBrTarget(MCInst &Inst, unsigned Imm,
71                                          uint64_t /*Address*/,
72                                          const void * /*Decoder*/) {
73   int32_t Offset = SignExtend32<24>(Imm);
74   Inst.addOperand(MCOperand::createImm(Offset));
75   return MCDisassembler::Success;
76 }
77 
78 // FIXME: These can be generated by TableGen from the existing register
79 // encoding values!
80 
81 template <std::size_t N>
82 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo,
83                                         const MCPhysReg (&Regs)[N]) {
84   assert(RegNo < N && "Invalid register number");
85   Inst.addOperand(MCOperand::createReg(Regs[RegNo]));
86   return MCDisassembler::Success;
87 }
88 
89 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
90                                             uint64_t Address,
91                                             const void *Decoder) {
92   return decodeRegisterClass(Inst, RegNo, CRRegs);
93 }
94 
95 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo,
96                                             uint64_t Address,
97                                             const void *Decoder) {
98   return decodeRegisterClass(Inst, RegNo, CRBITRegs);
99 }
100 
101 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo,
102                                             uint64_t Address,
103                                             const void *Decoder) {
104   return decodeRegisterClass(Inst, RegNo, FRegs);
105 }
106 
107 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
108                                             uint64_t Address,
109                                             const void *Decoder) {
110   return decodeRegisterClass(Inst, RegNo, FRegs);
111 }
112 
113 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
114                                             uint64_t Address,
115                                             const void *Decoder) {
116   return decodeRegisterClass(Inst, RegNo, VFRegs);
117 }
118 
119 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo,
120                                             uint64_t Address,
121                                             const void *Decoder) {
122   return decodeRegisterClass(Inst, RegNo, VRegs);
123 }
124 
125 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
126                                             uint64_t Address,
127                                             const void *Decoder) {
128   return decodeRegisterClass(Inst, RegNo, VSRegs);
129 }
130 
131 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo,
132                                             uint64_t Address,
133                                             const void *Decoder) {
134   return decodeRegisterClass(Inst, RegNo, VSFRegs);
135 }
136 
137 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo,
138                                             uint64_t Address,
139                                             const void *Decoder) {
140   return decodeRegisterClass(Inst, RegNo, VSSRegs);
141 }
142 
143 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo,
144                                             uint64_t Address,
145                                             const void *Decoder) {
146   return decodeRegisterClass(Inst, RegNo, RRegs);
147 }
148 
149 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo,
150                                             uint64_t Address,
151                                             const void *Decoder) {
152   return decodeRegisterClass(Inst, RegNo, RRegsNoR0);
153 }
154 
155 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo,
156                                             uint64_t Address,
157                                             const void *Decoder) {
158   return decodeRegisterClass(Inst, RegNo, XRegs);
159 }
160 
161 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo,
162                                             uint64_t Address,
163                                             const void *Decoder) {
164   return decodeRegisterClass(Inst, RegNo, XRegsNoX0);
165 }
166 
167 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass
168 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass
169 
170 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo,
171                                             uint64_t Address,
172                                             const void *Decoder) {
173   return decodeRegisterClass(Inst, RegNo, SPERegs);
174 }
175 
176 static DecodeStatus DecodeACCRCRegisterClass(MCInst &Inst, uint64_t RegNo,
177                                              uint64_t Address,
178                                              const void *Decoder) {
179   return decodeRegisterClass(Inst, RegNo, ACCRegs);
180 }
181 
182 static DecodeStatus DecodeVSRpRCRegisterClass(MCInst &Inst, uint64_t RegNo,
183                                               uint64_t Address,
184                                               const void *Decoder) {
185   return decodeRegisterClass(Inst, RegNo, VSRpRegs);
186 }
187 
188 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass
189 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass
190 
191 template<unsigned N>
192 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm,
193                                       int64_t Address, const void *Decoder) {
194   assert(isUInt<N>(Imm) && "Invalid immediate");
195   Inst.addOperand(MCOperand::createImm(Imm));
196   return MCDisassembler::Success;
197 }
198 
199 template<unsigned N>
200 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm,
201                                       int64_t Address, const void *Decoder) {
202   assert(isUInt<N>(Imm) && "Invalid immediate");
203   Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm)));
204   return MCDisassembler::Success;
205 }
206 
207 static DecodeStatus decodeImmZeroOperand(MCInst &Inst, uint64_t Imm,
208                                          int64_t Address, const void *Decoder) {
209   if (Imm != 0)
210     return MCDisassembler::Fail;
211   Inst.addOperand(MCOperand::createImm(Imm));
212   return MCDisassembler::Success;
213 }
214 
215 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm,
216                                         int64_t Address, const void *Decoder) {
217   // Decode the memri field (imm, reg), which has the low 16-bits as the
218   // displacement and the next 5 bits as the register #.
219 
220   uint64_t Base = Imm >> 16;
221   uint64_t Disp = Imm & 0xFFFF;
222 
223   assert(Base < 32 && "Invalid base register");
224 
225   switch (Inst.getOpcode()) {
226   default: break;
227   case PPC::LBZU:
228   case PPC::LHAU:
229   case PPC::LHZU:
230   case PPC::LWZU:
231   case PPC::LFSU:
232   case PPC::LFDU:
233     // Add the tied output operand.
234     Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
235     break;
236   case PPC::STBU:
237   case PPC::STHU:
238   case PPC::STWU:
239   case PPC::STFSU:
240   case PPC::STFDU:
241     Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
242     break;
243   }
244 
245   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp)));
246   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
247   return MCDisassembler::Success;
248 }
249 
250 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm,
251                                          int64_t Address, const void *Decoder) {
252   // Decode the memrix field (imm, reg), which has the low 14-bits as the
253   // displacement and the next 5 bits as the register #.
254 
255   uint64_t Base = Imm >> 14;
256   uint64_t Disp = Imm & 0x3FFF;
257 
258   assert(Base < 32 && "Invalid base register");
259 
260   if (Inst.getOpcode() == PPC::LDU)
261     // Add the tied output operand.
262     Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
263   else if (Inst.getOpcode() == PPC::STDU)
264     Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base]));
265 
266   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2)));
267   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
268   return MCDisassembler::Success;
269 }
270 
271 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm,
272                                          int64_t Address, const void *Decoder) {
273   // Decode the memrix16 field (imm, reg), which has the low 12-bits as the
274   // displacement with 16-byte aligned, and the next 5 bits as the register #.
275 
276   uint64_t Base = Imm >> 12;
277   uint64_t Disp = Imm & 0xFFF;
278 
279   assert(Base < 32 && "Invalid base register");
280 
281   Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4)));
282   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
283   return MCDisassembler::Success;
284 }
285 
286 static DecodeStatus decodeMemRI34PCRelOperands(MCInst &Inst, uint64_t Imm,
287                                                int64_t Address,
288                                                const void *Decoder) {
289   // Decode the memri34_pcrel field (imm, reg), which has the low 34-bits as the
290   // displacement, and the next 5 bits as an immediate 0.
291   uint64_t Base = Imm >> 34;
292   uint64_t Disp = Imm & 0x3FFFFFFFFUL;
293 
294   assert(Base < 32 && "Invalid base register");
295 
296   Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
297   return decodeImmZeroOperand(Inst, Base, Address, Decoder);
298 }
299 
300 static DecodeStatus decodeMemRI34Operands(MCInst &Inst, uint64_t Imm,
301                                           int64_t Address,
302                                           const void *Decoder) {
303   // Decode the memri34 field (imm, reg), which has the low 34-bits as the
304   // displacement, and the next 5 bits as the register #.
305   uint64_t Base = Imm >> 34;
306   uint64_t Disp = Imm & 0x3FFFFFFFFUL;
307 
308   assert(Base < 32 && "Invalid base register");
309 
310   Inst.addOperand(MCOperand::createImm(SignExtend64<34>(Disp)));
311   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
312   return MCDisassembler::Success;
313 }
314 
315 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm,
316                                          int64_t Address, const void *Decoder) {
317   // Decode the spe8disp field (imm, reg), which has the low 5-bits as the
318   // displacement with 8-byte aligned, and the next 5 bits as the register #.
319 
320   uint64_t Base = Imm >> 5;
321   uint64_t Disp = Imm & 0x1F;
322 
323   assert(Base < 32 && "Invalid base register");
324 
325   Inst.addOperand(MCOperand::createImm(Disp << 3));
326   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
327   return MCDisassembler::Success;
328 }
329 
330 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm,
331                                          int64_t Address, const void *Decoder) {
332   // Decode the spe4disp field (imm, reg), which has the low 5-bits as the
333   // displacement with 4-byte aligned, and the next 5 bits as the register #.
334 
335   uint64_t Base = Imm >> 5;
336   uint64_t Disp = Imm & 0x1F;
337 
338   assert(Base < 32 && "Invalid base register");
339 
340   Inst.addOperand(MCOperand::createImm(Disp << 2));
341   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
342   return MCDisassembler::Success;
343 }
344 
345 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm,
346                                          int64_t Address, const void *Decoder) {
347   // Decode the spe2disp field (imm, reg), which has the low 5-bits as the
348   // displacement with 2-byte aligned, and the next 5 bits as the register #.
349 
350   uint64_t Base = Imm >> 5;
351   uint64_t Disp = Imm & 0x1F;
352 
353   assert(Base < 32 && "Invalid base register");
354 
355   Inst.addOperand(MCOperand::createImm(Disp << 1));
356   Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base]));
357   return MCDisassembler::Success;
358 }
359 
360 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm,
361                                         int64_t Address, const void *Decoder) {
362   // The cr bit encoding is 0x80 >> cr_reg_num.
363 
364   unsigned Zeros = countTrailingZeros(Imm);
365   assert(Zeros < 8 && "Invalid CR bit value");
366 
367   Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros]));
368   return MCDisassembler::Success;
369 }
370 
371 #include "PPCGenDisassemblerTables.inc"
372 
373 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size,
374                                              ArrayRef<uint8_t> Bytes,
375                                              uint64_t Address,
376                                              raw_ostream &CS) const {
377   auto *ReadFunc = IsLittleEndian ? support::endian::read32le
378                                   : support::endian::read32be;
379 
380   // If this is an 8-byte prefixed instruction, handle it here.
381   // Note: prefixed instructions aren't technically 8-byte entities - the prefix
382   //       appears in memory at an address 4 bytes prior to that of the base
383   //       instruction regardless of endianness. So we read the two pieces and
384   //       rebuild the 8-byte instruction.
385   // TODO: In this function we call decodeInstruction several times with
386   //       different decoder tables. It may be possible to only call once by
387   //       looking at the top 6 bits of the instruction.
388   if (STI.getFeatureBits()[PPC::FeaturePrefixInstrs] && Bytes.size() >= 8) {
389     uint32_t Prefix = ReadFunc(Bytes.data());
390     uint32_t BaseInst = ReadFunc(Bytes.data() + 4);
391     uint64_t Inst = BaseInst | (uint64_t)Prefix << 32;
392     DecodeStatus result = decodeInstruction(DecoderTable64, MI, Inst, Address,
393                                             this, STI);
394     if (result != MCDisassembler::Fail) {
395       Size = 8;
396       return result;
397     }
398   }
399 
400   // Get the four bytes of the instruction.
401   Size = 4;
402   if (Bytes.size() < 4) {
403     Size = 0;
404     return MCDisassembler::Fail;
405   }
406 
407   // Read the instruction in the proper endianness.
408   uint64_t Inst = ReadFunc(Bytes.data());
409 
410   if (STI.getFeatureBits()[PPC::FeatureSPE]) {
411     DecodeStatus result =
412         decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI);
413     if (result != MCDisassembler::Fail)
414       return result;
415   }
416 
417   return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI);
418 }
419