1 //===------ PPCDisassembler.cpp - Disassembler for PowerPC ------*- C++ -*-===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCTargetDesc.h" 10 #include "llvm/MC/MCDisassembler/MCDisassembler.h" 11 #include "llvm/MC/MCFixedLenDisassembler.h" 12 #include "llvm/MC/MCInst.h" 13 #include "llvm/MC/MCSubtargetInfo.h" 14 #include "llvm/Support/Endian.h" 15 #include "llvm/Support/TargetRegistry.h" 16 17 using namespace llvm; 18 19 DEFINE_PPC_REGCLASSES; 20 21 #define DEBUG_TYPE "ppc-disassembler" 22 23 typedef MCDisassembler::DecodeStatus DecodeStatus; 24 25 namespace { 26 class PPCDisassembler : public MCDisassembler { 27 bool IsLittleEndian; 28 29 public: 30 PPCDisassembler(const MCSubtargetInfo &STI, MCContext &Ctx, 31 bool IsLittleEndian) 32 : MCDisassembler(STI, Ctx), IsLittleEndian(IsLittleEndian) {} 33 34 DecodeStatus getInstruction(MCInst &Instr, uint64_t &Size, 35 ArrayRef<uint8_t> Bytes, uint64_t Address, 36 raw_ostream &VStream, 37 raw_ostream &CStream) const override; 38 }; 39 } // end anonymous namespace 40 41 static MCDisassembler *createPPCDisassembler(const Target &T, 42 const MCSubtargetInfo &STI, 43 MCContext &Ctx) { 44 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/false); 45 } 46 47 static MCDisassembler *createPPCLEDisassembler(const Target &T, 48 const MCSubtargetInfo &STI, 49 MCContext &Ctx) { 50 return new PPCDisassembler(STI, Ctx, /*IsLittleEndian=*/true); 51 } 52 53 extern "C" void LLVMInitializePowerPCDisassembler() { 54 // Register the disassembler for each target. 55 TargetRegistry::RegisterMCDisassembler(getThePPC32Target(), 56 createPPCDisassembler); 57 TargetRegistry::RegisterMCDisassembler(getThePPC64Target(), 58 createPPCDisassembler); 59 TargetRegistry::RegisterMCDisassembler(getThePPC64LETarget(), 60 createPPCLEDisassembler); 61 } 62 63 // FIXME: These can be generated by TableGen from the existing register 64 // encoding values! 65 66 template <std::size_t N> 67 static DecodeStatus decodeRegisterClass(MCInst &Inst, uint64_t RegNo, 68 const MCPhysReg (&Regs)[N]) { 69 assert(RegNo < N && "Invalid register number"); 70 Inst.addOperand(MCOperand::createReg(Regs[RegNo])); 71 return MCDisassembler::Success; 72 } 73 74 static DecodeStatus DecodeCRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 75 uint64_t Address, 76 const void *Decoder) { 77 return decodeRegisterClass(Inst, RegNo, CRRegs); 78 } 79 80 static DecodeStatus DecodeCRRC0RegisterClass(MCInst &Inst, uint64_t RegNo, 81 uint64_t Address, 82 const void *Decoder) { 83 return decodeRegisterClass(Inst, RegNo, CRRegs); 84 } 85 86 static DecodeStatus DecodeCRBITRCRegisterClass(MCInst &Inst, uint64_t RegNo, 87 uint64_t Address, 88 const void *Decoder) { 89 return decodeRegisterClass(Inst, RegNo, CRBITRegs); 90 } 91 92 static DecodeStatus DecodeF4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 93 uint64_t Address, 94 const void *Decoder) { 95 return decodeRegisterClass(Inst, RegNo, FRegs); 96 } 97 98 static DecodeStatus DecodeF8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 99 uint64_t Address, 100 const void *Decoder) { 101 return decodeRegisterClass(Inst, RegNo, FRegs); 102 } 103 104 static DecodeStatus DecodeVFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 105 uint64_t Address, 106 const void *Decoder) { 107 return decodeRegisterClass(Inst, RegNo, VFRegs); 108 } 109 110 static DecodeStatus DecodeVRRCRegisterClass(MCInst &Inst, uint64_t RegNo, 111 uint64_t Address, 112 const void *Decoder) { 113 return decodeRegisterClass(Inst, RegNo, VRegs); 114 } 115 116 static DecodeStatus DecodeVSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 117 uint64_t Address, 118 const void *Decoder) { 119 return decodeRegisterClass(Inst, RegNo, VSRegs); 120 } 121 122 static DecodeStatus DecodeVSFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 123 uint64_t Address, 124 const void *Decoder) { 125 return decodeRegisterClass(Inst, RegNo, VSFRegs); 126 } 127 128 static DecodeStatus DecodeVSSRCRegisterClass(MCInst &Inst, uint64_t RegNo, 129 uint64_t Address, 130 const void *Decoder) { 131 return decodeRegisterClass(Inst, RegNo, VSSRegs); 132 } 133 134 static DecodeStatus DecodeGPRCRegisterClass(MCInst &Inst, uint64_t RegNo, 135 uint64_t Address, 136 const void *Decoder) { 137 return decodeRegisterClass(Inst, RegNo, RRegs); 138 } 139 140 static DecodeStatus DecodeGPRC_NOR0RegisterClass(MCInst &Inst, uint64_t RegNo, 141 uint64_t Address, 142 const void *Decoder) { 143 return decodeRegisterClass(Inst, RegNo, RRegsNoR0); 144 } 145 146 static DecodeStatus DecodeG8RCRegisterClass(MCInst &Inst, uint64_t RegNo, 147 uint64_t Address, 148 const void *Decoder) { 149 return decodeRegisterClass(Inst, RegNo, XRegs); 150 } 151 152 static DecodeStatus DecodeG8RC_NOX0RegisterClass(MCInst &Inst, uint64_t RegNo, 153 uint64_t Address, 154 const void *Decoder) { 155 return decodeRegisterClass(Inst, RegNo, XRegsNoX0); 156 } 157 158 #define DecodePointerLikeRegClass0 DecodeGPRCRegisterClass 159 #define DecodePointerLikeRegClass1 DecodeGPRC_NOR0RegisterClass 160 161 static DecodeStatus DecodeQFRCRegisterClass(MCInst &Inst, uint64_t RegNo, 162 uint64_t Address, 163 const void *Decoder) { 164 return decodeRegisterClass(Inst, RegNo, QFRegs); 165 } 166 167 static DecodeStatus DecodeSPE4RCRegisterClass(MCInst &Inst, uint64_t RegNo, 168 uint64_t Address, 169 const void *Decoder) { 170 return decodeRegisterClass(Inst, RegNo, RRegs); 171 } 172 173 static DecodeStatus DecodeSPERCRegisterClass(MCInst &Inst, uint64_t RegNo, 174 uint64_t Address, 175 const void *Decoder) { 176 return decodeRegisterClass(Inst, RegNo, SPERegs); 177 } 178 179 #define DecodeQSRCRegisterClass DecodeQFRCRegisterClass 180 #define DecodeQBRCRegisterClass DecodeQFRCRegisterClass 181 182 template<unsigned N> 183 static DecodeStatus decodeUImmOperand(MCInst &Inst, uint64_t Imm, 184 int64_t Address, const void *Decoder) { 185 assert(isUInt<N>(Imm) && "Invalid immediate"); 186 Inst.addOperand(MCOperand::createImm(Imm)); 187 return MCDisassembler::Success; 188 } 189 190 template<unsigned N> 191 static DecodeStatus decodeSImmOperand(MCInst &Inst, uint64_t Imm, 192 int64_t Address, const void *Decoder) { 193 assert(isUInt<N>(Imm) && "Invalid immediate"); 194 Inst.addOperand(MCOperand::createImm(SignExtend64<N>(Imm))); 195 return MCDisassembler::Success; 196 } 197 198 static DecodeStatus decodeMemRIOperands(MCInst &Inst, uint64_t Imm, 199 int64_t Address, const void *Decoder) { 200 // Decode the memri field (imm, reg), which has the low 16-bits as the 201 // displacement and the next 5 bits as the register #. 202 203 uint64_t Base = Imm >> 16; 204 uint64_t Disp = Imm & 0xFFFF; 205 206 assert(Base < 32 && "Invalid base register"); 207 208 switch (Inst.getOpcode()) { 209 default: break; 210 case PPC::LBZU: 211 case PPC::LHAU: 212 case PPC::LHZU: 213 case PPC::LWZU: 214 case PPC::LFSU: 215 case PPC::LFDU: 216 // Add the tied output operand. 217 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 218 break; 219 case PPC::STBU: 220 case PPC::STHU: 221 case PPC::STWU: 222 case PPC::STFSU: 223 case PPC::STFDU: 224 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 225 break; 226 } 227 228 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp))); 229 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 230 return MCDisassembler::Success; 231 } 232 233 static DecodeStatus decodeMemRIXOperands(MCInst &Inst, uint64_t Imm, 234 int64_t Address, const void *Decoder) { 235 // Decode the memrix field (imm, reg), which has the low 14-bits as the 236 // displacement and the next 5 bits as the register #. 237 238 uint64_t Base = Imm >> 14; 239 uint64_t Disp = Imm & 0x3FFF; 240 241 assert(Base < 32 && "Invalid base register"); 242 243 if (Inst.getOpcode() == PPC::LDU) 244 // Add the tied output operand. 245 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 246 else if (Inst.getOpcode() == PPC::STDU) 247 Inst.insert(Inst.begin(), MCOperand::createReg(RRegsNoR0[Base])); 248 249 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 2))); 250 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 251 return MCDisassembler::Success; 252 } 253 254 static DecodeStatus decodeMemRIX16Operands(MCInst &Inst, uint64_t Imm, 255 int64_t Address, const void *Decoder) { 256 // Decode the memrix16 field (imm, reg), which has the low 12-bits as the 257 // displacement with 16-byte aligned, and the next 5 bits as the register #. 258 259 uint64_t Base = Imm >> 12; 260 uint64_t Disp = Imm & 0xFFF; 261 262 assert(Base < 32 && "Invalid base register"); 263 264 Inst.addOperand(MCOperand::createImm(SignExtend64<16>(Disp << 4))); 265 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 266 return MCDisassembler::Success; 267 } 268 269 static DecodeStatus decodeSPE8Operands(MCInst &Inst, uint64_t Imm, 270 int64_t Address, const void *Decoder) { 271 // Decode the spe8disp field (imm, reg), which has the low 5-bits as the 272 // displacement with 8-byte aligned, and the next 5 bits as the register #. 273 274 uint64_t Base = Imm >> 5; 275 uint64_t Disp = Imm & 0x1F; 276 277 assert(Base < 32 && "Invalid base register"); 278 279 Inst.addOperand(MCOperand::createImm(Disp << 3)); 280 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 281 return MCDisassembler::Success; 282 } 283 284 static DecodeStatus decodeSPE4Operands(MCInst &Inst, uint64_t Imm, 285 int64_t Address, const void *Decoder) { 286 // Decode the spe4disp field (imm, reg), which has the low 5-bits as the 287 // displacement with 4-byte aligned, and the next 5 bits as the register #. 288 289 uint64_t Base = Imm >> 5; 290 uint64_t Disp = Imm & 0x1F; 291 292 assert(Base < 32 && "Invalid base register"); 293 294 Inst.addOperand(MCOperand::createImm(Disp << 2)); 295 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 296 return MCDisassembler::Success; 297 } 298 299 static DecodeStatus decodeSPE2Operands(MCInst &Inst, uint64_t Imm, 300 int64_t Address, const void *Decoder) { 301 // Decode the spe2disp field (imm, reg), which has the low 5-bits as the 302 // displacement with 2-byte aligned, and the next 5 bits as the register #. 303 304 uint64_t Base = Imm >> 5; 305 uint64_t Disp = Imm & 0x1F; 306 307 assert(Base < 32 && "Invalid base register"); 308 309 Inst.addOperand(MCOperand::createImm(Disp << 1)); 310 Inst.addOperand(MCOperand::createReg(RRegsNoR0[Base])); 311 return MCDisassembler::Success; 312 } 313 314 static DecodeStatus decodeCRBitMOperand(MCInst &Inst, uint64_t Imm, 315 int64_t Address, const void *Decoder) { 316 // The cr bit encoding is 0x80 >> cr_reg_num. 317 318 unsigned Zeros = countTrailingZeros(Imm); 319 assert(Zeros < 8 && "Invalid CR bit value"); 320 321 Inst.addOperand(MCOperand::createReg(CRRegs[7 - Zeros])); 322 return MCDisassembler::Success; 323 } 324 325 #include "PPCGenDisassemblerTables.inc" 326 327 DecodeStatus PPCDisassembler::getInstruction(MCInst &MI, uint64_t &Size, 328 ArrayRef<uint8_t> Bytes, 329 uint64_t Address, raw_ostream &OS, 330 raw_ostream &CS) const { 331 // Get the four bytes of the instruction. 332 Size = 4; 333 if (Bytes.size() < 4) { 334 Size = 0; 335 return MCDisassembler::Fail; 336 } 337 338 // Read the instruction in the proper endianness. 339 uint32_t Inst = IsLittleEndian ? support::endian::read32le(Bytes.data()) 340 : support::endian::read32be(Bytes.data()); 341 342 if (STI.getFeatureBits()[PPC::FeatureQPX]) { 343 DecodeStatus result = 344 decodeInstruction(DecoderTableQPX32, MI, Inst, Address, this, STI); 345 if (result != MCDisassembler::Fail) 346 return result; 347 } else if (STI.getFeatureBits()[PPC::FeatureSPE]) { 348 DecodeStatus result = 349 decodeInstruction(DecoderTableSPE32, MI, Inst, Address, this, STI); 350 if (result != MCDisassembler::Fail) 351 return result; 352 } 353 354 return decodeInstruction(DecoderTable32, MI, Inst, Address, this, STI); 355 } 356 357