1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 static const MCPhysReg RRegs[32] = {
35   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
36   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
37   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
38   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42   PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 };
44 static const MCPhysReg RRegsNoR0[32] = {
45   PPC::ZERO,
46             PPC::R1,  PPC::R2,  PPC::R3,
47   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
48   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
49   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53   PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 };
55 static const MCPhysReg XRegs[32] = {
56   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
57   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
58   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
59   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63   PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 };
65 static const MCPhysReg XRegsNoX0[32] = {
66   PPC::ZERO8,
67             PPC::X1,  PPC::X2,  PPC::X3,
68   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
69   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
70   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74   PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 };
76 static const MCPhysReg FRegs[32] = {
77   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
78   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
79   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
80   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84   PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 };
86 static const MCPhysReg VRegs[32] = {
87   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
88   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
89   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
90   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
91   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
92   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
93   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
94   PPC::V28, PPC::V29, PPC::V30, PPC::V31
95 };
96 static const MCPhysReg VSRegs[64] = {
97   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
98   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
99   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
100   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
101   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
102   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
103   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
104   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
105 
106   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
107   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
108   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
109   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
110   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
111   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
112   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
113   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
114 };
115 static const MCPhysReg VSFRegs[64] = {
116   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
117   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
118   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
119   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
120   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
121   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
122   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
123   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
124 
125   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
126   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
127   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
128   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
129   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
130   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
131   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
132   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
133 };
134 static const MCPhysReg VSSRegs[64] = {
135   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
136   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
137   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
138   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
139   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
140   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
141   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
142   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
143 
144   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
145   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
146   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
147   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
148   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
149   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
150   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
151   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
152 };
153 static unsigned QFRegs[32] = {
154   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
155   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
156   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
157   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
158   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
159   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
160   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
161   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
162 };
163 static const MCPhysReg CRBITRegs[32] = {
164   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
165   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
166   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
167   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
168   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
169   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
170   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
171   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
172 };
173 static const MCPhysReg CRRegs[8] = {
174   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
175   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
176 };
177 
178 // Evaluate an expression containing condition register
179 // or condition register field symbols.  Returns positive
180 // value on success, or -1 on error.
181 static int64_t
182 EvaluateCRExpr(const MCExpr *E) {
183   switch (E->getKind()) {
184   case MCExpr::Target:
185     return -1;
186 
187   case MCExpr::Constant: {
188     int64_t Res = cast<MCConstantExpr>(E)->getValue();
189     return Res < 0 ? -1 : Res;
190   }
191 
192   case MCExpr::SymbolRef: {
193     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
194     StringRef Name = SRE->getSymbol().getName();
195 
196     if (Name == "lt") return 0;
197     if (Name == "gt") return 1;
198     if (Name == "eq") return 2;
199     if (Name == "so") return 3;
200     if (Name == "un") return 3;
201 
202     if (Name == "cr0") return 0;
203     if (Name == "cr1") return 1;
204     if (Name == "cr2") return 2;
205     if (Name == "cr3") return 3;
206     if (Name == "cr4") return 4;
207     if (Name == "cr5") return 5;
208     if (Name == "cr6") return 6;
209     if (Name == "cr7") return 7;
210 
211     return -1;
212   }
213 
214   case MCExpr::Unary:
215     return -1;
216 
217   case MCExpr::Binary: {
218     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
219     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
220     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
221     int64_t Res;
222 
223     if (LHSVal < 0 || RHSVal < 0)
224       return -1;
225 
226     switch (BE->getOpcode()) {
227     default: return -1;
228     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
229     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
230     }
231 
232     return Res < 0 ? -1 : Res;
233   }
234   }
235 
236   llvm_unreachable("Invalid expression kind!");
237 }
238 
239 namespace {
240 
241 struct PPCOperand;
242 
243 class PPCAsmParser : public MCTargetAsmParser {
244   const MCInstrInfo &MII;
245   bool IsPPC64;
246   bool IsDarwin;
247 
248   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
249   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
250 
251   bool isPPC64() const { return IsPPC64; }
252   bool isDarwin() const { return IsDarwin; }
253 
254   bool MatchRegisterName(const AsmToken &Tok,
255                          unsigned &RegNo, int64_t &IntVal);
256 
257   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
258 
259   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
260                                         PPCMCExpr::VariantKind &Variant);
261   const MCExpr *FixupVariantKind(const MCExpr *E);
262   bool ParseExpression(const MCExpr *&EVal);
263   bool ParseDarwinExpression(const MCExpr *&EVal);
264 
265   bool ParseOperand(OperandVector &Operands);
266 
267   bool ParseDirectiveWord(unsigned Size, SMLoc L);
268   bool ParseDirectiveTC(unsigned Size, SMLoc L);
269   bool ParseDirectiveMachine(SMLoc L);
270   bool ParseDarwinDirectiveMachine(SMLoc L);
271   bool ParseDirectiveAbiVersion(SMLoc L);
272   bool ParseDirectiveLocalEntry(SMLoc L);
273 
274   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
275                                OperandVector &Operands, MCStreamer &Out,
276                                uint64_t &ErrorInfo,
277                                bool MatchingInlineAsm) override;
278 
279   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
280 
281   /// @name Auto-generated Match Functions
282   /// {
283 
284 #define GET_ASSEMBLER_HEADER
285 #include "PPCGenAsmMatcher.inc"
286 
287   /// }
288 
289 
290 public:
291   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
292                const MCInstrInfo &MII, const MCTargetOptions &Options)
293     : MCTargetAsmParser(Options, STI), MII(MII) {
294     // Check for 64-bit vs. 32-bit pointer mode.
295     const Triple &TheTriple = STI.getTargetTriple();
296     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
297                TheTriple.getArch() == Triple::ppc64le);
298     IsDarwin = TheTriple.isMacOSX();
299     // Initialize the set of available features.
300     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
301   }
302 
303   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
304                         SMLoc NameLoc, OperandVector &Operands) override;
305 
306   bool ParseDirective(AsmToken DirectiveID) override;
307 
308   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
309                                       unsigned Kind) override;
310 
311   const MCExpr *applyModifierToExpr(const MCExpr *E,
312                                     MCSymbolRefExpr::VariantKind,
313                                     MCContext &Ctx) override;
314 };
315 
316 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
317 /// instruction.
318 struct PPCOperand : public MCParsedAsmOperand {
319   enum KindTy {
320     Token,
321     Immediate,
322     ContextImmediate,
323     Expression,
324     TLSRegister
325   } Kind;
326 
327   SMLoc StartLoc, EndLoc;
328   bool IsPPC64;
329 
330   struct TokOp {
331     const char *Data;
332     unsigned Length;
333   };
334 
335   struct ImmOp {
336     int64_t Val;
337   };
338 
339   struct ExprOp {
340     const MCExpr *Val;
341     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
342   };
343 
344   struct TLSRegOp {
345     const MCSymbolRefExpr *Sym;
346   };
347 
348   union {
349     struct TokOp Tok;
350     struct ImmOp Imm;
351     struct ExprOp Expr;
352     struct TLSRegOp TLSReg;
353   };
354 
355   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
356 public:
357   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
358     Kind = o.Kind;
359     StartLoc = o.StartLoc;
360     EndLoc = o.EndLoc;
361     IsPPC64 = o.IsPPC64;
362     switch (Kind) {
363     case Token:
364       Tok = o.Tok;
365       break;
366     case Immediate:
367     case ContextImmediate:
368       Imm = o.Imm;
369       break;
370     case Expression:
371       Expr = o.Expr;
372       break;
373     case TLSRegister:
374       TLSReg = o.TLSReg;
375       break;
376     }
377   }
378 
379   // Disable use of sized deallocation due to overallocation of PPCOperand
380   // objects in CreateTokenWithStringCopy.
381   void operator delete(void *p) { ::operator delete(p); }
382 
383   /// getStartLoc - Get the location of the first token of this operand.
384   SMLoc getStartLoc() const override { return StartLoc; }
385 
386   /// getEndLoc - Get the location of the last token of this operand.
387   SMLoc getEndLoc() const override { return EndLoc; }
388 
389   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
390   bool isPPC64() const { return IsPPC64; }
391 
392   int64_t getImm() const {
393     assert(Kind == Immediate && "Invalid access!");
394     return Imm.Val;
395   }
396   int64_t getImmS16Context() const {
397     assert((Kind == Immediate || Kind == ContextImmediate) &&
398            "Invalid access!");
399     if (Kind == Immediate)
400       return Imm.Val;
401     return static_cast<int16_t>(Imm.Val);
402   }
403   int64_t getImmU16Context() const {
404     assert((Kind == Immediate || Kind == ContextImmediate) &&
405            "Invalid access!");
406     return Imm.Val;
407   }
408 
409   const MCExpr *getExpr() const {
410     assert(Kind == Expression && "Invalid access!");
411     return Expr.Val;
412   }
413 
414   int64_t getExprCRVal() const {
415     assert(Kind == Expression && "Invalid access!");
416     return Expr.CRVal;
417   }
418 
419   const MCExpr *getTLSReg() const {
420     assert(Kind == TLSRegister && "Invalid access!");
421     return TLSReg.Sym;
422   }
423 
424   unsigned getReg() const override {
425     assert(isRegNumber() && "Invalid access!");
426     return (unsigned) Imm.Val;
427   }
428 
429   unsigned getVSReg() const {
430     assert(isVSRegNumber() && "Invalid access!");
431     return (unsigned) Imm.Val;
432   }
433 
434   unsigned getCCReg() const {
435     assert(isCCRegNumber() && "Invalid access!");
436     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
437   }
438 
439   unsigned getCRBit() const {
440     assert(isCRBitNumber() && "Invalid access!");
441     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
442   }
443 
444   unsigned getCRBitMask() const {
445     assert(isCRBitMask() && "Invalid access!");
446     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
447   }
448 
449   bool isToken() const override { return Kind == Token; }
450   bool isImm() const override {
451     return Kind == Immediate || Kind == Expression;
452   }
453   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
454   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
455   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
456   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
457   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
458   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
459   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
460   bool isU6ImmX2() const { return Kind == Immediate &&
461                                   isUInt<6>(getImm()) &&
462                                   (getImm() & 1) == 0; }
463   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
464   bool isU7ImmX4() const { return Kind == Immediate &&
465                                   isUInt<7>(getImm()) &&
466                                   (getImm() & 3) == 0; }
467   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
468   bool isU8ImmX8() const { return Kind == Immediate &&
469                                   isUInt<8>(getImm()) &&
470                                   (getImm() & 7) == 0; }
471 
472   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
473   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
474   bool isU16Imm() const {
475     switch (Kind) {
476       case Expression:
477         return true;
478       case Immediate:
479       case ContextImmediate:
480         return isUInt<16>(getImmU16Context());
481       default:
482         return false;
483     }
484   }
485   bool isS16Imm() const {
486     switch (Kind) {
487       case Expression:
488         return true;
489       case Immediate:
490       case ContextImmediate:
491         return isInt<16>(getImmS16Context());
492       default:
493         return false;
494     }
495   }
496   bool isS16ImmX4() const { return Kind == Expression ||
497                                    (Kind == Immediate && isInt<16>(getImm()) &&
498                                     (getImm() & 3) == 0); }
499   bool isS16ImmX16() const { return Kind == Expression ||
500                                     (Kind == Immediate && isInt<16>(getImm()) &&
501                                      (getImm() & 15) == 0); }
502   bool isS17Imm() const {
503     switch (Kind) {
504       case Expression:
505         return true;
506       case Immediate:
507       case ContextImmediate:
508         return isInt<17>(getImmS16Context());
509       default:
510         return false;
511     }
512   }
513   bool isTLSReg() const { return Kind == TLSRegister; }
514   bool isDirectBr() const {
515     if (Kind == Expression)
516       return true;
517     if (Kind != Immediate)
518       return false;
519     // Operand must be 64-bit aligned, signed 27-bit immediate.
520     if ((getImm() & 3) != 0)
521       return false;
522     if (isInt<26>(getImm()))
523       return true;
524     if (!IsPPC64) {
525       // In 32-bit mode, large 32-bit quantities wrap around.
526       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
527         return true;
528     }
529     return false;
530   }
531   bool isCondBr() const { return Kind == Expression ||
532                                  (Kind == Immediate && isInt<16>(getImm()) &&
533                                   (getImm() & 3) == 0); }
534   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
535   bool isVSRegNumber() const {
536     return Kind == Immediate && isUInt<6>(getImm());
537   }
538   bool isCCRegNumber() const { return (Kind == Expression
539                                        && isUInt<3>(getExprCRVal())) ||
540                                       (Kind == Immediate
541                                        && isUInt<3>(getImm())); }
542   bool isCRBitNumber() const { return (Kind == Expression
543                                        && isUInt<5>(getExprCRVal())) ||
544                                       (Kind == Immediate
545                                        && isUInt<5>(getImm())); }
546   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
547                                     isPowerOf2_32(getImm()); }
548   bool isATBitsAsHint() const { return false; }
549   bool isMem() const override { return false; }
550   bool isReg() const override { return false; }
551 
552   void addRegOperands(MCInst &Inst, unsigned N) const {
553     llvm_unreachable("addRegOperands");
554   }
555 
556   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
557     assert(N == 1 && "Invalid number of operands!");
558     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
559   }
560 
561   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
562     assert(N == 1 && "Invalid number of operands!");
563     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
564   }
565 
566   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
567     assert(N == 1 && "Invalid number of operands!");
568     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
569   }
570 
571   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
572     assert(N == 1 && "Invalid number of operands!");
573     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
574   }
575 
576   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
577     if (isPPC64())
578       addRegG8RCOperands(Inst, N);
579     else
580       addRegGPRCOperands(Inst, N);
581   }
582 
583   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
584     if (isPPC64())
585       addRegG8RCNoX0Operands(Inst, N);
586     else
587       addRegGPRCNoR0Operands(Inst, N);
588   }
589 
590   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
591     assert(N == 1 && "Invalid number of operands!");
592     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
593   }
594 
595   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
596     assert(N == 1 && "Invalid number of operands!");
597     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
598   }
599 
600   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
601     assert(N == 1 && "Invalid number of operands!");
602     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
603   }
604 
605   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
606     assert(N == 1 && "Invalid number of operands!");
607     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
608   }
609 
610   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
611     assert(N == 1 && "Invalid number of operands!");
612     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
613   }
614 
615   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
616     assert(N == 1 && "Invalid number of operands!");
617     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
618   }
619 
620   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
621     assert(N == 1 && "Invalid number of operands!");
622     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
623   }
624 
625   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
626     assert(N == 1 && "Invalid number of operands!");
627     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
628   }
629 
630   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
631     assert(N == 1 && "Invalid number of operands!");
632     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
633   }
634 
635   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
636     assert(N == 1 && "Invalid number of operands!");
637     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
638   }
639 
640   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
641     assert(N == 1 && "Invalid number of operands!");
642     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
643   }
644 
645   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
646     assert(N == 1 && "Invalid number of operands!");
647     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
648   }
649 
650   void addImmOperands(MCInst &Inst, unsigned N) const {
651     assert(N == 1 && "Invalid number of operands!");
652     if (Kind == Immediate)
653       Inst.addOperand(MCOperand::createImm(getImm()));
654     else
655       Inst.addOperand(MCOperand::createExpr(getExpr()));
656   }
657 
658   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
659     assert(N == 1 && "Invalid number of operands!");
660     switch (Kind) {
661       case Immediate:
662         Inst.addOperand(MCOperand::createImm(getImm()));
663         break;
664       case ContextImmediate:
665         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
666         break;
667       default:
668         Inst.addOperand(MCOperand::createExpr(getExpr()));
669         break;
670     }
671   }
672 
673   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
674     assert(N == 1 && "Invalid number of operands!");
675     switch (Kind) {
676       case Immediate:
677         Inst.addOperand(MCOperand::createImm(getImm()));
678         break;
679       case ContextImmediate:
680         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
681         break;
682       default:
683         Inst.addOperand(MCOperand::createExpr(getExpr()));
684         break;
685     }
686   }
687 
688   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
689     assert(N == 1 && "Invalid number of operands!");
690     if (Kind == Immediate)
691       Inst.addOperand(MCOperand::createImm(getImm() / 4));
692     else
693       Inst.addOperand(MCOperand::createExpr(getExpr()));
694   }
695 
696   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
697     assert(N == 1 && "Invalid number of operands!");
698     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
699   }
700 
701   StringRef getToken() const {
702     assert(Kind == Token && "Invalid access!");
703     return StringRef(Tok.Data, Tok.Length);
704   }
705 
706   void print(raw_ostream &OS) const override;
707 
708   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
709                                                  bool IsPPC64) {
710     auto Op = make_unique<PPCOperand>(Token);
711     Op->Tok.Data = Str.data();
712     Op->Tok.Length = Str.size();
713     Op->StartLoc = S;
714     Op->EndLoc = S;
715     Op->IsPPC64 = IsPPC64;
716     return Op;
717   }
718 
719   static std::unique_ptr<PPCOperand>
720   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
721     // Allocate extra memory for the string and copy it.
722     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
723     // deleter which will destroy them by simply using "delete", not correctly
724     // calling operator delete on this extra memory after calling the dtor
725     // explicitly.
726     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
727     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
728     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
729     Op->Tok.Length = Str.size();
730     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
731     Op->StartLoc = S;
732     Op->EndLoc = S;
733     Op->IsPPC64 = IsPPC64;
734     return Op;
735   }
736 
737   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
738                                                bool IsPPC64) {
739     auto Op = make_unique<PPCOperand>(Immediate);
740     Op->Imm.Val = Val;
741     Op->StartLoc = S;
742     Op->EndLoc = E;
743     Op->IsPPC64 = IsPPC64;
744     return Op;
745   }
746 
747   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
748                                                 SMLoc E, bool IsPPC64) {
749     auto Op = make_unique<PPCOperand>(Expression);
750     Op->Expr.Val = Val;
751     Op->Expr.CRVal = EvaluateCRExpr(Val);
752     Op->StartLoc = S;
753     Op->EndLoc = E;
754     Op->IsPPC64 = IsPPC64;
755     return Op;
756   }
757 
758   static std::unique_ptr<PPCOperand>
759   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
760     auto Op = make_unique<PPCOperand>(TLSRegister);
761     Op->TLSReg.Sym = Sym;
762     Op->StartLoc = S;
763     Op->EndLoc = E;
764     Op->IsPPC64 = IsPPC64;
765     return Op;
766   }
767 
768   static std::unique_ptr<PPCOperand>
769   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
770     auto Op = make_unique<PPCOperand>(ContextImmediate);
771     Op->Imm.Val = Val;
772     Op->StartLoc = S;
773     Op->EndLoc = E;
774     Op->IsPPC64 = IsPPC64;
775     return Op;
776   }
777 
778   static std::unique_ptr<PPCOperand>
779   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
780     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
781       return CreateImm(CE->getValue(), S, E, IsPPC64);
782 
783     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
784       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
785         return CreateTLSReg(SRE, S, E, IsPPC64);
786 
787     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
788       int64_t Res;
789       if (TE->evaluateAsConstant(Res))
790         return CreateContextImm(Res, S, E, IsPPC64);
791     }
792 
793     return CreateExpr(Val, S, E, IsPPC64);
794   }
795 };
796 
797 } // end anonymous namespace.
798 
799 void PPCOperand::print(raw_ostream &OS) const {
800   switch (Kind) {
801   case Token:
802     OS << "'" << getToken() << "'";
803     break;
804   case Immediate:
805   case ContextImmediate:
806     OS << getImm();
807     break;
808   case Expression:
809     OS << *getExpr();
810     break;
811   case TLSRegister:
812     OS << *getTLSReg();
813     break;
814   }
815 }
816 
817 static void
818 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
819   if (Op.isImm()) {
820     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
821     return;
822   }
823   const MCExpr *Expr = Op.getExpr();
824   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
825     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
826       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
827       return;
828     }
829   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
830     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
831       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
832                                                  BinExpr->getLHS(), Ctx);
833       Inst.addOperand(MCOperand::createExpr(NE));
834       return;
835     }
836   }
837   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
838 }
839 
840 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
841                                       const OperandVector &Operands) {
842   int Opcode = Inst.getOpcode();
843   switch (Opcode) {
844   case PPC::DCBTx:
845   case PPC::DCBTT:
846   case PPC::DCBTSTx:
847   case PPC::DCBTSTT: {
848     MCInst TmpInst;
849     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
850                       PPC::DCBT : PPC::DCBTST);
851     TmpInst.addOperand(MCOperand::createImm(
852       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
853     TmpInst.addOperand(Inst.getOperand(0));
854     TmpInst.addOperand(Inst.getOperand(1));
855     Inst = TmpInst;
856     break;
857   }
858   case PPC::DCBTCT:
859   case PPC::DCBTDS: {
860     MCInst TmpInst;
861     TmpInst.setOpcode(PPC::DCBT);
862     TmpInst.addOperand(Inst.getOperand(2));
863     TmpInst.addOperand(Inst.getOperand(0));
864     TmpInst.addOperand(Inst.getOperand(1));
865     Inst = TmpInst;
866     break;
867   }
868   case PPC::DCBTSTCT:
869   case PPC::DCBTSTDS: {
870     MCInst TmpInst;
871     TmpInst.setOpcode(PPC::DCBTST);
872     TmpInst.addOperand(Inst.getOperand(2));
873     TmpInst.addOperand(Inst.getOperand(0));
874     TmpInst.addOperand(Inst.getOperand(1));
875     Inst = TmpInst;
876     break;
877   }
878   case PPC::DCBFx:
879   case PPC::DCBFL:
880   case PPC::DCBFLP: {
881     int L = 0;
882     if (Opcode == PPC::DCBFL)
883       L = 1;
884     else if (Opcode == PPC::DCBFLP)
885       L = 3;
886 
887     MCInst TmpInst;
888     TmpInst.setOpcode(PPC::DCBF);
889     TmpInst.addOperand(MCOperand::createImm(L));
890     TmpInst.addOperand(Inst.getOperand(0));
891     TmpInst.addOperand(Inst.getOperand(1));
892     Inst = TmpInst;
893     break;
894   }
895   case PPC::LAx: {
896     MCInst TmpInst;
897     TmpInst.setOpcode(PPC::LA);
898     TmpInst.addOperand(Inst.getOperand(0));
899     TmpInst.addOperand(Inst.getOperand(2));
900     TmpInst.addOperand(Inst.getOperand(1));
901     Inst = TmpInst;
902     break;
903   }
904   case PPC::SUBI: {
905     MCInst TmpInst;
906     TmpInst.setOpcode(PPC::ADDI);
907     TmpInst.addOperand(Inst.getOperand(0));
908     TmpInst.addOperand(Inst.getOperand(1));
909     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
910     Inst = TmpInst;
911     break;
912   }
913   case PPC::SUBIS: {
914     MCInst TmpInst;
915     TmpInst.setOpcode(PPC::ADDIS);
916     TmpInst.addOperand(Inst.getOperand(0));
917     TmpInst.addOperand(Inst.getOperand(1));
918     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
919     Inst = TmpInst;
920     break;
921   }
922   case PPC::SUBIC: {
923     MCInst TmpInst;
924     TmpInst.setOpcode(PPC::ADDIC);
925     TmpInst.addOperand(Inst.getOperand(0));
926     TmpInst.addOperand(Inst.getOperand(1));
927     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
928     Inst = TmpInst;
929     break;
930   }
931   case PPC::SUBICo: {
932     MCInst TmpInst;
933     TmpInst.setOpcode(PPC::ADDICo);
934     TmpInst.addOperand(Inst.getOperand(0));
935     TmpInst.addOperand(Inst.getOperand(1));
936     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
937     Inst = TmpInst;
938     break;
939   }
940   case PPC::EXTLWI:
941   case PPC::EXTLWIo: {
942     MCInst TmpInst;
943     int64_t N = Inst.getOperand(2).getImm();
944     int64_t B = Inst.getOperand(3).getImm();
945     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
946     TmpInst.addOperand(Inst.getOperand(0));
947     TmpInst.addOperand(Inst.getOperand(1));
948     TmpInst.addOperand(MCOperand::createImm(B));
949     TmpInst.addOperand(MCOperand::createImm(0));
950     TmpInst.addOperand(MCOperand::createImm(N - 1));
951     Inst = TmpInst;
952     break;
953   }
954   case PPC::EXTRWI:
955   case PPC::EXTRWIo: {
956     MCInst TmpInst;
957     int64_t N = Inst.getOperand(2).getImm();
958     int64_t B = Inst.getOperand(3).getImm();
959     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
960     TmpInst.addOperand(Inst.getOperand(0));
961     TmpInst.addOperand(Inst.getOperand(1));
962     TmpInst.addOperand(MCOperand::createImm(B + N));
963     TmpInst.addOperand(MCOperand::createImm(32 - N));
964     TmpInst.addOperand(MCOperand::createImm(31));
965     Inst = TmpInst;
966     break;
967   }
968   case PPC::INSLWI:
969   case PPC::INSLWIo: {
970     MCInst TmpInst;
971     int64_t N = Inst.getOperand(2).getImm();
972     int64_t B = Inst.getOperand(3).getImm();
973     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
974     TmpInst.addOperand(Inst.getOperand(0));
975     TmpInst.addOperand(Inst.getOperand(0));
976     TmpInst.addOperand(Inst.getOperand(1));
977     TmpInst.addOperand(MCOperand::createImm(32 - B));
978     TmpInst.addOperand(MCOperand::createImm(B));
979     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
980     Inst = TmpInst;
981     break;
982   }
983   case PPC::INSRWI:
984   case PPC::INSRWIo: {
985     MCInst TmpInst;
986     int64_t N = Inst.getOperand(2).getImm();
987     int64_t B = Inst.getOperand(3).getImm();
988     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
989     TmpInst.addOperand(Inst.getOperand(0));
990     TmpInst.addOperand(Inst.getOperand(0));
991     TmpInst.addOperand(Inst.getOperand(1));
992     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
993     TmpInst.addOperand(MCOperand::createImm(B));
994     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
995     Inst = TmpInst;
996     break;
997   }
998   case PPC::ROTRWI:
999   case PPC::ROTRWIo: {
1000     MCInst TmpInst;
1001     int64_t N = Inst.getOperand(2).getImm();
1002     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
1003     TmpInst.addOperand(Inst.getOperand(0));
1004     TmpInst.addOperand(Inst.getOperand(1));
1005     TmpInst.addOperand(MCOperand::createImm(32 - N));
1006     TmpInst.addOperand(MCOperand::createImm(0));
1007     TmpInst.addOperand(MCOperand::createImm(31));
1008     Inst = TmpInst;
1009     break;
1010   }
1011   case PPC::SLWI:
1012   case PPC::SLWIo: {
1013     MCInst TmpInst;
1014     int64_t N = Inst.getOperand(2).getImm();
1015     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1016     TmpInst.addOperand(Inst.getOperand(0));
1017     TmpInst.addOperand(Inst.getOperand(1));
1018     TmpInst.addOperand(MCOperand::createImm(N));
1019     TmpInst.addOperand(MCOperand::createImm(0));
1020     TmpInst.addOperand(MCOperand::createImm(31 - N));
1021     Inst = TmpInst;
1022     break;
1023   }
1024   case PPC::SRWI:
1025   case PPC::SRWIo: {
1026     MCInst TmpInst;
1027     int64_t N = Inst.getOperand(2).getImm();
1028     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1029     TmpInst.addOperand(Inst.getOperand(0));
1030     TmpInst.addOperand(Inst.getOperand(1));
1031     TmpInst.addOperand(MCOperand::createImm(32 - N));
1032     TmpInst.addOperand(MCOperand::createImm(N));
1033     TmpInst.addOperand(MCOperand::createImm(31));
1034     Inst = TmpInst;
1035     break;
1036   }
1037   case PPC::CLRRWI:
1038   case PPC::CLRRWIo: {
1039     MCInst TmpInst;
1040     int64_t N = Inst.getOperand(2).getImm();
1041     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1042     TmpInst.addOperand(Inst.getOperand(0));
1043     TmpInst.addOperand(Inst.getOperand(1));
1044     TmpInst.addOperand(MCOperand::createImm(0));
1045     TmpInst.addOperand(MCOperand::createImm(0));
1046     TmpInst.addOperand(MCOperand::createImm(31 - N));
1047     Inst = TmpInst;
1048     break;
1049   }
1050   case PPC::CLRLSLWI:
1051   case PPC::CLRLSLWIo: {
1052     MCInst TmpInst;
1053     int64_t B = Inst.getOperand(2).getImm();
1054     int64_t N = Inst.getOperand(3).getImm();
1055     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1056     TmpInst.addOperand(Inst.getOperand(0));
1057     TmpInst.addOperand(Inst.getOperand(1));
1058     TmpInst.addOperand(MCOperand::createImm(N));
1059     TmpInst.addOperand(MCOperand::createImm(B - N));
1060     TmpInst.addOperand(MCOperand::createImm(31 - N));
1061     Inst = TmpInst;
1062     break;
1063   }
1064   case PPC::EXTLDI:
1065   case PPC::EXTLDIo: {
1066     MCInst TmpInst;
1067     int64_t N = Inst.getOperand(2).getImm();
1068     int64_t B = Inst.getOperand(3).getImm();
1069     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1070     TmpInst.addOperand(Inst.getOperand(0));
1071     TmpInst.addOperand(Inst.getOperand(1));
1072     TmpInst.addOperand(MCOperand::createImm(B));
1073     TmpInst.addOperand(MCOperand::createImm(N - 1));
1074     Inst = TmpInst;
1075     break;
1076   }
1077   case PPC::EXTRDI:
1078   case PPC::EXTRDIo: {
1079     MCInst TmpInst;
1080     int64_t N = Inst.getOperand(2).getImm();
1081     int64_t B = Inst.getOperand(3).getImm();
1082     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1083     TmpInst.addOperand(Inst.getOperand(0));
1084     TmpInst.addOperand(Inst.getOperand(1));
1085     TmpInst.addOperand(MCOperand::createImm(B + N));
1086     TmpInst.addOperand(MCOperand::createImm(64 - N));
1087     Inst = TmpInst;
1088     break;
1089   }
1090   case PPC::INSRDI:
1091   case PPC::INSRDIo: {
1092     MCInst TmpInst;
1093     int64_t N = Inst.getOperand(2).getImm();
1094     int64_t B = Inst.getOperand(3).getImm();
1095     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1096     TmpInst.addOperand(Inst.getOperand(0));
1097     TmpInst.addOperand(Inst.getOperand(0));
1098     TmpInst.addOperand(Inst.getOperand(1));
1099     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1100     TmpInst.addOperand(MCOperand::createImm(B));
1101     Inst = TmpInst;
1102     break;
1103   }
1104   case PPC::ROTRDI:
1105   case PPC::ROTRDIo: {
1106     MCInst TmpInst;
1107     int64_t N = Inst.getOperand(2).getImm();
1108     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1109     TmpInst.addOperand(Inst.getOperand(0));
1110     TmpInst.addOperand(Inst.getOperand(1));
1111     TmpInst.addOperand(MCOperand::createImm(64 - N));
1112     TmpInst.addOperand(MCOperand::createImm(0));
1113     Inst = TmpInst;
1114     break;
1115   }
1116   case PPC::SLDI:
1117   case PPC::SLDIo: {
1118     MCInst TmpInst;
1119     int64_t N = Inst.getOperand(2).getImm();
1120     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1121     TmpInst.addOperand(Inst.getOperand(0));
1122     TmpInst.addOperand(Inst.getOperand(1));
1123     TmpInst.addOperand(MCOperand::createImm(N));
1124     TmpInst.addOperand(MCOperand::createImm(63 - N));
1125     Inst = TmpInst;
1126     break;
1127   }
1128   case PPC::SRDI:
1129   case PPC::SRDIo: {
1130     MCInst TmpInst;
1131     int64_t N = Inst.getOperand(2).getImm();
1132     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1133     TmpInst.addOperand(Inst.getOperand(0));
1134     TmpInst.addOperand(Inst.getOperand(1));
1135     TmpInst.addOperand(MCOperand::createImm(64 - N));
1136     TmpInst.addOperand(MCOperand::createImm(N));
1137     Inst = TmpInst;
1138     break;
1139   }
1140   case PPC::CLRRDI:
1141   case PPC::CLRRDIo: {
1142     MCInst TmpInst;
1143     int64_t N = Inst.getOperand(2).getImm();
1144     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1145     TmpInst.addOperand(Inst.getOperand(0));
1146     TmpInst.addOperand(Inst.getOperand(1));
1147     TmpInst.addOperand(MCOperand::createImm(0));
1148     TmpInst.addOperand(MCOperand::createImm(63 - N));
1149     Inst = TmpInst;
1150     break;
1151   }
1152   case PPC::CLRLSLDI:
1153   case PPC::CLRLSLDIo: {
1154     MCInst TmpInst;
1155     int64_t B = Inst.getOperand(2).getImm();
1156     int64_t N = Inst.getOperand(3).getImm();
1157     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1158     TmpInst.addOperand(Inst.getOperand(0));
1159     TmpInst.addOperand(Inst.getOperand(1));
1160     TmpInst.addOperand(MCOperand::createImm(N));
1161     TmpInst.addOperand(MCOperand::createImm(B - N));
1162     Inst = TmpInst;
1163     break;
1164   }
1165   case PPC::RLWINMbm:
1166   case PPC::RLWINMobm: {
1167     unsigned MB, ME;
1168     int64_t BM = Inst.getOperand(3).getImm();
1169     if (!isRunOfOnes(BM, MB, ME))
1170       break;
1171 
1172     MCInst TmpInst;
1173     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1174     TmpInst.addOperand(Inst.getOperand(0));
1175     TmpInst.addOperand(Inst.getOperand(1));
1176     TmpInst.addOperand(Inst.getOperand(2));
1177     TmpInst.addOperand(MCOperand::createImm(MB));
1178     TmpInst.addOperand(MCOperand::createImm(ME));
1179     Inst = TmpInst;
1180     break;
1181   }
1182   case PPC::RLWIMIbm:
1183   case PPC::RLWIMIobm: {
1184     unsigned MB, ME;
1185     int64_t BM = Inst.getOperand(3).getImm();
1186     if (!isRunOfOnes(BM, MB, ME))
1187       break;
1188 
1189     MCInst TmpInst;
1190     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1191     TmpInst.addOperand(Inst.getOperand(0));
1192     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1193     TmpInst.addOperand(Inst.getOperand(1));
1194     TmpInst.addOperand(Inst.getOperand(2));
1195     TmpInst.addOperand(MCOperand::createImm(MB));
1196     TmpInst.addOperand(MCOperand::createImm(ME));
1197     Inst = TmpInst;
1198     break;
1199   }
1200   case PPC::RLWNMbm:
1201   case PPC::RLWNMobm: {
1202     unsigned MB, ME;
1203     int64_t BM = Inst.getOperand(3).getImm();
1204     if (!isRunOfOnes(BM, MB, ME))
1205       break;
1206 
1207     MCInst TmpInst;
1208     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1209     TmpInst.addOperand(Inst.getOperand(0));
1210     TmpInst.addOperand(Inst.getOperand(1));
1211     TmpInst.addOperand(Inst.getOperand(2));
1212     TmpInst.addOperand(MCOperand::createImm(MB));
1213     TmpInst.addOperand(MCOperand::createImm(ME));
1214     Inst = TmpInst;
1215     break;
1216   }
1217   case PPC::MFTB: {
1218     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1219       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1220       Inst.setOpcode(PPC::MFSPR);
1221     }
1222     break;
1223   }
1224   case PPC::CP_COPYx:
1225   case PPC::CP_COPY_FIRST: {
1226     MCInst TmpInst;
1227     TmpInst.setOpcode(PPC::CP_COPY);
1228     TmpInst.addOperand(Inst.getOperand(0));
1229     TmpInst.addOperand(Inst.getOperand(1));
1230     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1231 
1232     Inst = TmpInst;
1233     break;
1234   }
1235   case PPC::CP_PASTEx :
1236   case PPC::CP_PASTE_LAST: {
1237     MCInst TmpInst;
1238     TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1239                       PPC::CP_PASTE : PPC::CP_PASTEo);
1240     TmpInst.addOperand(Inst.getOperand(0));
1241     TmpInst.addOperand(Inst.getOperand(1));
1242     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1243 
1244     Inst = TmpInst;
1245     break;
1246   }
1247   }
1248 }
1249 
1250 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1251                                            OperandVector &Operands,
1252                                            MCStreamer &Out, uint64_t &ErrorInfo,
1253                                            bool MatchingInlineAsm) {
1254   MCInst Inst;
1255 
1256   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1257   case Match_Success:
1258     // Post-process instructions (typically extended mnemonics)
1259     ProcessInstruction(Inst, Operands);
1260     Inst.setLoc(IDLoc);
1261     Out.EmitInstruction(Inst, getSTI());
1262     return false;
1263   case Match_MissingFeature:
1264     return Error(IDLoc, "instruction use requires an option to be enabled");
1265   case Match_MnemonicFail:
1266     return Error(IDLoc, "unrecognized instruction mnemonic");
1267   case Match_InvalidOperand: {
1268     SMLoc ErrorLoc = IDLoc;
1269     if (ErrorInfo != ~0ULL) {
1270       if (ErrorInfo >= Operands.size())
1271         return Error(IDLoc, "too few operands for instruction");
1272 
1273       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1274       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1275     }
1276 
1277     return Error(ErrorLoc, "invalid operand for instruction");
1278   }
1279   }
1280 
1281   llvm_unreachable("Implement any new match types added!");
1282 }
1283 
1284 bool PPCAsmParser::
1285 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1286   if (Tok.is(AsmToken::Identifier)) {
1287     StringRef Name = Tok.getString();
1288 
1289     if (Name.equals_lower("lr")) {
1290       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1291       IntVal = 8;
1292       return false;
1293     } else if (Name.equals_lower("ctr")) {
1294       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1295       IntVal = 9;
1296       return false;
1297     } else if (Name.equals_lower("vrsave")) {
1298       RegNo = PPC::VRSAVE;
1299       IntVal = 256;
1300       return false;
1301     } else if (Name.startswith_lower("r") &&
1302                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1303       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1304       return false;
1305     } else if (Name.startswith_lower("f") &&
1306                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1307       RegNo = FRegs[IntVal];
1308       return false;
1309     } else if (Name.startswith_lower("vs") &&
1310                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1311       RegNo = VSRegs[IntVal];
1312       return false;
1313     } else if (Name.startswith_lower("v") &&
1314                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1315       RegNo = VRegs[IntVal];
1316       return false;
1317     } else if (Name.startswith_lower("q") &&
1318                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1319       RegNo = QFRegs[IntVal];
1320       return false;
1321     } else if (Name.startswith_lower("cr") &&
1322                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1323       RegNo = CRRegs[IntVal];
1324       return false;
1325     }
1326   }
1327 
1328   return true;
1329 }
1330 
1331 bool PPCAsmParser::
1332 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1333   MCAsmParser &Parser = getParser();
1334   const AsmToken &Tok = Parser.getTok();
1335   StartLoc = Tok.getLoc();
1336   EndLoc = Tok.getEndLoc();
1337   RegNo = 0;
1338   int64_t IntVal;
1339 
1340   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1341     Parser.Lex(); // Eat identifier token.
1342     return false;
1343   }
1344 
1345   return Error(StartLoc, "invalid register name");
1346 }
1347 
1348 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1349 /// the expression and check for VK_PPC_LO/HI/HA
1350 /// symbol variants.  If all symbols with modifier use the same
1351 /// variant, return the corresponding PPCMCExpr::VariantKind,
1352 /// and a modified expression using the default symbol variant.
1353 /// Otherwise, return NULL.
1354 const MCExpr *PPCAsmParser::
1355 ExtractModifierFromExpr(const MCExpr *E,
1356                         PPCMCExpr::VariantKind &Variant) {
1357   MCContext &Context = getParser().getContext();
1358   Variant = PPCMCExpr::VK_PPC_None;
1359 
1360   switch (E->getKind()) {
1361   case MCExpr::Target:
1362   case MCExpr::Constant:
1363     return nullptr;
1364 
1365   case MCExpr::SymbolRef: {
1366     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1367 
1368     switch (SRE->getKind()) {
1369     case MCSymbolRefExpr::VK_PPC_LO:
1370       Variant = PPCMCExpr::VK_PPC_LO;
1371       break;
1372     case MCSymbolRefExpr::VK_PPC_HI:
1373       Variant = PPCMCExpr::VK_PPC_HI;
1374       break;
1375     case MCSymbolRefExpr::VK_PPC_HA:
1376       Variant = PPCMCExpr::VK_PPC_HA;
1377       break;
1378     case MCSymbolRefExpr::VK_PPC_HIGHER:
1379       Variant = PPCMCExpr::VK_PPC_HIGHER;
1380       break;
1381     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1382       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1383       break;
1384     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1385       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1386       break;
1387     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1388       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1389       break;
1390     default:
1391       return nullptr;
1392     }
1393 
1394     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1395   }
1396 
1397   case MCExpr::Unary: {
1398     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1399     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1400     if (!Sub)
1401       return nullptr;
1402     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1403   }
1404 
1405   case MCExpr::Binary: {
1406     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1407     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1408     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1409     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1410 
1411     if (!LHS && !RHS)
1412       return nullptr;
1413 
1414     if (!LHS) LHS = BE->getLHS();
1415     if (!RHS) RHS = BE->getRHS();
1416 
1417     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1418       Variant = RHSVariant;
1419     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1420       Variant = LHSVariant;
1421     else if (LHSVariant == RHSVariant)
1422       Variant = LHSVariant;
1423     else
1424       return nullptr;
1425 
1426     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1427   }
1428   }
1429 
1430   llvm_unreachable("Invalid expression kind!");
1431 }
1432 
1433 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1434 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1435 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1436 /// FIXME: This is a hack.
1437 const MCExpr *PPCAsmParser::
1438 FixupVariantKind(const MCExpr *E) {
1439   MCContext &Context = getParser().getContext();
1440 
1441   switch (E->getKind()) {
1442   case MCExpr::Target:
1443   case MCExpr::Constant:
1444     return E;
1445 
1446   case MCExpr::SymbolRef: {
1447     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1448     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1449 
1450     switch (SRE->getKind()) {
1451     case MCSymbolRefExpr::VK_TLSGD:
1452       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1453       break;
1454     case MCSymbolRefExpr::VK_TLSLD:
1455       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1456       break;
1457     default:
1458       return E;
1459     }
1460     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1461   }
1462 
1463   case MCExpr::Unary: {
1464     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1465     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1466     if (Sub == UE->getSubExpr())
1467       return E;
1468     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1469   }
1470 
1471   case MCExpr::Binary: {
1472     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1473     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1474     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1475     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1476       return E;
1477     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1478   }
1479   }
1480 
1481   llvm_unreachable("Invalid expression kind!");
1482 }
1483 
1484 /// ParseExpression.  This differs from the default "parseExpression" in that
1485 /// it handles modifiers.
1486 bool PPCAsmParser::
1487 ParseExpression(const MCExpr *&EVal) {
1488 
1489   if (isDarwin())
1490     return ParseDarwinExpression(EVal);
1491 
1492   // (ELF Platforms)
1493   // Handle \code @l/@ha \endcode
1494   if (getParser().parseExpression(EVal))
1495     return true;
1496 
1497   EVal = FixupVariantKind(EVal);
1498 
1499   PPCMCExpr::VariantKind Variant;
1500   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1501   if (E)
1502     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1503 
1504   return false;
1505 }
1506 
1507 /// ParseDarwinExpression.  (MachO Platforms)
1508 /// This differs from the default "parseExpression" in that it handles detection
1509 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1510 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1511 /// syntax form so it is done here.  TODO: Determine if there is merit in
1512 /// arranging for this to be done at a higher level.
1513 bool PPCAsmParser::
1514 ParseDarwinExpression(const MCExpr *&EVal) {
1515   MCAsmParser &Parser = getParser();
1516   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1517   switch (getLexer().getKind()) {
1518   default:
1519     break;
1520   case AsmToken::Identifier:
1521     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1522     // something starting with any other char should be part of the
1523     // asm syntax.  If handwritten asm includes an identifier like lo16,
1524     // then all bets are off - but no-one would do that, right?
1525     StringRef poss = Parser.getTok().getString();
1526     if (poss.equals_lower("lo16")) {
1527       Variant = PPCMCExpr::VK_PPC_LO;
1528     } else if (poss.equals_lower("hi16")) {
1529       Variant = PPCMCExpr::VK_PPC_HI;
1530     } else if (poss.equals_lower("ha16")) {
1531       Variant = PPCMCExpr::VK_PPC_HA;
1532     }
1533     if (Variant != PPCMCExpr::VK_PPC_None) {
1534       Parser.Lex(); // Eat the xx16
1535       if (getLexer().isNot(AsmToken::LParen))
1536         return Error(Parser.getTok().getLoc(), "expected '('");
1537       Parser.Lex(); // Eat the '('
1538     }
1539     break;
1540   }
1541 
1542   if (getParser().parseExpression(EVal))
1543     return true;
1544 
1545   if (Variant != PPCMCExpr::VK_PPC_None) {
1546     if (getLexer().isNot(AsmToken::RParen))
1547       return Error(Parser.getTok().getLoc(), "expected ')'");
1548     Parser.Lex(); // Eat the ')'
1549     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1550   }
1551   return false;
1552 }
1553 
1554 /// ParseOperand
1555 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1556 /// rNN for MachO.
1557 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1558   MCAsmParser &Parser = getParser();
1559   SMLoc S = Parser.getTok().getLoc();
1560   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1561   const MCExpr *EVal;
1562 
1563   // Attempt to parse the next token as an immediate
1564   switch (getLexer().getKind()) {
1565   // Special handling for register names.  These are interpreted
1566   // as immediates corresponding to the register number.
1567   case AsmToken::Percent:
1568     Parser.Lex(); // Eat the '%'.
1569     unsigned RegNo;
1570     int64_t IntVal;
1571     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1572       Parser.Lex(); // Eat the identifier token.
1573       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1574       return false;
1575     }
1576     return Error(S, "invalid register name");
1577 
1578   case AsmToken::Identifier:
1579     // Note that non-register-name identifiers from the compiler will begin
1580     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1581     // identifiers like r31foo - so we fall through in the event that parsing
1582     // a register name fails.
1583     if (isDarwin()) {
1584       unsigned RegNo;
1585       int64_t IntVal;
1586       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1587         Parser.Lex(); // Eat the identifier token.
1588         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1589         return false;
1590       }
1591     }
1592     // Fall-through to process non-register-name identifiers as expression.
1593     LLVM_FALLTHROUGH;
1594   // All other expressions
1595   case AsmToken::LParen:
1596   case AsmToken::Plus:
1597   case AsmToken::Minus:
1598   case AsmToken::Integer:
1599   case AsmToken::Dot:
1600   case AsmToken::Dollar:
1601   case AsmToken::Exclaim:
1602   case AsmToken::Tilde:
1603     if (!ParseExpression(EVal))
1604       break;
1605     /* fall through */
1606   default:
1607     return Error(S, "unknown operand");
1608   }
1609 
1610   // Push the parsed operand into the list of operands
1611   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1612 
1613   // Check whether this is a TLS call expression
1614   bool TLSCall = false;
1615   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1616     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1617 
1618   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1619     const MCExpr *TLSSym;
1620 
1621     Parser.Lex(); // Eat the '('.
1622     S = Parser.getTok().getLoc();
1623     if (ParseExpression(TLSSym))
1624       return Error(S, "invalid TLS call expression");
1625     if (getLexer().isNot(AsmToken::RParen))
1626       return Error(Parser.getTok().getLoc(), "missing ')'");
1627     E = Parser.getTok().getLoc();
1628     Parser.Lex(); // Eat the ')'.
1629 
1630     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1631   }
1632 
1633   // Otherwise, check for D-form memory operands
1634   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1635     Parser.Lex(); // Eat the '('.
1636     S = Parser.getTok().getLoc();
1637 
1638     int64_t IntVal;
1639     switch (getLexer().getKind()) {
1640     case AsmToken::Percent:
1641       Parser.Lex(); // Eat the '%'.
1642       unsigned RegNo;
1643       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1644         return Error(S, "invalid register name");
1645       Parser.Lex(); // Eat the identifier token.
1646       break;
1647 
1648     case AsmToken::Integer:
1649       if (!isDarwin()) {
1650         if (getParser().parseAbsoluteExpression(IntVal) ||
1651           IntVal < 0 || IntVal > 31)
1652         return Error(S, "invalid register number");
1653       } else {
1654         return Error(S, "unexpected integer value");
1655       }
1656       break;
1657 
1658    case AsmToken::Identifier:
1659     if (isDarwin()) {
1660       unsigned RegNo;
1661       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1662         Parser.Lex(); // Eat the identifier token.
1663         break;
1664       }
1665     }
1666     LLVM_FALLTHROUGH;
1667 
1668     default:
1669       return Error(S, "invalid memory operand");
1670     }
1671 
1672     if (getLexer().isNot(AsmToken::RParen))
1673       return Error(Parser.getTok().getLoc(), "missing ')'");
1674     E = Parser.getTok().getLoc();
1675     Parser.Lex(); // Eat the ')'.
1676 
1677     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1678   }
1679 
1680   return false;
1681 }
1682 
1683 /// Parse an instruction mnemonic followed by its operands.
1684 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1685                                     SMLoc NameLoc, OperandVector &Operands) {
1686   // The first operand is the token for the instruction name.
1687   // If the next character is a '+' or '-', we need to add it to the
1688   // instruction name, to match what TableGen is doing.
1689   std::string NewOpcode;
1690   if (getLexer().is(AsmToken::Plus)) {
1691     getLexer().Lex();
1692     NewOpcode = Name;
1693     NewOpcode += '+';
1694     Name = NewOpcode;
1695   }
1696   if (getLexer().is(AsmToken::Minus)) {
1697     getLexer().Lex();
1698     NewOpcode = Name;
1699     NewOpcode += '-';
1700     Name = NewOpcode;
1701   }
1702   // If the instruction ends in a '.', we need to create a separate
1703   // token for it, to match what TableGen is doing.
1704   size_t Dot = Name.find('.');
1705   StringRef Mnemonic = Name.slice(0, Dot);
1706   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1707     Operands.push_back(
1708         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1709   else
1710     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1711   if (Dot != StringRef::npos) {
1712     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1713     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1714     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1715       Operands.push_back(
1716           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1717     else
1718       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1719   }
1720 
1721   // If there are no more operands then finish
1722   if (getLexer().is(AsmToken::EndOfStatement))
1723     return false;
1724 
1725   // Parse the first operand
1726   if (ParseOperand(Operands))
1727     return true;
1728 
1729   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1730          getLexer().is(AsmToken::Comma)) {
1731     // Consume the comma token
1732     Lex();
1733 
1734     // Parse the next operand
1735     if (ParseOperand(Operands))
1736       return true;
1737   }
1738 
1739   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1740   // and dcbtst instructions differs for server vs. embedded cores.
1741   //  The syntax for dcbt is:
1742   //    dcbt ra, rb, th [server]
1743   //    dcbt th, ra, rb [embedded]
1744   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1745   //  server form to be the default, so swap the operands if we're parsing for
1746   //  an embedded core (they'll be swapped again upon printing).
1747   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1748       Operands.size() == 4 &&
1749       (Name == "dcbt" || Name == "dcbtst")) {
1750     std::swap(Operands[1], Operands[3]);
1751     std::swap(Operands[2], Operands[1]);
1752   }
1753 
1754   return false;
1755 }
1756 
1757 /// ParseDirective parses the PPC specific directives
1758 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1759   StringRef IDVal = DirectiveID.getIdentifier();
1760   if (!isDarwin()) {
1761     if (IDVal == ".word")
1762       return ParseDirectiveWord(2, DirectiveID.getLoc());
1763     if (IDVal == ".llong")
1764       return ParseDirectiveWord(8, DirectiveID.getLoc());
1765     if (IDVal == ".tc")
1766       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1767     if (IDVal == ".machine")
1768       return ParseDirectiveMachine(DirectiveID.getLoc());
1769     if (IDVal == ".abiversion")
1770       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1771     if (IDVal == ".localentry")
1772       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1773   } else {
1774     if (IDVal == ".machine")
1775       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1776   }
1777   return true;
1778 }
1779 
1780 /// ParseDirectiveWord
1781 ///  ::= .word [ expression (, expression)* ]
1782 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1783   MCAsmParser &Parser = getParser();
1784   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1785     for (;;) {
1786       const MCExpr *Value;
1787       SMLoc ExprLoc = getLexer().getLoc();
1788       if (getParser().parseExpression(Value))
1789         return false;
1790 
1791       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1792         assert(Size <= 8 && "Invalid size");
1793         uint64_t IntValue = MCE->getValue();
1794         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1795           return Error(ExprLoc, "literal value out of range for directive");
1796         getStreamer().EmitIntValue(IntValue, Size);
1797       } else {
1798         getStreamer().EmitValue(Value, Size, ExprLoc);
1799       }
1800 
1801       if (getLexer().is(AsmToken::EndOfStatement))
1802         break;
1803 
1804       if (getLexer().isNot(AsmToken::Comma))
1805         return Error(L, "unexpected token in directive");
1806       Parser.Lex();
1807     }
1808   }
1809 
1810   Parser.Lex();
1811   return false;
1812 }
1813 
1814 /// ParseDirectiveTC
1815 ///  ::= .tc [ symbol (, expression)* ]
1816 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1817   MCAsmParser &Parser = getParser();
1818   // Skip TC symbol, which is only used with XCOFF.
1819   while (getLexer().isNot(AsmToken::EndOfStatement)
1820          && getLexer().isNot(AsmToken::Comma))
1821     Parser.Lex();
1822   if (getLexer().isNot(AsmToken::Comma)) {
1823     Error(L, "unexpected token in directive");
1824     return false;
1825   }
1826   Parser.Lex();
1827 
1828   // Align to word size.
1829   getParser().getStreamer().EmitValueToAlignment(Size);
1830 
1831   // Emit expressions.
1832   return ParseDirectiveWord(Size, L);
1833 }
1834 
1835 /// ParseDirectiveMachine (ELF platforms)
1836 ///  ::= .machine [ cpu | "push" | "pop" ]
1837 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1838   MCAsmParser &Parser = getParser();
1839   if (getLexer().isNot(AsmToken::Identifier) &&
1840       getLexer().isNot(AsmToken::String)) {
1841     Error(L, "unexpected token in directive");
1842     return false;
1843   }
1844 
1845   StringRef CPU = Parser.getTok().getIdentifier();
1846   Parser.Lex();
1847 
1848   // FIXME: Right now, the parser always allows any available
1849   // instruction, so the .machine directive is not useful.
1850   // Implement ".machine any" (by doing nothing) for the benefit
1851   // of existing assembler code.  Likewise, we can then implement
1852   // ".machine push" and ".machine pop" as no-op.
1853   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1854     Error(L, "unrecognized machine type");
1855     return false;
1856   }
1857 
1858   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1859     Error(L, "unexpected token in directive");
1860     return false;
1861   }
1862   PPCTargetStreamer &TStreamer =
1863       *static_cast<PPCTargetStreamer *>(
1864            getParser().getStreamer().getTargetStreamer());
1865   TStreamer.emitMachine(CPU);
1866 
1867   return false;
1868 }
1869 
1870 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1871 ///  ::= .machine cpu-identifier
1872 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1873   MCAsmParser &Parser = getParser();
1874   if (getLexer().isNot(AsmToken::Identifier) &&
1875       getLexer().isNot(AsmToken::String)) {
1876     Error(L, "unexpected token in directive");
1877     return false;
1878   }
1879 
1880   StringRef CPU = Parser.getTok().getIdentifier();
1881   Parser.Lex();
1882 
1883   // FIXME: this is only the 'default' set of cpu variants.
1884   // However we don't act on this information at present, this is simply
1885   // allowing parsing to proceed with minimal sanity checking.
1886   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1887     Error(L, "unrecognized cpu type");
1888     return false;
1889   }
1890 
1891   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1892     Error(L, "wrong cpu type specified for 64bit");
1893     return false;
1894   }
1895   if (!isPPC64() && CPU == "ppc64") {
1896     Error(L, "wrong cpu type specified for 32bit");
1897     return false;
1898   }
1899 
1900   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1901     Error(L, "unexpected token in directive");
1902     return false;
1903   }
1904 
1905   return false;
1906 }
1907 
1908 /// ParseDirectiveAbiVersion
1909 ///  ::= .abiversion constant-expression
1910 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1911   int64_t AbiVersion;
1912   if (getParser().parseAbsoluteExpression(AbiVersion)){
1913     Error(L, "expected constant expression");
1914     return false;
1915   }
1916   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1917     Error(L, "unexpected token in directive");
1918     return false;
1919   }
1920 
1921   PPCTargetStreamer &TStreamer =
1922       *static_cast<PPCTargetStreamer *>(
1923            getParser().getStreamer().getTargetStreamer());
1924   TStreamer.emitAbiVersion(AbiVersion);
1925 
1926   return false;
1927 }
1928 
1929 /// ParseDirectiveLocalEntry
1930 ///  ::= .localentry symbol, expression
1931 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1932   StringRef Name;
1933   if (getParser().parseIdentifier(Name)) {
1934     Error(L, "expected identifier in directive");
1935     return false;
1936   }
1937   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1938 
1939   if (getLexer().isNot(AsmToken::Comma)) {
1940     Error(L, "unexpected token in directive");
1941     return false;
1942   }
1943   Lex();
1944 
1945   const MCExpr *Expr;
1946   if (getParser().parseExpression(Expr)) {
1947     Error(L, "expected expression");
1948     return false;
1949   }
1950 
1951   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1952     Error(L, "unexpected token in directive");
1953     return false;
1954   }
1955 
1956   PPCTargetStreamer &TStreamer =
1957       *static_cast<PPCTargetStreamer *>(
1958            getParser().getStreamer().getTargetStreamer());
1959   TStreamer.emitLocalEntry(Sym, Expr);
1960 
1961   return false;
1962 }
1963 
1964 
1965 
1966 /// Force static initialization.
1967 extern "C" void LLVMInitializePowerPCAsmParser() {
1968   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1969   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1970   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1971 }
1972 
1973 #define GET_REGISTER_MATCHER
1974 #define GET_MATCHER_IMPLEMENTATION
1975 #include "PPCGenAsmMatcher.inc"
1976 
1977 // Define this matcher function after the auto-generated include so we
1978 // have the match class enum definitions.
1979 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1980                                                   unsigned Kind) {
1981   // If the kind is a token for a literal immediate, check if our asm
1982   // operand matches. This is for InstAliases which have a fixed-value
1983   // immediate in the syntax.
1984   int64_t ImmVal;
1985   switch (Kind) {
1986     case MCK_0: ImmVal = 0; break;
1987     case MCK_1: ImmVal = 1; break;
1988     case MCK_2: ImmVal = 2; break;
1989     case MCK_3: ImmVal = 3; break;
1990     case MCK_4: ImmVal = 4; break;
1991     case MCK_5: ImmVal = 5; break;
1992     case MCK_6: ImmVal = 6; break;
1993     case MCK_7: ImmVal = 7; break;
1994     default: return Match_InvalidOperand;
1995   }
1996 
1997   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1998   if (Op.isImm() && Op.getImm() == ImmVal)
1999     return Match_Success;
2000 
2001   return Match_InvalidOperand;
2002 }
2003 
2004 const MCExpr *
2005 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
2006                                   MCSymbolRefExpr::VariantKind Variant,
2007                                   MCContext &Ctx) {
2008   switch (Variant) {
2009   case MCSymbolRefExpr::VK_PPC_LO:
2010     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
2011   case MCSymbolRefExpr::VK_PPC_HI:
2012     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
2013   case MCSymbolRefExpr::VK_PPC_HA:
2014     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
2015   case MCSymbolRefExpr::VK_PPC_HIGHER:
2016     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
2017   case MCSymbolRefExpr::VK_PPC_HIGHERA:
2018     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
2019   case MCSymbolRefExpr::VK_PPC_HIGHEST:
2020     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
2021   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
2022     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
2023   default:
2024     return nullptr;
2025   }
2026 }
2027