1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 static const MCPhysReg RRegs[32] = {
35   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
36   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
37   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
38   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42   PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 };
44 static const MCPhysReg RRegsNoR0[32] = {
45   PPC::ZERO,
46             PPC::R1,  PPC::R2,  PPC::R3,
47   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
48   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
49   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53   PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 };
55 static const MCPhysReg XRegs[32] = {
56   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
57   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
58   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
59   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63   PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 };
65 static const MCPhysReg XRegsNoX0[32] = {
66   PPC::ZERO8,
67             PPC::X1,  PPC::X2,  PPC::X3,
68   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
69   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
70   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74   PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 };
76 static const MCPhysReg FRegs[32] = {
77   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
78   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
79   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
80   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84   PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 };
86 static const MCPhysReg VRegs[32] = {
87   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
88   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
89   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
90   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
91   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
92   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
93   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
94   PPC::V28, PPC::V29, PPC::V30, PPC::V31
95 };
96 static const MCPhysReg VSRegs[64] = {
97   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
98   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
99   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
100   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
101   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
102   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
103   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
104   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
105 
106   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
107   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
108   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
109   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
110   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
111   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
112   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
113   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
114 };
115 static const MCPhysReg VSFRegs[64] = {
116   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
117   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
118   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
119   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
120   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
121   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
122   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
123   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
124 
125   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
126   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
127   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
128   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
129   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
130   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
131   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
132   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
133 };
134 static const MCPhysReg VSSRegs[64] = {
135   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
136   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
137   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
138   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
139   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
140   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
141   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
142   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
143 
144   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
145   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
146   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
147   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
148   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
149   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
150   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
151   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
152 };
153 static unsigned QFRegs[32] = {
154   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
155   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
156   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
157   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
158   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
159   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
160   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
161   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
162 };
163 static const MCPhysReg CRBITRegs[32] = {
164   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
165   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
166   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
167   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
168   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
169   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
170   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
171   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
172 };
173 static const MCPhysReg CRRegs[8] = {
174   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
175   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
176 };
177 
178 // Evaluate an expression containing condition register
179 // or condition register field symbols.  Returns positive
180 // value on success, or -1 on error.
181 static int64_t
182 EvaluateCRExpr(const MCExpr *E) {
183   switch (E->getKind()) {
184   case MCExpr::Target:
185     return -1;
186 
187   case MCExpr::Constant: {
188     int64_t Res = cast<MCConstantExpr>(E)->getValue();
189     return Res < 0 ? -1 : Res;
190   }
191 
192   case MCExpr::SymbolRef: {
193     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
194     StringRef Name = SRE->getSymbol().getName();
195 
196     if (Name == "lt") return 0;
197     if (Name == "gt") return 1;
198     if (Name == "eq") return 2;
199     if (Name == "so") return 3;
200     if (Name == "un") return 3;
201 
202     if (Name == "cr0") return 0;
203     if (Name == "cr1") return 1;
204     if (Name == "cr2") return 2;
205     if (Name == "cr3") return 3;
206     if (Name == "cr4") return 4;
207     if (Name == "cr5") return 5;
208     if (Name == "cr6") return 6;
209     if (Name == "cr7") return 7;
210 
211     return -1;
212   }
213 
214   case MCExpr::Unary:
215     return -1;
216 
217   case MCExpr::Binary: {
218     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
219     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
220     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
221     int64_t Res;
222 
223     if (LHSVal < 0 || RHSVal < 0)
224       return -1;
225 
226     switch (BE->getOpcode()) {
227     default: return -1;
228     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
229     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
230     }
231 
232     return Res < 0 ? -1 : Res;
233   }
234   }
235 
236   llvm_unreachable("Invalid expression kind!");
237 }
238 
239 namespace {
240 
241 struct PPCOperand;
242 
243 class PPCAsmParser : public MCTargetAsmParser {
244   const MCInstrInfo &MII;
245   bool IsPPC64;
246   bool IsDarwin;
247 
248   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
249   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
250 
251   bool isPPC64() const { return IsPPC64; }
252   bool isDarwin() const { return IsDarwin; }
253 
254   bool MatchRegisterName(const AsmToken &Tok,
255                          unsigned &RegNo, int64_t &IntVal);
256 
257   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
258 
259   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
260                                         PPCMCExpr::VariantKind &Variant);
261   const MCExpr *FixupVariantKind(const MCExpr *E);
262   bool ParseExpression(const MCExpr *&EVal);
263   bool ParseDarwinExpression(const MCExpr *&EVal);
264 
265   bool ParseOperand(OperandVector &Operands);
266 
267   bool ParseDirectiveWord(unsigned Size, SMLoc L);
268   bool ParseDirectiveTC(unsigned Size, SMLoc L);
269   bool ParseDirectiveMachine(SMLoc L);
270   bool ParseDarwinDirectiveMachine(SMLoc L);
271   bool ParseDirectiveAbiVersion(SMLoc L);
272   bool ParseDirectiveLocalEntry(SMLoc L);
273 
274   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
275                                OperandVector &Operands, MCStreamer &Out,
276                                uint64_t &ErrorInfo,
277                                bool MatchingInlineAsm) override;
278 
279   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
280 
281   /// @name Auto-generated Match Functions
282   /// {
283 
284 #define GET_ASSEMBLER_HEADER
285 #include "PPCGenAsmMatcher.inc"
286 
287   /// }
288 
289 
290 public:
291   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
292                const MCInstrInfo &MII, const MCTargetOptions &Options)
293     : MCTargetAsmParser(Options, STI), MII(MII) {
294     // Check for 64-bit vs. 32-bit pointer mode.
295     Triple TheTriple(STI.getTargetTriple());
296     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
297                TheTriple.getArch() == Triple::ppc64le);
298     IsDarwin = TheTriple.isMacOSX();
299     // Initialize the set of available features.
300     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
301   }
302 
303   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
304                         SMLoc NameLoc, OperandVector &Operands) override;
305 
306   bool ParseDirective(AsmToken DirectiveID) override;
307 
308   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
309                                       unsigned Kind) override;
310 
311   const MCExpr *applyModifierToExpr(const MCExpr *E,
312                                     MCSymbolRefExpr::VariantKind,
313                                     MCContext &Ctx) override;
314 };
315 
316 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
317 /// instruction.
318 struct PPCOperand : public MCParsedAsmOperand {
319   enum KindTy {
320     Token,
321     Immediate,
322     ContextImmediate,
323     Expression,
324     TLSRegister
325   } Kind;
326 
327   SMLoc StartLoc, EndLoc;
328   bool IsPPC64;
329 
330   struct TokOp {
331     const char *Data;
332     unsigned Length;
333   };
334 
335   struct ImmOp {
336     int64_t Val;
337   };
338 
339   struct ExprOp {
340     const MCExpr *Val;
341     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
342   };
343 
344   struct TLSRegOp {
345     const MCSymbolRefExpr *Sym;
346   };
347 
348   union {
349     struct TokOp Tok;
350     struct ImmOp Imm;
351     struct ExprOp Expr;
352     struct TLSRegOp TLSReg;
353   };
354 
355   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
356 public:
357   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
358     Kind = o.Kind;
359     StartLoc = o.StartLoc;
360     EndLoc = o.EndLoc;
361     IsPPC64 = o.IsPPC64;
362     switch (Kind) {
363     case Token:
364       Tok = o.Tok;
365       break;
366     case Immediate:
367     case ContextImmediate:
368       Imm = o.Imm;
369       break;
370     case Expression:
371       Expr = o.Expr;
372       break;
373     case TLSRegister:
374       TLSReg = o.TLSReg;
375       break;
376     }
377   }
378 
379   // Disable use of sized deallocation due to overallocation of PPCOperand
380   // objects in CreateTokenWithStringCopy.
381   void operator delete(void *p) { ::operator delete(p); }
382 
383   /// getStartLoc - Get the location of the first token of this operand.
384   SMLoc getStartLoc() const override { return StartLoc; }
385 
386   /// getEndLoc - Get the location of the last token of this operand.
387   SMLoc getEndLoc() const override { return EndLoc; }
388 
389   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
390   bool isPPC64() const { return IsPPC64; }
391 
392   int64_t getImm() const {
393     assert(Kind == Immediate && "Invalid access!");
394     return Imm.Val;
395   }
396   int64_t getImmS16Context() const {
397     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
398     if (Kind == Immediate)
399       return Imm.Val;
400     return static_cast<int16_t>(Imm.Val);
401   }
402   int64_t getImmU16Context() const {
403     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
404     return Imm.Val;
405   }
406 
407   const MCExpr *getExpr() const {
408     assert(Kind == Expression && "Invalid access!");
409     return Expr.Val;
410   }
411 
412   int64_t getExprCRVal() const {
413     assert(Kind == Expression && "Invalid access!");
414     return Expr.CRVal;
415   }
416 
417   const MCExpr *getTLSReg() const {
418     assert(Kind == TLSRegister && "Invalid access!");
419     return TLSReg.Sym;
420   }
421 
422   unsigned getReg() const override {
423     assert(isRegNumber() && "Invalid access!");
424     return (unsigned) Imm.Val;
425   }
426 
427   unsigned getVSReg() const {
428     assert(isVSRegNumber() && "Invalid access!");
429     return (unsigned) Imm.Val;
430   }
431 
432   unsigned getCCReg() const {
433     assert(isCCRegNumber() && "Invalid access!");
434     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
435   }
436 
437   unsigned getCRBit() const {
438     assert(isCRBitNumber() && "Invalid access!");
439     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
440   }
441 
442   unsigned getCRBitMask() const {
443     assert(isCRBitMask() && "Invalid access!");
444     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
445   }
446 
447   bool isToken() const override { return Kind == Token; }
448   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
449   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
450   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
451   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
452   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
453   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
454   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
455   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
456   bool isU6ImmX2() const { return Kind == Immediate &&
457                                   isUInt<6>(getImm()) &&
458                                   (getImm() & 1) == 0; }
459   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
460   bool isU7ImmX4() const { return Kind == Immediate &&
461                                   isUInt<7>(getImm()) &&
462                                   (getImm() & 3) == 0; }
463   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
464   bool isU8ImmX8() const { return Kind == Immediate &&
465                                   isUInt<8>(getImm()) &&
466                                   (getImm() & 7) == 0; }
467 
468   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
469   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
470   bool isU16Imm() const {
471     switch (Kind) {
472       case Expression:
473         return true;
474       case Immediate:
475       case ContextImmediate:
476         return isUInt<16>(getImmU16Context());
477       default:
478         return false;
479     }
480   }
481   bool isS16Imm() const {
482     switch (Kind) {
483       case Expression:
484         return true;
485       case Immediate:
486       case ContextImmediate:
487         return isInt<16>(getImmS16Context());
488       default:
489         return false;
490     }
491   }
492   bool isS16ImmX4() const { return Kind == Expression ||
493                                    (Kind == Immediate && isInt<16>(getImm()) &&
494                                     (getImm() & 3) == 0); }
495   bool isS16ImmX16() const { return Kind == Expression ||
496                                     (Kind == Immediate && isInt<16>(getImm()) &&
497                                      (getImm() & 15) == 0); }
498   bool isS17Imm() const {
499     switch (Kind) {
500       case Expression:
501         return true;
502       case Immediate:
503       case ContextImmediate:
504         return isInt<17>(getImmS16Context());
505       default:
506         return false;
507     }
508   }
509   bool isTLSReg() const { return Kind == TLSRegister; }
510   bool isDirectBr() const {
511     if (Kind == Expression)
512       return true;
513     if (Kind != Immediate)
514       return false;
515     // Operand must be 64-bit aligned, signed 27-bit immediate.
516     if ((getImm() & 3) != 0)
517       return false;
518     if (isInt<26>(getImm()))
519       return true;
520     if (!IsPPC64) {
521       // In 32-bit mode, large 32-bit quantities wrap around.
522       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
523         return true;
524     }
525     return false;
526   }
527   bool isCondBr() const { return Kind == Expression ||
528                                  (Kind == Immediate && isInt<16>(getImm()) &&
529                                   (getImm() & 3) == 0); }
530   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
531   bool isD8RCRegNumber() const { return Kind == Immediate &&
532                                         isUInt<5>(getImm()) &&
533                                         // required even register id
534                                         !(getImm() & 0x1); }
535   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
536   bool isCCRegNumber() const { return (Kind == Expression
537                                        && isUInt<3>(getExprCRVal())) ||
538                                       (Kind == Immediate
539                                        && isUInt<3>(getImm())); }
540   bool isCRBitNumber() const { return (Kind == Expression
541                                        && isUInt<5>(getExprCRVal())) ||
542                                       (Kind == Immediate
543                                        && isUInt<5>(getImm())); }
544   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
545                                     isPowerOf2_32(getImm()); }
546   bool isMem() const override { return false; }
547   bool isReg() const override { return false; }
548 
549   void addRegOperands(MCInst &Inst, unsigned N) const {
550     llvm_unreachable("addRegOperands");
551   }
552 
553   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
554     assert(N == 1 && "Invalid number of operands!");
555     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
556   }
557 
558   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
559     assert(N == 1 && "Invalid number of operands!");
560     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
561   }
562 
563   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
564     assert(N == 1 && "Invalid number of operands!");
565     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
566   }
567 
568   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
569     assert(N == 1 && "Invalid number of operands!");
570     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
571   }
572 
573   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
574     if (isPPC64())
575       addRegG8RCOperands(Inst, N);
576     else
577       addRegGPRCOperands(Inst, N);
578   }
579 
580   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
581     if (isPPC64())
582       addRegG8RCNoX0Operands(Inst, N);
583     else
584       addRegGPRCNoR0Operands(Inst, N);
585   }
586 
587   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
588     assert(N == 1 && "Invalid number of operands!");
589     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
590   }
591 
592   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
593     assert(N == 1 && "Invalid number of operands!");
594     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
595   }
596 
597   void addRegD8RCOperands(MCInst &Inst, unsigned N) const {
598     assert(N == 1 && "Invalid number of operands!");
599     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
600   }
601 
602   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
603     assert(N == 1 && "Invalid number of operands!");
604     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
605   }
606 
607   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
608     assert(N == 1 && "Invalid number of operands!");
609     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
610   }
611 
612   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
613     assert(N == 1 && "Invalid number of operands!");
614     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
615   }
616 
617   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
618     assert(N == 1 && "Invalid number of operands!");
619     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
620   }
621 
622   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
623     assert(N == 1 && "Invalid number of operands!");
624     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
625   }
626 
627   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
628     assert(N == 1 && "Invalid number of operands!");
629     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
630   }
631 
632   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
633     assert(N == 1 && "Invalid number of operands!");
634     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
635   }
636 
637   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
638     assert(N == 1 && "Invalid number of operands!");
639     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
640   }
641 
642   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
643     assert(N == 1 && "Invalid number of operands!");
644     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
645   }
646 
647   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
648     assert(N == 1 && "Invalid number of operands!");
649     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
650   }
651 
652   void addImmOperands(MCInst &Inst, unsigned N) const {
653     assert(N == 1 && "Invalid number of operands!");
654     if (Kind == Immediate)
655       Inst.addOperand(MCOperand::createImm(getImm()));
656     else
657       Inst.addOperand(MCOperand::createExpr(getExpr()));
658   }
659 
660   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
661     assert(N == 1 && "Invalid number of operands!");
662     switch (Kind) {
663       case Immediate:
664         Inst.addOperand(MCOperand::createImm(getImm()));
665         break;
666       case ContextImmediate:
667         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
668         break;
669       default:
670         Inst.addOperand(MCOperand::createExpr(getExpr()));
671         break;
672     }
673   }
674 
675   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
676     assert(N == 1 && "Invalid number of operands!");
677     switch (Kind) {
678       case Immediate:
679         Inst.addOperand(MCOperand::createImm(getImm()));
680         break;
681       case ContextImmediate:
682         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
683         break;
684       default:
685         Inst.addOperand(MCOperand::createExpr(getExpr()));
686         break;
687     }
688   }
689 
690   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
691     assert(N == 1 && "Invalid number of operands!");
692     if (Kind == Immediate)
693       Inst.addOperand(MCOperand::createImm(getImm() / 4));
694     else
695       Inst.addOperand(MCOperand::createExpr(getExpr()));
696   }
697 
698   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
699     assert(N == 1 && "Invalid number of operands!");
700     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
701   }
702 
703   StringRef getToken() const {
704     assert(Kind == Token && "Invalid access!");
705     return StringRef(Tok.Data, Tok.Length);
706   }
707 
708   void print(raw_ostream &OS) const override;
709 
710   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
711                                                  bool IsPPC64) {
712     auto Op = make_unique<PPCOperand>(Token);
713     Op->Tok.Data = Str.data();
714     Op->Tok.Length = Str.size();
715     Op->StartLoc = S;
716     Op->EndLoc = S;
717     Op->IsPPC64 = IsPPC64;
718     return Op;
719   }
720 
721   static std::unique_ptr<PPCOperand>
722   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
723     // Allocate extra memory for the string and copy it.
724     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
725     // deleter which will destroy them by simply using "delete", not correctly
726     // calling operator delete on this extra memory after calling the dtor
727     // explicitly.
728     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
729     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
730     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
731     Op->Tok.Length = Str.size();
732     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
733     Op->StartLoc = S;
734     Op->EndLoc = S;
735     Op->IsPPC64 = IsPPC64;
736     return Op;
737   }
738 
739   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
740                                                bool IsPPC64) {
741     auto Op = make_unique<PPCOperand>(Immediate);
742     Op->Imm.Val = Val;
743     Op->StartLoc = S;
744     Op->EndLoc = E;
745     Op->IsPPC64 = IsPPC64;
746     return Op;
747   }
748 
749   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
750                                                 SMLoc E, bool IsPPC64) {
751     auto Op = make_unique<PPCOperand>(Expression);
752     Op->Expr.Val = Val;
753     Op->Expr.CRVal = EvaluateCRExpr(Val);
754     Op->StartLoc = S;
755     Op->EndLoc = E;
756     Op->IsPPC64 = IsPPC64;
757     return Op;
758   }
759 
760   static std::unique_ptr<PPCOperand>
761   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
762     auto Op = make_unique<PPCOperand>(TLSRegister);
763     Op->TLSReg.Sym = Sym;
764     Op->StartLoc = S;
765     Op->EndLoc = E;
766     Op->IsPPC64 = IsPPC64;
767     return Op;
768   }
769 
770   static std::unique_ptr<PPCOperand>
771   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
772     auto Op = make_unique<PPCOperand>(ContextImmediate);
773     Op->Imm.Val = Val;
774     Op->StartLoc = S;
775     Op->EndLoc = E;
776     Op->IsPPC64 = IsPPC64;
777     return Op;
778   }
779 
780   static std::unique_ptr<PPCOperand>
781   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
782     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
783       return CreateImm(CE->getValue(), S, E, IsPPC64);
784 
785     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
786       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
787         return CreateTLSReg(SRE, S, E, IsPPC64);
788 
789     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
790       int64_t Res;
791       if (TE->evaluateAsConstant(Res))
792         return CreateContextImm(Res, S, E, IsPPC64);
793     }
794 
795     return CreateExpr(Val, S, E, IsPPC64);
796   }
797 };
798 
799 } // end anonymous namespace.
800 
801 void PPCOperand::print(raw_ostream &OS) const {
802   switch (Kind) {
803   case Token:
804     OS << "'" << getToken() << "'";
805     break;
806   case Immediate:
807   case ContextImmediate:
808     OS << getImm();
809     break;
810   case Expression:
811     OS << *getExpr();
812     break;
813   case TLSRegister:
814     OS << *getTLSReg();
815     break;
816   }
817 }
818 
819 static void
820 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
821   if (Op.isImm()) {
822     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
823     return;
824   }
825   const MCExpr *Expr = Op.getExpr();
826   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
827     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
828       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
829       return;
830     }
831   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
832     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
833       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
834                                                  BinExpr->getLHS(), Ctx);
835       Inst.addOperand(MCOperand::createExpr(NE));
836       return;
837     }
838   }
839   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
840 }
841 
842 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
843                                       const OperandVector &Operands) {
844   int Opcode = Inst.getOpcode();
845   switch (Opcode) {
846   case PPC::DCBTx:
847   case PPC::DCBTT:
848   case PPC::DCBTSTx:
849   case PPC::DCBTSTT: {
850     MCInst TmpInst;
851     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
852                       PPC::DCBT : PPC::DCBTST);
853     TmpInst.addOperand(MCOperand::createImm(
854       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
855     TmpInst.addOperand(Inst.getOperand(0));
856     TmpInst.addOperand(Inst.getOperand(1));
857     Inst = TmpInst;
858     break;
859   }
860   case PPC::DCBTCT:
861   case PPC::DCBTDS: {
862     MCInst TmpInst;
863     TmpInst.setOpcode(PPC::DCBT);
864     TmpInst.addOperand(Inst.getOperand(2));
865     TmpInst.addOperand(Inst.getOperand(0));
866     TmpInst.addOperand(Inst.getOperand(1));
867     Inst = TmpInst;
868     break;
869   }
870   case PPC::DCBTSTCT:
871   case PPC::DCBTSTDS: {
872     MCInst TmpInst;
873     TmpInst.setOpcode(PPC::DCBTST);
874     TmpInst.addOperand(Inst.getOperand(2));
875     TmpInst.addOperand(Inst.getOperand(0));
876     TmpInst.addOperand(Inst.getOperand(1));
877     Inst = TmpInst;
878     break;
879   }
880   case PPC::LAx: {
881     MCInst TmpInst;
882     TmpInst.setOpcode(PPC::LA);
883     TmpInst.addOperand(Inst.getOperand(0));
884     TmpInst.addOperand(Inst.getOperand(2));
885     TmpInst.addOperand(Inst.getOperand(1));
886     Inst = TmpInst;
887     break;
888   }
889   case PPC::SUBI: {
890     MCInst TmpInst;
891     TmpInst.setOpcode(PPC::ADDI);
892     TmpInst.addOperand(Inst.getOperand(0));
893     TmpInst.addOperand(Inst.getOperand(1));
894     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
895     Inst = TmpInst;
896     break;
897   }
898   case PPC::SUBIS: {
899     MCInst TmpInst;
900     TmpInst.setOpcode(PPC::ADDIS);
901     TmpInst.addOperand(Inst.getOperand(0));
902     TmpInst.addOperand(Inst.getOperand(1));
903     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
904     Inst = TmpInst;
905     break;
906   }
907   case PPC::SUBIC: {
908     MCInst TmpInst;
909     TmpInst.setOpcode(PPC::ADDIC);
910     TmpInst.addOperand(Inst.getOperand(0));
911     TmpInst.addOperand(Inst.getOperand(1));
912     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
913     Inst = TmpInst;
914     break;
915   }
916   case PPC::SUBICo: {
917     MCInst TmpInst;
918     TmpInst.setOpcode(PPC::ADDICo);
919     TmpInst.addOperand(Inst.getOperand(0));
920     TmpInst.addOperand(Inst.getOperand(1));
921     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
922     Inst = TmpInst;
923     break;
924   }
925   case PPC::EXTLWI:
926   case PPC::EXTLWIo: {
927     MCInst TmpInst;
928     int64_t N = Inst.getOperand(2).getImm();
929     int64_t B = Inst.getOperand(3).getImm();
930     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
931     TmpInst.addOperand(Inst.getOperand(0));
932     TmpInst.addOperand(Inst.getOperand(1));
933     TmpInst.addOperand(MCOperand::createImm(B));
934     TmpInst.addOperand(MCOperand::createImm(0));
935     TmpInst.addOperand(MCOperand::createImm(N - 1));
936     Inst = TmpInst;
937     break;
938   }
939   case PPC::EXTRWI:
940   case PPC::EXTRWIo: {
941     MCInst TmpInst;
942     int64_t N = Inst.getOperand(2).getImm();
943     int64_t B = Inst.getOperand(3).getImm();
944     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
945     TmpInst.addOperand(Inst.getOperand(0));
946     TmpInst.addOperand(Inst.getOperand(1));
947     TmpInst.addOperand(MCOperand::createImm(B + N));
948     TmpInst.addOperand(MCOperand::createImm(32 - N));
949     TmpInst.addOperand(MCOperand::createImm(31));
950     Inst = TmpInst;
951     break;
952   }
953   case PPC::INSLWI:
954   case PPC::INSLWIo: {
955     MCInst TmpInst;
956     int64_t N = Inst.getOperand(2).getImm();
957     int64_t B = Inst.getOperand(3).getImm();
958     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
959     TmpInst.addOperand(Inst.getOperand(0));
960     TmpInst.addOperand(Inst.getOperand(0));
961     TmpInst.addOperand(Inst.getOperand(1));
962     TmpInst.addOperand(MCOperand::createImm(32 - B));
963     TmpInst.addOperand(MCOperand::createImm(B));
964     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
965     Inst = TmpInst;
966     break;
967   }
968   case PPC::INSRWI:
969   case PPC::INSRWIo: {
970     MCInst TmpInst;
971     int64_t N = Inst.getOperand(2).getImm();
972     int64_t B = Inst.getOperand(3).getImm();
973     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
974     TmpInst.addOperand(Inst.getOperand(0));
975     TmpInst.addOperand(Inst.getOperand(0));
976     TmpInst.addOperand(Inst.getOperand(1));
977     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
978     TmpInst.addOperand(MCOperand::createImm(B));
979     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
980     Inst = TmpInst;
981     break;
982   }
983   case PPC::ROTRWI:
984   case PPC::ROTRWIo: {
985     MCInst TmpInst;
986     int64_t N = Inst.getOperand(2).getImm();
987     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
988     TmpInst.addOperand(Inst.getOperand(0));
989     TmpInst.addOperand(Inst.getOperand(1));
990     TmpInst.addOperand(MCOperand::createImm(32 - N));
991     TmpInst.addOperand(MCOperand::createImm(0));
992     TmpInst.addOperand(MCOperand::createImm(31));
993     Inst = TmpInst;
994     break;
995   }
996   case PPC::SLWI:
997   case PPC::SLWIo: {
998     MCInst TmpInst;
999     int64_t N = Inst.getOperand(2).getImm();
1000     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1001     TmpInst.addOperand(Inst.getOperand(0));
1002     TmpInst.addOperand(Inst.getOperand(1));
1003     TmpInst.addOperand(MCOperand::createImm(N));
1004     TmpInst.addOperand(MCOperand::createImm(0));
1005     TmpInst.addOperand(MCOperand::createImm(31 - N));
1006     Inst = TmpInst;
1007     break;
1008   }
1009   case PPC::SRWI:
1010   case PPC::SRWIo: {
1011     MCInst TmpInst;
1012     int64_t N = Inst.getOperand(2).getImm();
1013     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1014     TmpInst.addOperand(Inst.getOperand(0));
1015     TmpInst.addOperand(Inst.getOperand(1));
1016     TmpInst.addOperand(MCOperand::createImm(32 - N));
1017     TmpInst.addOperand(MCOperand::createImm(N));
1018     TmpInst.addOperand(MCOperand::createImm(31));
1019     Inst = TmpInst;
1020     break;
1021   }
1022   case PPC::CLRRWI:
1023   case PPC::CLRRWIo: {
1024     MCInst TmpInst;
1025     int64_t N = Inst.getOperand(2).getImm();
1026     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1027     TmpInst.addOperand(Inst.getOperand(0));
1028     TmpInst.addOperand(Inst.getOperand(1));
1029     TmpInst.addOperand(MCOperand::createImm(0));
1030     TmpInst.addOperand(MCOperand::createImm(0));
1031     TmpInst.addOperand(MCOperand::createImm(31 - N));
1032     Inst = TmpInst;
1033     break;
1034   }
1035   case PPC::CLRLSLWI:
1036   case PPC::CLRLSLWIo: {
1037     MCInst TmpInst;
1038     int64_t B = Inst.getOperand(2).getImm();
1039     int64_t N = Inst.getOperand(3).getImm();
1040     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1041     TmpInst.addOperand(Inst.getOperand(0));
1042     TmpInst.addOperand(Inst.getOperand(1));
1043     TmpInst.addOperand(MCOperand::createImm(N));
1044     TmpInst.addOperand(MCOperand::createImm(B - N));
1045     TmpInst.addOperand(MCOperand::createImm(31 - N));
1046     Inst = TmpInst;
1047     break;
1048   }
1049   case PPC::EXTLDI:
1050   case PPC::EXTLDIo: {
1051     MCInst TmpInst;
1052     int64_t N = Inst.getOperand(2).getImm();
1053     int64_t B = Inst.getOperand(3).getImm();
1054     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1055     TmpInst.addOperand(Inst.getOperand(0));
1056     TmpInst.addOperand(Inst.getOperand(1));
1057     TmpInst.addOperand(MCOperand::createImm(B));
1058     TmpInst.addOperand(MCOperand::createImm(N - 1));
1059     Inst = TmpInst;
1060     break;
1061   }
1062   case PPC::EXTRDI:
1063   case PPC::EXTRDIo: {
1064     MCInst TmpInst;
1065     int64_t N = Inst.getOperand(2).getImm();
1066     int64_t B = Inst.getOperand(3).getImm();
1067     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1068     TmpInst.addOperand(Inst.getOperand(0));
1069     TmpInst.addOperand(Inst.getOperand(1));
1070     TmpInst.addOperand(MCOperand::createImm(B + N));
1071     TmpInst.addOperand(MCOperand::createImm(64 - N));
1072     Inst = TmpInst;
1073     break;
1074   }
1075   case PPC::INSRDI:
1076   case PPC::INSRDIo: {
1077     MCInst TmpInst;
1078     int64_t N = Inst.getOperand(2).getImm();
1079     int64_t B = Inst.getOperand(3).getImm();
1080     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1081     TmpInst.addOperand(Inst.getOperand(0));
1082     TmpInst.addOperand(Inst.getOperand(0));
1083     TmpInst.addOperand(Inst.getOperand(1));
1084     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1085     TmpInst.addOperand(MCOperand::createImm(B));
1086     Inst = TmpInst;
1087     break;
1088   }
1089   case PPC::ROTRDI:
1090   case PPC::ROTRDIo: {
1091     MCInst TmpInst;
1092     int64_t N = Inst.getOperand(2).getImm();
1093     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1094     TmpInst.addOperand(Inst.getOperand(0));
1095     TmpInst.addOperand(Inst.getOperand(1));
1096     TmpInst.addOperand(MCOperand::createImm(64 - N));
1097     TmpInst.addOperand(MCOperand::createImm(0));
1098     Inst = TmpInst;
1099     break;
1100   }
1101   case PPC::SLDI:
1102   case PPC::SLDIo: {
1103     MCInst TmpInst;
1104     int64_t N = Inst.getOperand(2).getImm();
1105     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1106     TmpInst.addOperand(Inst.getOperand(0));
1107     TmpInst.addOperand(Inst.getOperand(1));
1108     TmpInst.addOperand(MCOperand::createImm(N));
1109     TmpInst.addOperand(MCOperand::createImm(63 - N));
1110     Inst = TmpInst;
1111     break;
1112   }
1113   case PPC::SRDI:
1114   case PPC::SRDIo: {
1115     MCInst TmpInst;
1116     int64_t N = Inst.getOperand(2).getImm();
1117     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1118     TmpInst.addOperand(Inst.getOperand(0));
1119     TmpInst.addOperand(Inst.getOperand(1));
1120     TmpInst.addOperand(MCOperand::createImm(64 - N));
1121     TmpInst.addOperand(MCOperand::createImm(N));
1122     Inst = TmpInst;
1123     break;
1124   }
1125   case PPC::CLRRDI:
1126   case PPC::CLRRDIo: {
1127     MCInst TmpInst;
1128     int64_t N = Inst.getOperand(2).getImm();
1129     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1130     TmpInst.addOperand(Inst.getOperand(0));
1131     TmpInst.addOperand(Inst.getOperand(1));
1132     TmpInst.addOperand(MCOperand::createImm(0));
1133     TmpInst.addOperand(MCOperand::createImm(63 - N));
1134     Inst = TmpInst;
1135     break;
1136   }
1137   case PPC::CLRLSLDI:
1138   case PPC::CLRLSLDIo: {
1139     MCInst TmpInst;
1140     int64_t B = Inst.getOperand(2).getImm();
1141     int64_t N = Inst.getOperand(3).getImm();
1142     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1143     TmpInst.addOperand(Inst.getOperand(0));
1144     TmpInst.addOperand(Inst.getOperand(1));
1145     TmpInst.addOperand(MCOperand::createImm(N));
1146     TmpInst.addOperand(MCOperand::createImm(B - N));
1147     Inst = TmpInst;
1148     break;
1149   }
1150   case PPC::RLWINMbm:
1151   case PPC::RLWINMobm: {
1152     unsigned MB, ME;
1153     int64_t BM = Inst.getOperand(3).getImm();
1154     if (!isRunOfOnes(BM, MB, ME))
1155       break;
1156 
1157     MCInst TmpInst;
1158     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1159     TmpInst.addOperand(Inst.getOperand(0));
1160     TmpInst.addOperand(Inst.getOperand(1));
1161     TmpInst.addOperand(Inst.getOperand(2));
1162     TmpInst.addOperand(MCOperand::createImm(MB));
1163     TmpInst.addOperand(MCOperand::createImm(ME));
1164     Inst = TmpInst;
1165     break;
1166   }
1167   case PPC::RLWIMIbm:
1168   case PPC::RLWIMIobm: {
1169     unsigned MB, ME;
1170     int64_t BM = Inst.getOperand(3).getImm();
1171     if (!isRunOfOnes(BM, MB, ME))
1172       break;
1173 
1174     MCInst TmpInst;
1175     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1176     TmpInst.addOperand(Inst.getOperand(0));
1177     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1178     TmpInst.addOperand(Inst.getOperand(1));
1179     TmpInst.addOperand(Inst.getOperand(2));
1180     TmpInst.addOperand(MCOperand::createImm(MB));
1181     TmpInst.addOperand(MCOperand::createImm(ME));
1182     Inst = TmpInst;
1183     break;
1184   }
1185   case PPC::RLWNMbm:
1186   case PPC::RLWNMobm: {
1187     unsigned MB, ME;
1188     int64_t BM = Inst.getOperand(3).getImm();
1189     if (!isRunOfOnes(BM, MB, ME))
1190       break;
1191 
1192     MCInst TmpInst;
1193     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1194     TmpInst.addOperand(Inst.getOperand(0));
1195     TmpInst.addOperand(Inst.getOperand(1));
1196     TmpInst.addOperand(Inst.getOperand(2));
1197     TmpInst.addOperand(MCOperand::createImm(MB));
1198     TmpInst.addOperand(MCOperand::createImm(ME));
1199     Inst = TmpInst;
1200     break;
1201   }
1202   case PPC::MFTB: {
1203     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1204       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1205       Inst.setOpcode(PPC::MFSPR);
1206     }
1207     break;
1208   }
1209   case PPC::CP_COPYx:
1210   case PPC::CP_COPY_FIRST: {
1211     MCInst TmpInst;
1212     TmpInst.setOpcode(PPC::CP_COPY);
1213     TmpInst.addOperand(Inst.getOperand(0));
1214     TmpInst.addOperand(Inst.getOperand(1));
1215     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1216 
1217     Inst = TmpInst;
1218     break;
1219   }
1220   case PPC::CP_PASTEx :
1221   case PPC::CP_PASTE_LAST: {
1222     MCInst TmpInst;
1223     TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1224                       PPC::CP_PASTE : PPC::CP_PASTEo);
1225     TmpInst.addOperand(Inst.getOperand(0));
1226     TmpInst.addOperand(Inst.getOperand(1));
1227     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1228 
1229     Inst = TmpInst;
1230     break;
1231   }
1232   // ISA3.0 Instructions:
1233   case PPC::SUBPCIS:
1234   case PPC::LNIA: {
1235     MCInst TmpInst;
1236     TmpInst.setOpcode(PPC::ADDPCIS);
1237     TmpInst.addOperand(Inst.getOperand(0));
1238     if (Opcode == PPC::SUBPCIS)
1239       addNegOperand(TmpInst, Inst.getOperand(1), getContext());
1240     else
1241       TmpInst.addOperand(MCOperand::createImm(0));
1242     Inst = TmpInst;
1243     break;
1244   }
1245   }
1246 }
1247 
1248 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1249                                            OperandVector &Operands,
1250                                            MCStreamer &Out, uint64_t &ErrorInfo,
1251                                            bool MatchingInlineAsm) {
1252   MCInst Inst;
1253 
1254   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1255   case Match_Success:
1256     // Post-process instructions (typically extended mnemonics)
1257     ProcessInstruction(Inst, Operands);
1258     Inst.setLoc(IDLoc);
1259     Out.EmitInstruction(Inst, getSTI());
1260     return false;
1261   case Match_MissingFeature:
1262     return Error(IDLoc, "instruction use requires an option to be enabled");
1263   case Match_MnemonicFail:
1264     return Error(IDLoc, "unrecognized instruction mnemonic");
1265   case Match_InvalidOperand: {
1266     SMLoc ErrorLoc = IDLoc;
1267     if (ErrorInfo != ~0ULL) {
1268       if (ErrorInfo >= Operands.size())
1269         return Error(IDLoc, "too few operands for instruction");
1270 
1271       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1272       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1273     }
1274 
1275     return Error(ErrorLoc, "invalid operand for instruction");
1276   }
1277   }
1278 
1279   llvm_unreachable("Implement any new match types added!");
1280 }
1281 
1282 bool PPCAsmParser::
1283 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1284   if (Tok.is(AsmToken::Identifier)) {
1285     StringRef Name = Tok.getString();
1286 
1287     if (Name.equals_lower("lr")) {
1288       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1289       IntVal = 8;
1290       return false;
1291     } else if (Name.equals_lower("ctr")) {
1292       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1293       IntVal = 9;
1294       return false;
1295     } else if (Name.equals_lower("vrsave")) {
1296       RegNo = PPC::VRSAVE;
1297       IntVal = 256;
1298       return false;
1299     } else if (Name.startswith_lower("r") &&
1300                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1301       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1302       return false;
1303     } else if (Name.startswith_lower("f") &&
1304                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1305       RegNo = FRegs[IntVal];
1306       return false;
1307     } else if (Name.startswith_lower("vs") &&
1308                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1309       RegNo = VSRegs[IntVal];
1310       return false;
1311     } else if (Name.startswith_lower("v") &&
1312                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1313       RegNo = VRegs[IntVal];
1314       return false;
1315     } else if (Name.startswith_lower("q") &&
1316                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1317       RegNo = QFRegs[IntVal];
1318       return false;
1319     } else if (Name.startswith_lower("cr") &&
1320                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1321       RegNo = CRRegs[IntVal];
1322       return false;
1323     }
1324   }
1325 
1326   return true;
1327 }
1328 
1329 bool PPCAsmParser::
1330 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1331   MCAsmParser &Parser = getParser();
1332   const AsmToken &Tok = Parser.getTok();
1333   StartLoc = Tok.getLoc();
1334   EndLoc = Tok.getEndLoc();
1335   RegNo = 0;
1336   int64_t IntVal;
1337 
1338   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1339     Parser.Lex(); // Eat identifier token.
1340     return false;
1341   }
1342 
1343   return Error(StartLoc, "invalid register name");
1344 }
1345 
1346 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1347 /// the expression and check for VK_PPC_LO/HI/HA
1348 /// symbol variants.  If all symbols with modifier use the same
1349 /// variant, return the corresponding PPCMCExpr::VariantKind,
1350 /// and a modified expression using the default symbol variant.
1351 /// Otherwise, return NULL.
1352 const MCExpr *PPCAsmParser::
1353 ExtractModifierFromExpr(const MCExpr *E,
1354                         PPCMCExpr::VariantKind &Variant) {
1355   MCContext &Context = getParser().getContext();
1356   Variant = PPCMCExpr::VK_PPC_None;
1357 
1358   switch (E->getKind()) {
1359   case MCExpr::Target:
1360   case MCExpr::Constant:
1361     return nullptr;
1362 
1363   case MCExpr::SymbolRef: {
1364     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1365 
1366     switch (SRE->getKind()) {
1367     case MCSymbolRefExpr::VK_PPC_LO:
1368       Variant = PPCMCExpr::VK_PPC_LO;
1369       break;
1370     case MCSymbolRefExpr::VK_PPC_HI:
1371       Variant = PPCMCExpr::VK_PPC_HI;
1372       break;
1373     case MCSymbolRefExpr::VK_PPC_HA:
1374       Variant = PPCMCExpr::VK_PPC_HA;
1375       break;
1376     case MCSymbolRefExpr::VK_PPC_HIGHER:
1377       Variant = PPCMCExpr::VK_PPC_HIGHER;
1378       break;
1379     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1380       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1381       break;
1382     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1383       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1384       break;
1385     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1386       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1387       break;
1388     default:
1389       return nullptr;
1390     }
1391 
1392     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1393   }
1394 
1395   case MCExpr::Unary: {
1396     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1397     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1398     if (!Sub)
1399       return nullptr;
1400     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1401   }
1402 
1403   case MCExpr::Binary: {
1404     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1405     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1406     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1407     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1408 
1409     if (!LHS && !RHS)
1410       return nullptr;
1411 
1412     if (!LHS) LHS = BE->getLHS();
1413     if (!RHS) RHS = BE->getRHS();
1414 
1415     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1416       Variant = RHSVariant;
1417     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1418       Variant = LHSVariant;
1419     else if (LHSVariant == RHSVariant)
1420       Variant = LHSVariant;
1421     else
1422       return nullptr;
1423 
1424     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1425   }
1426   }
1427 
1428   llvm_unreachable("Invalid expression kind!");
1429 }
1430 
1431 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1432 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1433 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1434 /// FIXME: This is a hack.
1435 const MCExpr *PPCAsmParser::
1436 FixupVariantKind(const MCExpr *E) {
1437   MCContext &Context = getParser().getContext();
1438 
1439   switch (E->getKind()) {
1440   case MCExpr::Target:
1441   case MCExpr::Constant:
1442     return E;
1443 
1444   case MCExpr::SymbolRef: {
1445     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1446     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1447 
1448     switch (SRE->getKind()) {
1449     case MCSymbolRefExpr::VK_TLSGD:
1450       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1451       break;
1452     case MCSymbolRefExpr::VK_TLSLD:
1453       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1454       break;
1455     default:
1456       return E;
1457     }
1458     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1459   }
1460 
1461   case MCExpr::Unary: {
1462     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1463     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1464     if (Sub == UE->getSubExpr())
1465       return E;
1466     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1467   }
1468 
1469   case MCExpr::Binary: {
1470     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1471     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1472     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1473     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1474       return E;
1475     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1476   }
1477   }
1478 
1479   llvm_unreachable("Invalid expression kind!");
1480 }
1481 
1482 /// ParseExpression.  This differs from the default "parseExpression" in that
1483 /// it handles modifiers.
1484 bool PPCAsmParser::
1485 ParseExpression(const MCExpr *&EVal) {
1486 
1487   if (isDarwin())
1488     return ParseDarwinExpression(EVal);
1489 
1490   // (ELF Platforms)
1491   // Handle \code @l/@ha \endcode
1492   if (getParser().parseExpression(EVal))
1493     return true;
1494 
1495   EVal = FixupVariantKind(EVal);
1496 
1497   PPCMCExpr::VariantKind Variant;
1498   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1499   if (E)
1500     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1501 
1502   return false;
1503 }
1504 
1505 /// ParseDarwinExpression.  (MachO Platforms)
1506 /// This differs from the default "parseExpression" in that it handles detection
1507 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1508 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1509 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1510 /// for this to be done at a higher level.
1511 bool PPCAsmParser::
1512 ParseDarwinExpression(const MCExpr *&EVal) {
1513   MCAsmParser &Parser = getParser();
1514   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1515   switch (getLexer().getKind()) {
1516   default:
1517     break;
1518   case AsmToken::Identifier:
1519     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1520     // something starting with any other char should be part of the
1521     // asm syntax.  If handwritten asm includes an identifier like lo16,
1522     // then all bets are off - but no-one would do that, right?
1523     StringRef poss = Parser.getTok().getString();
1524     if (poss.equals_lower("lo16")) {
1525       Variant = PPCMCExpr::VK_PPC_LO;
1526     } else if (poss.equals_lower("hi16")) {
1527       Variant = PPCMCExpr::VK_PPC_HI;
1528     } else if (poss.equals_lower("ha16")) {
1529       Variant = PPCMCExpr::VK_PPC_HA;
1530     }
1531     if (Variant != PPCMCExpr::VK_PPC_None) {
1532       Parser.Lex(); // Eat the xx16
1533       if (getLexer().isNot(AsmToken::LParen))
1534         return Error(Parser.getTok().getLoc(), "expected '('");
1535       Parser.Lex(); // Eat the '('
1536     }
1537     break;
1538   }
1539 
1540   if (getParser().parseExpression(EVal))
1541     return true;
1542 
1543   if (Variant != PPCMCExpr::VK_PPC_None) {
1544     if (getLexer().isNot(AsmToken::RParen))
1545       return Error(Parser.getTok().getLoc(), "expected ')'");
1546     Parser.Lex(); // Eat the ')'
1547     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1548   }
1549   return false;
1550 }
1551 
1552 /// ParseOperand
1553 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1554 /// rNN for MachO.
1555 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1556   MCAsmParser &Parser = getParser();
1557   SMLoc S = Parser.getTok().getLoc();
1558   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1559   const MCExpr *EVal;
1560 
1561   // Attempt to parse the next token as an immediate
1562   switch (getLexer().getKind()) {
1563   // Special handling for register names.  These are interpreted
1564   // as immediates corresponding to the register number.
1565   case AsmToken::Percent:
1566     Parser.Lex(); // Eat the '%'.
1567     unsigned RegNo;
1568     int64_t IntVal;
1569     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1570       Parser.Lex(); // Eat the identifier token.
1571       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1572       return false;
1573     }
1574     return Error(S, "invalid register name");
1575 
1576   case AsmToken::Identifier:
1577     // Note that non-register-name identifiers from the compiler will begin
1578     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1579     // identifiers like r31foo - so we fall through in the event that parsing
1580     // a register name fails.
1581     if (isDarwin()) {
1582       unsigned RegNo;
1583       int64_t IntVal;
1584       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1585         Parser.Lex(); // Eat the identifier token.
1586         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1587         return false;
1588       }
1589     }
1590   // Fall-through to process non-register-name identifiers as expression.
1591   // All other expressions
1592   case AsmToken::LParen:
1593   case AsmToken::Plus:
1594   case AsmToken::Minus:
1595   case AsmToken::Integer:
1596   case AsmToken::Dot:
1597   case AsmToken::Dollar:
1598   case AsmToken::Exclaim:
1599   case AsmToken::Tilde:
1600     if (!ParseExpression(EVal))
1601       break;
1602     /* fall through */
1603   default:
1604     return Error(S, "unknown operand");
1605   }
1606 
1607   // Push the parsed operand into the list of operands
1608   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1609 
1610   // Check whether this is a TLS call expression
1611   bool TLSCall = false;
1612   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1613     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1614 
1615   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1616     const MCExpr *TLSSym;
1617 
1618     Parser.Lex(); // Eat the '('.
1619     S = Parser.getTok().getLoc();
1620     if (ParseExpression(TLSSym))
1621       return Error(S, "invalid TLS call expression");
1622     if (getLexer().isNot(AsmToken::RParen))
1623       return Error(Parser.getTok().getLoc(), "missing ')'");
1624     E = Parser.getTok().getLoc();
1625     Parser.Lex(); // Eat the ')'.
1626 
1627     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1628   }
1629 
1630   // Otherwise, check for D-form memory operands
1631   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1632     Parser.Lex(); // Eat the '('.
1633     S = Parser.getTok().getLoc();
1634 
1635     int64_t IntVal;
1636     switch (getLexer().getKind()) {
1637     case AsmToken::Percent:
1638       Parser.Lex(); // Eat the '%'.
1639       unsigned RegNo;
1640       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1641         return Error(S, "invalid register name");
1642       Parser.Lex(); // Eat the identifier token.
1643       break;
1644 
1645     case AsmToken::Integer:
1646       if (!isDarwin()) {
1647         if (getParser().parseAbsoluteExpression(IntVal) ||
1648           IntVal < 0 || IntVal > 31)
1649         return Error(S, "invalid register number");
1650       } else {
1651         return Error(S, "unexpected integer value");
1652       }
1653       break;
1654 
1655    case AsmToken::Identifier:
1656     if (isDarwin()) {
1657       unsigned RegNo;
1658       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1659         Parser.Lex(); // Eat the identifier token.
1660         break;
1661       }
1662     }
1663     // Fall-through..
1664 
1665     default:
1666       return Error(S, "invalid memory operand");
1667     }
1668 
1669     if (getLexer().isNot(AsmToken::RParen))
1670       return Error(Parser.getTok().getLoc(), "missing ')'");
1671     E = Parser.getTok().getLoc();
1672     Parser.Lex(); // Eat the ')'.
1673 
1674     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1675   }
1676 
1677   return false;
1678 }
1679 
1680 /// Parse an instruction mnemonic followed by its operands.
1681 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1682                                     SMLoc NameLoc, OperandVector &Operands) {
1683   // The first operand is the token for the instruction name.
1684   // If the next character is a '+' or '-', we need to add it to the
1685   // instruction name, to match what TableGen is doing.
1686   std::string NewOpcode;
1687   if (getLexer().is(AsmToken::Plus)) {
1688     getLexer().Lex();
1689     NewOpcode = Name;
1690     NewOpcode += '+';
1691     Name = NewOpcode;
1692   }
1693   if (getLexer().is(AsmToken::Minus)) {
1694     getLexer().Lex();
1695     NewOpcode = Name;
1696     NewOpcode += '-';
1697     Name = NewOpcode;
1698   }
1699   // If the instruction ends in a '.', we need to create a separate
1700   // token for it, to match what TableGen is doing.
1701   size_t Dot = Name.find('.');
1702   StringRef Mnemonic = Name.slice(0, Dot);
1703   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1704     Operands.push_back(
1705         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1706   else
1707     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1708   if (Dot != StringRef::npos) {
1709     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1710     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1711     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1712       Operands.push_back(
1713           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1714     else
1715       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1716   }
1717 
1718   // If there are no more operands then finish
1719   if (getLexer().is(AsmToken::EndOfStatement))
1720     return false;
1721 
1722   // Parse the first operand
1723   if (ParseOperand(Operands))
1724     return true;
1725 
1726   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1727          getLexer().is(AsmToken::Comma)) {
1728     // Consume the comma token
1729     getLexer().Lex();
1730 
1731     // Parse the next operand
1732     if (ParseOperand(Operands))
1733       return true;
1734   }
1735 
1736   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1737   // and dcbtst instructions differs for server vs. embedded cores.
1738   //  The syntax for dcbt is:
1739   //    dcbt ra, rb, th [server]
1740   //    dcbt th, ra, rb [embedded]
1741   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1742   //  server form to be the default, so swap the operands if we're parsing for
1743   //  an embedded core (they'll be swapped again upon printing).
1744   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1745       Operands.size() == 4 &&
1746       (Name == "dcbt" || Name == "dcbtst")) {
1747     std::swap(Operands[1], Operands[3]);
1748     std::swap(Operands[2], Operands[1]);
1749   }
1750 
1751   return false;
1752 }
1753 
1754 /// ParseDirective parses the PPC specific directives
1755 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1756   StringRef IDVal = DirectiveID.getIdentifier();
1757   if (!isDarwin()) {
1758     if (IDVal == ".word")
1759       return ParseDirectiveWord(2, DirectiveID.getLoc());
1760     if (IDVal == ".llong")
1761       return ParseDirectiveWord(8, DirectiveID.getLoc());
1762     if (IDVal == ".tc")
1763       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1764     if (IDVal == ".machine")
1765       return ParseDirectiveMachine(DirectiveID.getLoc());
1766     if (IDVal == ".abiversion")
1767       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1768     if (IDVal == ".localentry")
1769       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1770   } else {
1771     if (IDVal == ".machine")
1772       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1773   }
1774   return true;
1775 }
1776 
1777 /// ParseDirectiveWord
1778 ///  ::= .word [ expression (, expression)* ]
1779 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1780   MCAsmParser &Parser = getParser();
1781   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1782     for (;;) {
1783       const MCExpr *Value;
1784       SMLoc ExprLoc = getLexer().getLoc();
1785       if (getParser().parseExpression(Value))
1786         return false;
1787 
1788       if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1789         assert(Size <= 8 && "Invalid size");
1790         uint64_t IntValue = MCE->getValue();
1791         if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1792           return Error(ExprLoc, "literal value out of range for directive");
1793         getStreamer().EmitIntValue(IntValue, Size);
1794       } else {
1795         getStreamer().EmitValue(Value, Size, ExprLoc);
1796       }
1797 
1798       if (getLexer().is(AsmToken::EndOfStatement))
1799         break;
1800 
1801       if (getLexer().isNot(AsmToken::Comma))
1802         return Error(L, "unexpected token in directive");
1803       Parser.Lex();
1804     }
1805   }
1806 
1807   Parser.Lex();
1808   return false;
1809 }
1810 
1811 /// ParseDirectiveTC
1812 ///  ::= .tc [ symbol (, expression)* ]
1813 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1814   MCAsmParser &Parser = getParser();
1815   // Skip TC symbol, which is only used with XCOFF.
1816   while (getLexer().isNot(AsmToken::EndOfStatement)
1817          && getLexer().isNot(AsmToken::Comma))
1818     Parser.Lex();
1819   if (getLexer().isNot(AsmToken::Comma)) {
1820     Error(L, "unexpected token in directive");
1821     return false;
1822   }
1823   Parser.Lex();
1824 
1825   // Align to word size.
1826   getParser().getStreamer().EmitValueToAlignment(Size);
1827 
1828   // Emit expressions.
1829   return ParseDirectiveWord(Size, L);
1830 }
1831 
1832 /// ParseDirectiveMachine (ELF platforms)
1833 ///  ::= .machine [ cpu | "push" | "pop" ]
1834 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1835   MCAsmParser &Parser = getParser();
1836   if (getLexer().isNot(AsmToken::Identifier) &&
1837       getLexer().isNot(AsmToken::String)) {
1838     Error(L, "unexpected token in directive");
1839     return false;
1840   }
1841 
1842   StringRef CPU = Parser.getTok().getIdentifier();
1843   Parser.Lex();
1844 
1845   // FIXME: Right now, the parser always allows any available
1846   // instruction, so the .machine directive is not useful.
1847   // Implement ".machine any" (by doing nothing) for the benefit
1848   // of existing assembler code.  Likewise, we can then implement
1849   // ".machine push" and ".machine pop" as no-op.
1850   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1851     Error(L, "unrecognized machine type");
1852     return false;
1853   }
1854 
1855   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1856     Error(L, "unexpected token in directive");
1857     return false;
1858   }
1859   PPCTargetStreamer &TStreamer =
1860       *static_cast<PPCTargetStreamer *>(
1861            getParser().getStreamer().getTargetStreamer());
1862   TStreamer.emitMachine(CPU);
1863 
1864   return false;
1865 }
1866 
1867 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1868 ///  ::= .machine cpu-identifier
1869 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1870   MCAsmParser &Parser = getParser();
1871   if (getLexer().isNot(AsmToken::Identifier) &&
1872       getLexer().isNot(AsmToken::String)) {
1873     Error(L, "unexpected token in directive");
1874     return false;
1875   }
1876 
1877   StringRef CPU = Parser.getTok().getIdentifier();
1878   Parser.Lex();
1879 
1880   // FIXME: this is only the 'default' set of cpu variants.
1881   // However we don't act on this information at present, this is simply
1882   // allowing parsing to proceed with minimal sanity checking.
1883   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1884     Error(L, "unrecognized cpu type");
1885     return false;
1886   }
1887 
1888   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1889     Error(L, "wrong cpu type specified for 64bit");
1890     return false;
1891   }
1892   if (!isPPC64() && CPU == "ppc64") {
1893     Error(L, "wrong cpu type specified for 32bit");
1894     return false;
1895   }
1896 
1897   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1898     Error(L, "unexpected token in directive");
1899     return false;
1900   }
1901 
1902   return false;
1903 }
1904 
1905 /// ParseDirectiveAbiVersion
1906 ///  ::= .abiversion constant-expression
1907 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1908   int64_t AbiVersion;
1909   if (getParser().parseAbsoluteExpression(AbiVersion)){
1910     Error(L, "expected constant expression");
1911     return false;
1912   }
1913   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1914     Error(L, "unexpected token in directive");
1915     return false;
1916   }
1917 
1918   PPCTargetStreamer &TStreamer =
1919       *static_cast<PPCTargetStreamer *>(
1920            getParser().getStreamer().getTargetStreamer());
1921   TStreamer.emitAbiVersion(AbiVersion);
1922 
1923   return false;
1924 }
1925 
1926 /// ParseDirectiveLocalEntry
1927 ///  ::= .localentry symbol, expression
1928 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1929   StringRef Name;
1930   if (getParser().parseIdentifier(Name)) {
1931     Error(L, "expected identifier in directive");
1932     return false;
1933   }
1934   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1935 
1936   if (getLexer().isNot(AsmToken::Comma)) {
1937     Error(L, "unexpected token in directive");
1938     return false;
1939   }
1940   Lex();
1941 
1942   const MCExpr *Expr;
1943   if (getParser().parseExpression(Expr)) {
1944     Error(L, "expected expression");
1945     return false;
1946   }
1947 
1948   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1949     Error(L, "unexpected token in directive");
1950     return false;
1951   }
1952 
1953   PPCTargetStreamer &TStreamer =
1954       *static_cast<PPCTargetStreamer *>(
1955            getParser().getStreamer().getTargetStreamer());
1956   TStreamer.emitLocalEntry(Sym, Expr);
1957 
1958   return false;
1959 }
1960 
1961 
1962 
1963 /// Force static initialization.
1964 extern "C" void LLVMInitializePowerPCAsmParser() {
1965   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1966   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1967   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1968 }
1969 
1970 #define GET_REGISTER_MATCHER
1971 #define GET_MATCHER_IMPLEMENTATION
1972 #include "PPCGenAsmMatcher.inc"
1973 
1974 // Define this matcher function after the auto-generated include so we
1975 // have the match class enum definitions.
1976 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1977                                                   unsigned Kind) {
1978   // If the kind is a token for a literal immediate, check if our asm
1979   // operand matches. This is for InstAliases which have a fixed-value
1980   // immediate in the syntax.
1981   int64_t ImmVal;
1982   switch (Kind) {
1983     case MCK_0: ImmVal = 0; break;
1984     case MCK_1: ImmVal = 1; break;
1985     case MCK_2: ImmVal = 2; break;
1986     case MCK_3: ImmVal = 3; break;
1987     case MCK_4: ImmVal = 4; break;
1988     case MCK_5: ImmVal = 5; break;
1989     case MCK_6: ImmVal = 6; break;
1990     case MCK_7: ImmVal = 7; break;
1991     default: return Match_InvalidOperand;
1992   }
1993 
1994   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1995   if (Op.isImm() && Op.getImm() == ImmVal)
1996     return Match_Success;
1997 
1998   return Match_InvalidOperand;
1999 }
2000 
2001 const MCExpr *
2002 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
2003                                   MCSymbolRefExpr::VariantKind Variant,
2004                                   MCContext &Ctx) {
2005   switch (Variant) {
2006   case MCSymbolRefExpr::VK_PPC_LO:
2007     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
2008   case MCSymbolRefExpr::VK_PPC_HI:
2009     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
2010   case MCSymbolRefExpr::VK_PPC_HA:
2011     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
2012   case MCSymbolRefExpr::VK_PPC_HIGHER:
2013     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
2014   case MCSymbolRefExpr::VK_PPC_HIGHERA:
2015     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
2016   case MCSymbolRefExpr::VK_PPC_HIGHEST:
2017     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
2018   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
2019     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
2020   default:
2021     return nullptr;
2022   }
2023 }
2024