1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCExpr.h"
11 #include "MCTargetDesc/PPCMCTargetDesc.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/StringSwitch.h"
15 #include "llvm/ADT/Twine.h"
16 #include "llvm/MC/MCContext.h"
17 #include "llvm/MC/MCExpr.h"
18 #include "llvm/MC/MCInst.h"
19 #include "llvm/MC/MCInstrInfo.h"
20 #include "llvm/MC/MCParser/MCAsmLexer.h"
21 #include "llvm/MC/MCParser/MCAsmParser.h"
22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
23 #include "llvm/MC/MCParser/MCTargetAsmParser.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCSymbolELF.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 static const MCPhysReg RRegs[32] = {
35   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
36   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
37   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
38   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
39   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
40   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
41   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
42   PPC::R28, PPC::R29, PPC::R30, PPC::R31
43 };
44 static const MCPhysReg RRegsNoR0[32] = {
45   PPC::ZERO,
46             PPC::R1,  PPC::R2,  PPC::R3,
47   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
48   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
49   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
50   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
51   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
52   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
53   PPC::R28, PPC::R29, PPC::R30, PPC::R31
54 };
55 static const MCPhysReg XRegs[32] = {
56   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
57   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
58   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
59   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
60   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
61   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
62   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
63   PPC::X28, PPC::X29, PPC::X30, PPC::X31
64 };
65 static const MCPhysReg XRegsNoX0[32] = {
66   PPC::ZERO8,
67             PPC::X1,  PPC::X2,  PPC::X3,
68   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
69   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
70   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
71   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
72   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
73   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
74   PPC::X28, PPC::X29, PPC::X30, PPC::X31
75 };
76 static const MCPhysReg FRegs[32] = {
77   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
78   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
79   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
80   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
81   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
82   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
83   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
84   PPC::F28, PPC::F29, PPC::F30, PPC::F31
85 };
86 static const MCPhysReg VFRegs[32] = {
87   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
88   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
89   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
90   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
91   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
92   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
93   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
94   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
95 };
96 static const MCPhysReg VRegs[32] = {
97   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
98   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
99   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
100   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
101   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
102   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
103   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
104   PPC::V28, PPC::V29, PPC::V30, PPC::V31
105 };
106 static const MCPhysReg VSRegs[64] = {
107   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
108   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
109   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
110   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
111   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
112   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
113   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
114   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
115 
116   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
117   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
118   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
119   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
120   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
121   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
122   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
123   PPC::V28, PPC::V29, PPC::V30, PPC::V31
124 };
125 static const MCPhysReg VSFRegs[64] = {
126   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
127   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
128   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
129   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
130   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
131   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
132   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
133   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
134 
135   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
136   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
137   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
138   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
139   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
140   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
141   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
142   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
143 };
144 static const MCPhysReg VSSRegs[64] = {
145   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
146   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
147   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
148   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
149   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
150   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
151   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
152   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
153 
154   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
155   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
156   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
157   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
158   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
159   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
160   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
161   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
162 };
163 static unsigned QFRegs[32] = {
164   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
165   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
166   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
167   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
168   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
169   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
170   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
171   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
172 };
173 static const MCPhysReg CRBITRegs[32] = {
174   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
175   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
176   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
177   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
178   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
179   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
180   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
181   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
182 };
183 static const MCPhysReg CRRegs[8] = {
184   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
185   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
186 };
187 
188 // Evaluate an expression containing condition register
189 // or condition register field symbols.  Returns positive
190 // value on success, or -1 on error.
191 static int64_t
192 EvaluateCRExpr(const MCExpr *E) {
193   switch (E->getKind()) {
194   case MCExpr::Target:
195     return -1;
196 
197   case MCExpr::Constant: {
198     int64_t Res = cast<MCConstantExpr>(E)->getValue();
199     return Res < 0 ? -1 : Res;
200   }
201 
202   case MCExpr::SymbolRef: {
203     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
204     StringRef Name = SRE->getSymbol().getName();
205 
206     if (Name == "lt") return 0;
207     if (Name == "gt") return 1;
208     if (Name == "eq") return 2;
209     if (Name == "so") return 3;
210     if (Name == "un") return 3;
211 
212     if (Name == "cr0") return 0;
213     if (Name == "cr1") return 1;
214     if (Name == "cr2") return 2;
215     if (Name == "cr3") return 3;
216     if (Name == "cr4") return 4;
217     if (Name == "cr5") return 5;
218     if (Name == "cr6") return 6;
219     if (Name == "cr7") return 7;
220 
221     return -1;
222   }
223 
224   case MCExpr::Unary:
225     return -1;
226 
227   case MCExpr::Binary: {
228     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
229     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
230     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
231     int64_t Res;
232 
233     if (LHSVal < 0 || RHSVal < 0)
234       return -1;
235 
236     switch (BE->getOpcode()) {
237     default: return -1;
238     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
239     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
240     }
241 
242     return Res < 0 ? -1 : Res;
243   }
244   }
245 
246   llvm_unreachable("Invalid expression kind!");
247 }
248 
249 namespace {
250 
251 struct PPCOperand;
252 
253 class PPCAsmParser : public MCTargetAsmParser {
254   const MCInstrInfo &MII;
255   bool IsPPC64;
256   bool IsDarwin;
257 
258   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
259 
260   bool isPPC64() const { return IsPPC64; }
261   bool isDarwin() const { return IsDarwin; }
262 
263   bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal);
264 
265   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
266 
267   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
268                                         PPCMCExpr::VariantKind &Variant);
269   const MCExpr *FixupVariantKind(const MCExpr *E);
270   bool ParseExpression(const MCExpr *&EVal);
271   bool ParseDarwinExpression(const MCExpr *&EVal);
272 
273   bool ParseOperand(OperandVector &Operands);
274 
275   bool ParseDirectiveWord(unsigned Size, AsmToken ID);
276   bool ParseDirectiveTC(unsigned Size, AsmToken ID);
277   bool ParseDirectiveMachine(SMLoc L);
278   bool ParseDarwinDirectiveMachine(SMLoc L);
279   bool ParseDirectiveAbiVersion(SMLoc L);
280   bool ParseDirectiveLocalEntry(SMLoc L);
281 
282   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
283                                OperandVector &Operands, MCStreamer &Out,
284                                uint64_t &ErrorInfo,
285                                bool MatchingInlineAsm) override;
286 
287   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
288 
289   /// @name Auto-generated Match Functions
290   /// {
291 
292 #define GET_ASSEMBLER_HEADER
293 #include "PPCGenAsmMatcher.inc"
294 
295   /// }
296 
297 
298 public:
299   PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &,
300                const MCInstrInfo &MII, const MCTargetOptions &Options)
301     : MCTargetAsmParser(Options, STI), MII(MII) {
302     // Check for 64-bit vs. 32-bit pointer mode.
303     const Triple &TheTriple = STI.getTargetTriple();
304     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
305                TheTriple.getArch() == Triple::ppc64le);
306     IsDarwin = TheTriple.isMacOSX();
307     // Initialize the set of available features.
308     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
309   }
310 
311   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
312                         SMLoc NameLoc, OperandVector &Operands) override;
313 
314   bool ParseDirective(AsmToken DirectiveID) override;
315 
316   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
317                                       unsigned Kind) override;
318 
319   const MCExpr *applyModifierToExpr(const MCExpr *E,
320                                     MCSymbolRefExpr::VariantKind,
321                                     MCContext &Ctx) override;
322 };
323 
324 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
325 /// instruction.
326 struct PPCOperand : public MCParsedAsmOperand {
327   enum KindTy {
328     Token,
329     Immediate,
330     ContextImmediate,
331     Expression,
332     TLSRegister
333   } Kind;
334 
335   SMLoc StartLoc, EndLoc;
336   bool IsPPC64;
337 
338   struct TokOp {
339     const char *Data;
340     unsigned Length;
341   };
342 
343   struct ImmOp {
344     int64_t Val;
345   };
346 
347   struct ExprOp {
348     const MCExpr *Val;
349     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
350   };
351 
352   struct TLSRegOp {
353     const MCSymbolRefExpr *Sym;
354   };
355 
356   union {
357     struct TokOp Tok;
358     struct ImmOp Imm;
359     struct ExprOp Expr;
360     struct TLSRegOp TLSReg;
361   };
362 
363   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
364 public:
365   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
366     Kind = o.Kind;
367     StartLoc = o.StartLoc;
368     EndLoc = o.EndLoc;
369     IsPPC64 = o.IsPPC64;
370     switch (Kind) {
371     case Token:
372       Tok = o.Tok;
373       break;
374     case Immediate:
375     case ContextImmediate:
376       Imm = o.Imm;
377       break;
378     case Expression:
379       Expr = o.Expr;
380       break;
381     case TLSRegister:
382       TLSReg = o.TLSReg;
383       break;
384     }
385   }
386 
387   // Disable use of sized deallocation due to overallocation of PPCOperand
388   // objects in CreateTokenWithStringCopy.
389   void operator delete(void *p) { ::operator delete(p); }
390 
391   /// getStartLoc - Get the location of the first token of this operand.
392   SMLoc getStartLoc() const override { return StartLoc; }
393 
394   /// getEndLoc - Get the location of the last token of this operand.
395   SMLoc getEndLoc() const override { return EndLoc; }
396 
397   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
398   bool isPPC64() const { return IsPPC64; }
399 
400   int64_t getImm() const {
401     assert(Kind == Immediate && "Invalid access!");
402     return Imm.Val;
403   }
404   int64_t getImmS16Context() const {
405     assert((Kind == Immediate || Kind == ContextImmediate) &&
406            "Invalid access!");
407     if (Kind == Immediate)
408       return Imm.Val;
409     return static_cast<int16_t>(Imm.Val);
410   }
411   int64_t getImmU16Context() const {
412     assert((Kind == Immediate || Kind == ContextImmediate) &&
413            "Invalid access!");
414     return Imm.Val;
415   }
416 
417   const MCExpr *getExpr() const {
418     assert(Kind == Expression && "Invalid access!");
419     return Expr.Val;
420   }
421 
422   int64_t getExprCRVal() const {
423     assert(Kind == Expression && "Invalid access!");
424     return Expr.CRVal;
425   }
426 
427   const MCExpr *getTLSReg() const {
428     assert(Kind == TLSRegister && "Invalid access!");
429     return TLSReg.Sym;
430   }
431 
432   unsigned getReg() const override {
433     assert(isRegNumber() && "Invalid access!");
434     return (unsigned) Imm.Val;
435   }
436 
437   unsigned getVSReg() const {
438     assert(isVSRegNumber() && "Invalid access!");
439     return (unsigned) Imm.Val;
440   }
441 
442   unsigned getCCReg() const {
443     assert(isCCRegNumber() && "Invalid access!");
444     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
445   }
446 
447   unsigned getCRBit() const {
448     assert(isCRBitNumber() && "Invalid access!");
449     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
450   }
451 
452   unsigned getCRBitMask() const {
453     assert(isCRBitMask() && "Invalid access!");
454     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
455   }
456 
457   bool isToken() const override { return Kind == Token; }
458   bool isImm() const override {
459     return Kind == Immediate || Kind == Expression;
460   }
461   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
462   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
463   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
464   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
465   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
466   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
467   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
468   bool isU6ImmX2() const { return Kind == Immediate &&
469                                   isUInt<6>(getImm()) &&
470                                   (getImm() & 1) == 0; }
471   bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); }
472   bool isU7ImmX4() const { return Kind == Immediate &&
473                                   isUInt<7>(getImm()) &&
474                                   (getImm() & 3) == 0; }
475   bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); }
476   bool isU8ImmX8() const { return Kind == Immediate &&
477                                   isUInt<8>(getImm()) &&
478                                   (getImm() & 7) == 0; }
479 
480   bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); }
481   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
482   bool isU16Imm() const {
483     switch (Kind) {
484       case Expression:
485         return true;
486       case Immediate:
487       case ContextImmediate:
488         return isUInt<16>(getImmU16Context());
489       default:
490         return false;
491     }
492   }
493   bool isS16Imm() const {
494     switch (Kind) {
495       case Expression:
496         return true;
497       case Immediate:
498       case ContextImmediate:
499         return isInt<16>(getImmS16Context());
500       default:
501         return false;
502     }
503   }
504   bool isS16ImmX4() const { return Kind == Expression ||
505                                    (Kind == Immediate && isInt<16>(getImm()) &&
506                                     (getImm() & 3) == 0); }
507   bool isS16ImmX16() const { return Kind == Expression ||
508                                     (Kind == Immediate && isInt<16>(getImm()) &&
509                                      (getImm() & 15) == 0); }
510   bool isS17Imm() const {
511     switch (Kind) {
512       case Expression:
513         return true;
514       case Immediate:
515       case ContextImmediate:
516         return isInt<17>(getImmS16Context());
517       default:
518         return false;
519     }
520   }
521   bool isTLSReg() const { return Kind == TLSRegister; }
522   bool isDirectBr() const {
523     if (Kind == Expression)
524       return true;
525     if (Kind != Immediate)
526       return false;
527     // Operand must be 64-bit aligned, signed 27-bit immediate.
528     if ((getImm() & 3) != 0)
529       return false;
530     if (isInt<26>(getImm()))
531       return true;
532     if (!IsPPC64) {
533       // In 32-bit mode, large 32-bit quantities wrap around.
534       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
535         return true;
536     }
537     return false;
538   }
539   bool isCondBr() const { return Kind == Expression ||
540                                  (Kind == Immediate && isInt<16>(getImm()) &&
541                                   (getImm() & 3) == 0); }
542   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
543   bool isVSRegNumber() const {
544     return Kind == Immediate && isUInt<6>(getImm());
545   }
546   bool isCCRegNumber() const { return (Kind == Expression
547                                        && isUInt<3>(getExprCRVal())) ||
548                                       (Kind == Immediate
549                                        && isUInt<3>(getImm())); }
550   bool isCRBitNumber() const { return (Kind == Expression
551                                        && isUInt<5>(getExprCRVal())) ||
552                                       (Kind == Immediate
553                                        && isUInt<5>(getImm())); }
554   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
555                                     isPowerOf2_32(getImm()); }
556   bool isATBitsAsHint() const { return false; }
557   bool isMem() const override { return false; }
558   bool isReg() const override { return false; }
559 
560   void addRegOperands(MCInst &Inst, unsigned N) const {
561     llvm_unreachable("addRegOperands");
562   }
563 
564   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
565     assert(N == 1 && "Invalid number of operands!");
566     Inst.addOperand(MCOperand::createReg(RRegs[getReg()]));
567   }
568 
569   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
570     assert(N == 1 && "Invalid number of operands!");
571     Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()]));
572   }
573 
574   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
575     assert(N == 1 && "Invalid number of operands!");
576     Inst.addOperand(MCOperand::createReg(XRegs[getReg()]));
577   }
578 
579   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
580     assert(N == 1 && "Invalid number of operands!");
581     Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()]));
582   }
583 
584   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
585     if (isPPC64())
586       addRegG8RCOperands(Inst, N);
587     else
588       addRegGPRCOperands(Inst, N);
589   }
590 
591   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
592     if (isPPC64())
593       addRegG8RCNoX0Operands(Inst, N);
594     else
595       addRegGPRCNoR0Operands(Inst, N);
596   }
597 
598   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
599     assert(N == 1 && "Invalid number of operands!");
600     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
601   }
602 
603   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
604     assert(N == 1 && "Invalid number of operands!");
605     Inst.addOperand(MCOperand::createReg(FRegs[getReg()]));
606   }
607 
608   void addRegVFRCOperands(MCInst &Inst, unsigned N) const {
609     assert(N == 1 && "Invalid number of operands!");
610     Inst.addOperand(MCOperand::createReg(VFRegs[getReg()]));
611   }
612 
613   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
614     assert(N == 1 && "Invalid number of operands!");
615     Inst.addOperand(MCOperand::createReg(VRegs[getReg()]));
616   }
617 
618   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
619     assert(N == 1 && "Invalid number of operands!");
620     Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()]));
621   }
622 
623   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
624     assert(N == 1 && "Invalid number of operands!");
625     Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()]));
626   }
627 
628   void addRegVSSRCOperands(MCInst &Inst, unsigned N) const {
629     assert(N == 1 && "Invalid number of operands!");
630     Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()]));
631   }
632 
633   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
634     assert(N == 1 && "Invalid number of operands!");
635     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
636   }
637 
638   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
639     assert(N == 1 && "Invalid number of operands!");
640     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
641   }
642 
643   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
644     assert(N == 1 && "Invalid number of operands!");
645     Inst.addOperand(MCOperand::createReg(QFRegs[getReg()]));
646   }
647 
648   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
649     assert(N == 1 && "Invalid number of operands!");
650     Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()]));
651   }
652 
653   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
654     assert(N == 1 && "Invalid number of operands!");
655     Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()]));
656   }
657 
658   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
659     assert(N == 1 && "Invalid number of operands!");
660     Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()]));
661   }
662 
663   void addImmOperands(MCInst &Inst, unsigned N) const {
664     assert(N == 1 && "Invalid number of operands!");
665     if (Kind == Immediate)
666       Inst.addOperand(MCOperand::createImm(getImm()));
667     else
668       Inst.addOperand(MCOperand::createExpr(getExpr()));
669   }
670 
671   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
672     assert(N == 1 && "Invalid number of operands!");
673     switch (Kind) {
674       case Immediate:
675         Inst.addOperand(MCOperand::createImm(getImm()));
676         break;
677       case ContextImmediate:
678         Inst.addOperand(MCOperand::createImm(getImmS16Context()));
679         break;
680       default:
681         Inst.addOperand(MCOperand::createExpr(getExpr()));
682         break;
683     }
684   }
685 
686   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
687     assert(N == 1 && "Invalid number of operands!");
688     switch (Kind) {
689       case Immediate:
690         Inst.addOperand(MCOperand::createImm(getImm()));
691         break;
692       case ContextImmediate:
693         Inst.addOperand(MCOperand::createImm(getImmU16Context()));
694         break;
695       default:
696         Inst.addOperand(MCOperand::createExpr(getExpr()));
697         break;
698     }
699   }
700 
701   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
702     assert(N == 1 && "Invalid number of operands!");
703     if (Kind == Immediate)
704       Inst.addOperand(MCOperand::createImm(getImm() / 4));
705     else
706       Inst.addOperand(MCOperand::createExpr(getExpr()));
707   }
708 
709   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
710     assert(N == 1 && "Invalid number of operands!");
711     Inst.addOperand(MCOperand::createExpr(getTLSReg()));
712   }
713 
714   StringRef getToken() const {
715     assert(Kind == Token && "Invalid access!");
716     return StringRef(Tok.Data, Tok.Length);
717   }
718 
719   void print(raw_ostream &OS) const override;
720 
721   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
722                                                  bool IsPPC64) {
723     auto Op = make_unique<PPCOperand>(Token);
724     Op->Tok.Data = Str.data();
725     Op->Tok.Length = Str.size();
726     Op->StartLoc = S;
727     Op->EndLoc = S;
728     Op->IsPPC64 = IsPPC64;
729     return Op;
730   }
731 
732   static std::unique_ptr<PPCOperand>
733   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
734     // Allocate extra memory for the string and copy it.
735     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
736     // deleter which will destroy them by simply using "delete", not correctly
737     // calling operator delete on this extra memory after calling the dtor
738     // explicitly.
739     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
740     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
741     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
742     Op->Tok.Length = Str.size();
743     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
744     Op->StartLoc = S;
745     Op->EndLoc = S;
746     Op->IsPPC64 = IsPPC64;
747     return Op;
748   }
749 
750   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
751                                                bool IsPPC64) {
752     auto Op = make_unique<PPCOperand>(Immediate);
753     Op->Imm.Val = Val;
754     Op->StartLoc = S;
755     Op->EndLoc = E;
756     Op->IsPPC64 = IsPPC64;
757     return Op;
758   }
759 
760   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
761                                                 SMLoc E, bool IsPPC64) {
762     auto Op = make_unique<PPCOperand>(Expression);
763     Op->Expr.Val = Val;
764     Op->Expr.CRVal = EvaluateCRExpr(Val);
765     Op->StartLoc = S;
766     Op->EndLoc = E;
767     Op->IsPPC64 = IsPPC64;
768     return Op;
769   }
770 
771   static std::unique_ptr<PPCOperand>
772   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
773     auto Op = make_unique<PPCOperand>(TLSRegister);
774     Op->TLSReg.Sym = Sym;
775     Op->StartLoc = S;
776     Op->EndLoc = E;
777     Op->IsPPC64 = IsPPC64;
778     return Op;
779   }
780 
781   static std::unique_ptr<PPCOperand>
782   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
783     auto Op = make_unique<PPCOperand>(ContextImmediate);
784     Op->Imm.Val = Val;
785     Op->StartLoc = S;
786     Op->EndLoc = E;
787     Op->IsPPC64 = IsPPC64;
788     return Op;
789   }
790 
791   static std::unique_ptr<PPCOperand>
792   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
793     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
794       return CreateImm(CE->getValue(), S, E, IsPPC64);
795 
796     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
797       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
798         return CreateTLSReg(SRE, S, E, IsPPC64);
799 
800     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
801       int64_t Res;
802       if (TE->evaluateAsConstant(Res))
803         return CreateContextImm(Res, S, E, IsPPC64);
804     }
805 
806     return CreateExpr(Val, S, E, IsPPC64);
807   }
808 };
809 
810 } // end anonymous namespace.
811 
812 void PPCOperand::print(raw_ostream &OS) const {
813   switch (Kind) {
814   case Token:
815     OS << "'" << getToken() << "'";
816     break;
817   case Immediate:
818   case ContextImmediate:
819     OS << getImm();
820     break;
821   case Expression:
822     OS << *getExpr();
823     break;
824   case TLSRegister:
825     OS << *getTLSReg();
826     break;
827   }
828 }
829 
830 static void
831 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
832   if (Op.isImm()) {
833     Inst.addOperand(MCOperand::createImm(-Op.getImm()));
834     return;
835   }
836   const MCExpr *Expr = Op.getExpr();
837   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
838     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
839       Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr()));
840       return;
841     }
842   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
843     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
844       const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(),
845                                                  BinExpr->getLHS(), Ctx);
846       Inst.addOperand(MCOperand::createExpr(NE));
847       return;
848     }
849   }
850   Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx)));
851 }
852 
853 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
854                                       const OperandVector &Operands) {
855   int Opcode = Inst.getOpcode();
856   switch (Opcode) {
857   case PPC::DCBTx:
858   case PPC::DCBTT:
859   case PPC::DCBTSTx:
860   case PPC::DCBTSTT: {
861     MCInst TmpInst;
862     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
863                       PPC::DCBT : PPC::DCBTST);
864     TmpInst.addOperand(MCOperand::createImm(
865       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
866     TmpInst.addOperand(Inst.getOperand(0));
867     TmpInst.addOperand(Inst.getOperand(1));
868     Inst = TmpInst;
869     break;
870   }
871   case PPC::DCBTCT:
872   case PPC::DCBTDS: {
873     MCInst TmpInst;
874     TmpInst.setOpcode(PPC::DCBT);
875     TmpInst.addOperand(Inst.getOperand(2));
876     TmpInst.addOperand(Inst.getOperand(0));
877     TmpInst.addOperand(Inst.getOperand(1));
878     Inst = TmpInst;
879     break;
880   }
881   case PPC::DCBTSTCT:
882   case PPC::DCBTSTDS: {
883     MCInst TmpInst;
884     TmpInst.setOpcode(PPC::DCBTST);
885     TmpInst.addOperand(Inst.getOperand(2));
886     TmpInst.addOperand(Inst.getOperand(0));
887     TmpInst.addOperand(Inst.getOperand(1));
888     Inst = TmpInst;
889     break;
890   }
891   case PPC::DCBFx:
892   case PPC::DCBFL:
893   case PPC::DCBFLP: {
894     int L = 0;
895     if (Opcode == PPC::DCBFL)
896       L = 1;
897     else if (Opcode == PPC::DCBFLP)
898       L = 3;
899 
900     MCInst TmpInst;
901     TmpInst.setOpcode(PPC::DCBF);
902     TmpInst.addOperand(MCOperand::createImm(L));
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(Inst.getOperand(1));
905     Inst = TmpInst;
906     break;
907   }
908   case PPC::LAx: {
909     MCInst TmpInst;
910     TmpInst.setOpcode(PPC::LA);
911     TmpInst.addOperand(Inst.getOperand(0));
912     TmpInst.addOperand(Inst.getOperand(2));
913     TmpInst.addOperand(Inst.getOperand(1));
914     Inst = TmpInst;
915     break;
916   }
917   case PPC::SUBI: {
918     MCInst TmpInst;
919     TmpInst.setOpcode(PPC::ADDI);
920     TmpInst.addOperand(Inst.getOperand(0));
921     TmpInst.addOperand(Inst.getOperand(1));
922     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
923     Inst = TmpInst;
924     break;
925   }
926   case PPC::SUBIS: {
927     MCInst TmpInst;
928     TmpInst.setOpcode(PPC::ADDIS);
929     TmpInst.addOperand(Inst.getOperand(0));
930     TmpInst.addOperand(Inst.getOperand(1));
931     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
932     Inst = TmpInst;
933     break;
934   }
935   case PPC::SUBIC: {
936     MCInst TmpInst;
937     TmpInst.setOpcode(PPC::ADDIC);
938     TmpInst.addOperand(Inst.getOperand(0));
939     TmpInst.addOperand(Inst.getOperand(1));
940     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
941     Inst = TmpInst;
942     break;
943   }
944   case PPC::SUBICo: {
945     MCInst TmpInst;
946     TmpInst.setOpcode(PPC::ADDICo);
947     TmpInst.addOperand(Inst.getOperand(0));
948     TmpInst.addOperand(Inst.getOperand(1));
949     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
950     Inst = TmpInst;
951     break;
952   }
953   case PPC::EXTLWI:
954   case PPC::EXTLWIo: {
955     MCInst TmpInst;
956     int64_t N = Inst.getOperand(2).getImm();
957     int64_t B = Inst.getOperand(3).getImm();
958     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
959     TmpInst.addOperand(Inst.getOperand(0));
960     TmpInst.addOperand(Inst.getOperand(1));
961     TmpInst.addOperand(MCOperand::createImm(B));
962     TmpInst.addOperand(MCOperand::createImm(0));
963     TmpInst.addOperand(MCOperand::createImm(N - 1));
964     Inst = TmpInst;
965     break;
966   }
967   case PPC::EXTRWI:
968   case PPC::EXTRWIo: {
969     MCInst TmpInst;
970     int64_t N = Inst.getOperand(2).getImm();
971     int64_t B = Inst.getOperand(3).getImm();
972     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
973     TmpInst.addOperand(Inst.getOperand(0));
974     TmpInst.addOperand(Inst.getOperand(1));
975     TmpInst.addOperand(MCOperand::createImm(B + N));
976     TmpInst.addOperand(MCOperand::createImm(32 - N));
977     TmpInst.addOperand(MCOperand::createImm(31));
978     Inst = TmpInst;
979     break;
980   }
981   case PPC::INSLWI:
982   case PPC::INSLWIo: {
983     MCInst TmpInst;
984     int64_t N = Inst.getOperand(2).getImm();
985     int64_t B = Inst.getOperand(3).getImm();
986     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
987     TmpInst.addOperand(Inst.getOperand(0));
988     TmpInst.addOperand(Inst.getOperand(0));
989     TmpInst.addOperand(Inst.getOperand(1));
990     TmpInst.addOperand(MCOperand::createImm(32 - B));
991     TmpInst.addOperand(MCOperand::createImm(B));
992     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
993     Inst = TmpInst;
994     break;
995   }
996   case PPC::INSRWI:
997   case PPC::INSRWIo: {
998     MCInst TmpInst;
999     int64_t N = Inst.getOperand(2).getImm();
1000     int64_t B = Inst.getOperand(3).getImm();
1001     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
1002     TmpInst.addOperand(Inst.getOperand(0));
1003     TmpInst.addOperand(Inst.getOperand(0));
1004     TmpInst.addOperand(Inst.getOperand(1));
1005     TmpInst.addOperand(MCOperand::createImm(32 - (B + N)));
1006     TmpInst.addOperand(MCOperand::createImm(B));
1007     TmpInst.addOperand(MCOperand::createImm((B + N) - 1));
1008     Inst = TmpInst;
1009     break;
1010   }
1011   case PPC::ROTRWI:
1012   case PPC::ROTRWIo: {
1013     MCInst TmpInst;
1014     int64_t N = Inst.getOperand(2).getImm();
1015     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
1016     TmpInst.addOperand(Inst.getOperand(0));
1017     TmpInst.addOperand(Inst.getOperand(1));
1018     TmpInst.addOperand(MCOperand::createImm(32 - N));
1019     TmpInst.addOperand(MCOperand::createImm(0));
1020     TmpInst.addOperand(MCOperand::createImm(31));
1021     Inst = TmpInst;
1022     break;
1023   }
1024   case PPC::SLWI:
1025   case PPC::SLWIo: {
1026     MCInst TmpInst;
1027     int64_t N = Inst.getOperand(2).getImm();
1028     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
1029     TmpInst.addOperand(Inst.getOperand(0));
1030     TmpInst.addOperand(Inst.getOperand(1));
1031     TmpInst.addOperand(MCOperand::createImm(N));
1032     TmpInst.addOperand(MCOperand::createImm(0));
1033     TmpInst.addOperand(MCOperand::createImm(31 - N));
1034     Inst = TmpInst;
1035     break;
1036   }
1037   case PPC::SRWI:
1038   case PPC::SRWIo: {
1039     MCInst TmpInst;
1040     int64_t N = Inst.getOperand(2).getImm();
1041     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
1042     TmpInst.addOperand(Inst.getOperand(0));
1043     TmpInst.addOperand(Inst.getOperand(1));
1044     TmpInst.addOperand(MCOperand::createImm(32 - N));
1045     TmpInst.addOperand(MCOperand::createImm(N));
1046     TmpInst.addOperand(MCOperand::createImm(31));
1047     Inst = TmpInst;
1048     break;
1049   }
1050   case PPC::CLRRWI:
1051   case PPC::CLRRWIo: {
1052     MCInst TmpInst;
1053     int64_t N = Inst.getOperand(2).getImm();
1054     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
1055     TmpInst.addOperand(Inst.getOperand(0));
1056     TmpInst.addOperand(Inst.getOperand(1));
1057     TmpInst.addOperand(MCOperand::createImm(0));
1058     TmpInst.addOperand(MCOperand::createImm(0));
1059     TmpInst.addOperand(MCOperand::createImm(31 - N));
1060     Inst = TmpInst;
1061     break;
1062   }
1063   case PPC::CLRLSLWI:
1064   case PPC::CLRLSLWIo: {
1065     MCInst TmpInst;
1066     int64_t B = Inst.getOperand(2).getImm();
1067     int64_t N = Inst.getOperand(3).getImm();
1068     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
1069     TmpInst.addOperand(Inst.getOperand(0));
1070     TmpInst.addOperand(Inst.getOperand(1));
1071     TmpInst.addOperand(MCOperand::createImm(N));
1072     TmpInst.addOperand(MCOperand::createImm(B - N));
1073     TmpInst.addOperand(MCOperand::createImm(31 - N));
1074     Inst = TmpInst;
1075     break;
1076   }
1077   case PPC::EXTLDI:
1078   case PPC::EXTLDIo: {
1079     MCInst TmpInst;
1080     int64_t N = Inst.getOperand(2).getImm();
1081     int64_t B = Inst.getOperand(3).getImm();
1082     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1083     TmpInst.addOperand(Inst.getOperand(0));
1084     TmpInst.addOperand(Inst.getOperand(1));
1085     TmpInst.addOperand(MCOperand::createImm(B));
1086     TmpInst.addOperand(MCOperand::createImm(N - 1));
1087     Inst = TmpInst;
1088     break;
1089   }
1090   case PPC::EXTRDI:
1091   case PPC::EXTRDIo: {
1092     MCInst TmpInst;
1093     int64_t N = Inst.getOperand(2).getImm();
1094     int64_t B = Inst.getOperand(3).getImm();
1095     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1096     TmpInst.addOperand(Inst.getOperand(0));
1097     TmpInst.addOperand(Inst.getOperand(1));
1098     TmpInst.addOperand(MCOperand::createImm(B + N));
1099     TmpInst.addOperand(MCOperand::createImm(64 - N));
1100     Inst = TmpInst;
1101     break;
1102   }
1103   case PPC::INSRDI:
1104   case PPC::INSRDIo: {
1105     MCInst TmpInst;
1106     int64_t N = Inst.getOperand(2).getImm();
1107     int64_t B = Inst.getOperand(3).getImm();
1108     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1109     TmpInst.addOperand(Inst.getOperand(0));
1110     TmpInst.addOperand(Inst.getOperand(0));
1111     TmpInst.addOperand(Inst.getOperand(1));
1112     TmpInst.addOperand(MCOperand::createImm(64 - (B + N)));
1113     TmpInst.addOperand(MCOperand::createImm(B));
1114     Inst = TmpInst;
1115     break;
1116   }
1117   case PPC::ROTRDI:
1118   case PPC::ROTRDIo: {
1119     MCInst TmpInst;
1120     int64_t N = Inst.getOperand(2).getImm();
1121     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1122     TmpInst.addOperand(Inst.getOperand(0));
1123     TmpInst.addOperand(Inst.getOperand(1));
1124     TmpInst.addOperand(MCOperand::createImm(64 - N));
1125     TmpInst.addOperand(MCOperand::createImm(0));
1126     Inst = TmpInst;
1127     break;
1128   }
1129   case PPC::SLDI:
1130   case PPC::SLDIo: {
1131     MCInst TmpInst;
1132     int64_t N = Inst.getOperand(2).getImm();
1133     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1134     TmpInst.addOperand(Inst.getOperand(0));
1135     TmpInst.addOperand(Inst.getOperand(1));
1136     TmpInst.addOperand(MCOperand::createImm(N));
1137     TmpInst.addOperand(MCOperand::createImm(63 - N));
1138     Inst = TmpInst;
1139     break;
1140   }
1141   case PPC::SUBPCIS: {
1142     MCInst TmpInst;
1143     int64_t N = Inst.getOperand(1).getImm();
1144     TmpInst.setOpcode(PPC::ADDPCIS);
1145     TmpInst.addOperand(Inst.getOperand(0));
1146     TmpInst.addOperand(MCOperand::createImm(-N));
1147     Inst = TmpInst;
1148     break;
1149   }
1150   case PPC::SRDI:
1151   case PPC::SRDIo: {
1152     MCInst TmpInst;
1153     int64_t N = Inst.getOperand(2).getImm();
1154     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1155     TmpInst.addOperand(Inst.getOperand(0));
1156     TmpInst.addOperand(Inst.getOperand(1));
1157     TmpInst.addOperand(MCOperand::createImm(64 - N));
1158     TmpInst.addOperand(MCOperand::createImm(N));
1159     Inst = TmpInst;
1160     break;
1161   }
1162   case PPC::CLRRDI:
1163   case PPC::CLRRDIo: {
1164     MCInst TmpInst;
1165     int64_t N = Inst.getOperand(2).getImm();
1166     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1167     TmpInst.addOperand(Inst.getOperand(0));
1168     TmpInst.addOperand(Inst.getOperand(1));
1169     TmpInst.addOperand(MCOperand::createImm(0));
1170     TmpInst.addOperand(MCOperand::createImm(63 - N));
1171     Inst = TmpInst;
1172     break;
1173   }
1174   case PPC::CLRLSLDI:
1175   case PPC::CLRLSLDIo: {
1176     MCInst TmpInst;
1177     int64_t B = Inst.getOperand(2).getImm();
1178     int64_t N = Inst.getOperand(3).getImm();
1179     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1180     TmpInst.addOperand(Inst.getOperand(0));
1181     TmpInst.addOperand(Inst.getOperand(1));
1182     TmpInst.addOperand(MCOperand::createImm(N));
1183     TmpInst.addOperand(MCOperand::createImm(B - N));
1184     Inst = TmpInst;
1185     break;
1186   }
1187   case PPC::RLWINMbm:
1188   case PPC::RLWINMobm: {
1189     unsigned MB, ME;
1190     int64_t BM = Inst.getOperand(3).getImm();
1191     if (!isRunOfOnes(BM, MB, ME))
1192       break;
1193 
1194     MCInst TmpInst;
1195     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1196     TmpInst.addOperand(Inst.getOperand(0));
1197     TmpInst.addOperand(Inst.getOperand(1));
1198     TmpInst.addOperand(Inst.getOperand(2));
1199     TmpInst.addOperand(MCOperand::createImm(MB));
1200     TmpInst.addOperand(MCOperand::createImm(ME));
1201     Inst = TmpInst;
1202     break;
1203   }
1204   case PPC::RLWIMIbm:
1205   case PPC::RLWIMIobm: {
1206     unsigned MB, ME;
1207     int64_t BM = Inst.getOperand(3).getImm();
1208     if (!isRunOfOnes(BM, MB, ME))
1209       break;
1210 
1211     MCInst TmpInst;
1212     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1213     TmpInst.addOperand(Inst.getOperand(0));
1214     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1215     TmpInst.addOperand(Inst.getOperand(1));
1216     TmpInst.addOperand(Inst.getOperand(2));
1217     TmpInst.addOperand(MCOperand::createImm(MB));
1218     TmpInst.addOperand(MCOperand::createImm(ME));
1219     Inst = TmpInst;
1220     break;
1221   }
1222   case PPC::RLWNMbm:
1223   case PPC::RLWNMobm: {
1224     unsigned MB, ME;
1225     int64_t BM = Inst.getOperand(3).getImm();
1226     if (!isRunOfOnes(BM, MB, ME))
1227       break;
1228 
1229     MCInst TmpInst;
1230     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1231     TmpInst.addOperand(Inst.getOperand(0));
1232     TmpInst.addOperand(Inst.getOperand(1));
1233     TmpInst.addOperand(Inst.getOperand(2));
1234     TmpInst.addOperand(MCOperand::createImm(MB));
1235     TmpInst.addOperand(MCOperand::createImm(ME));
1236     Inst = TmpInst;
1237     break;
1238   }
1239   case PPC::MFTB: {
1240     if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) {
1241       assert(Inst.getNumOperands() == 2 && "Expecting two operands");
1242       Inst.setOpcode(PPC::MFSPR);
1243     }
1244     break;
1245   }
1246   case PPC::CP_COPYx:
1247   case PPC::CP_COPY_FIRST: {
1248     MCInst TmpInst;
1249     TmpInst.setOpcode(PPC::CP_COPY);
1250     TmpInst.addOperand(Inst.getOperand(0));
1251     TmpInst.addOperand(Inst.getOperand(1));
1252     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1));
1253 
1254     Inst = TmpInst;
1255     break;
1256   }
1257   case PPC::CP_PASTEx :
1258   case PPC::CP_PASTE_LAST: {
1259     MCInst TmpInst;
1260     TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ?
1261                       PPC::CP_PASTE : PPC::CP_PASTEo);
1262     TmpInst.addOperand(Inst.getOperand(0));
1263     TmpInst.addOperand(Inst.getOperand(1));
1264     TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1));
1265 
1266     Inst = TmpInst;
1267     break;
1268   }
1269   }
1270 }
1271 
1272 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1273                                            OperandVector &Operands,
1274                                            MCStreamer &Out, uint64_t &ErrorInfo,
1275                                            bool MatchingInlineAsm) {
1276   MCInst Inst;
1277 
1278   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1279   case Match_Success:
1280     // Post-process instructions (typically extended mnemonics)
1281     ProcessInstruction(Inst, Operands);
1282     Inst.setLoc(IDLoc);
1283     Out.EmitInstruction(Inst, getSTI());
1284     return false;
1285   case Match_MissingFeature:
1286     return Error(IDLoc, "instruction use requires an option to be enabled");
1287   case Match_MnemonicFail:
1288     return Error(IDLoc, "unrecognized instruction mnemonic");
1289   case Match_InvalidOperand: {
1290     SMLoc ErrorLoc = IDLoc;
1291     if (ErrorInfo != ~0ULL) {
1292       if (ErrorInfo >= Operands.size())
1293         return Error(IDLoc, "too few operands for instruction");
1294 
1295       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1296       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1297     }
1298 
1299     return Error(ErrorLoc, "invalid operand for instruction");
1300   }
1301   }
1302 
1303   llvm_unreachable("Implement any new match types added!");
1304 }
1305 
1306 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) {
1307   if (getParser().getTok().is(AsmToken::Identifier)) {
1308     StringRef Name = getParser().getTok().getString();
1309     if (Name.equals_lower("lr")) {
1310       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1311       IntVal = 8;
1312     } else if (Name.equals_lower("ctr")) {
1313       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1314       IntVal = 9;
1315     } else if (Name.equals_lower("vrsave")) {
1316       RegNo = PPC::VRSAVE;
1317       IntVal = 256;
1318     } else if (Name.startswith_lower("r") &&
1319                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1320       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1321     } else if (Name.startswith_lower("f") &&
1322                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1323       RegNo = FRegs[IntVal];
1324     } else if (Name.startswith_lower("vs") &&
1325                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1326       RegNo = VSRegs[IntVal];
1327     } else if (Name.startswith_lower("v") &&
1328                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1329       RegNo = VRegs[IntVal];
1330     } else if (Name.startswith_lower("q") &&
1331                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1332       RegNo = QFRegs[IntVal];
1333     } else if (Name.startswith_lower("cr") &&
1334                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1335       RegNo = CRRegs[IntVal];
1336     } else
1337       return true;
1338     getParser().Lex();
1339     return false;
1340   }
1341   return true;
1342 }
1343 
1344 bool PPCAsmParser::
1345 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1346   const AsmToken &Tok = getParser().getTok();
1347   StartLoc = Tok.getLoc();
1348   EndLoc = Tok.getEndLoc();
1349   RegNo = 0;
1350   int64_t IntVal;
1351   if (MatchRegisterName(RegNo, IntVal))
1352     return TokError("invalid register name");
1353   return false;
1354 }
1355 
1356 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1357 /// the expression and check for VK_PPC_LO/HI/HA
1358 /// symbol variants.  If all symbols with modifier use the same
1359 /// variant, return the corresponding PPCMCExpr::VariantKind,
1360 /// and a modified expression using the default symbol variant.
1361 /// Otherwise, return NULL.
1362 const MCExpr *PPCAsmParser::
1363 ExtractModifierFromExpr(const MCExpr *E,
1364                         PPCMCExpr::VariantKind &Variant) {
1365   MCContext &Context = getParser().getContext();
1366   Variant = PPCMCExpr::VK_PPC_None;
1367 
1368   switch (E->getKind()) {
1369   case MCExpr::Target:
1370   case MCExpr::Constant:
1371     return nullptr;
1372 
1373   case MCExpr::SymbolRef: {
1374     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1375 
1376     switch (SRE->getKind()) {
1377     case MCSymbolRefExpr::VK_PPC_LO:
1378       Variant = PPCMCExpr::VK_PPC_LO;
1379       break;
1380     case MCSymbolRefExpr::VK_PPC_HI:
1381       Variant = PPCMCExpr::VK_PPC_HI;
1382       break;
1383     case MCSymbolRefExpr::VK_PPC_HA:
1384       Variant = PPCMCExpr::VK_PPC_HA;
1385       break;
1386     case MCSymbolRefExpr::VK_PPC_HIGHER:
1387       Variant = PPCMCExpr::VK_PPC_HIGHER;
1388       break;
1389     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1390       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1391       break;
1392     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1393       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1394       break;
1395     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1396       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1397       break;
1398     default:
1399       return nullptr;
1400     }
1401 
1402     return MCSymbolRefExpr::create(&SRE->getSymbol(), Context);
1403   }
1404 
1405   case MCExpr::Unary: {
1406     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1407     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1408     if (!Sub)
1409       return nullptr;
1410     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1411   }
1412 
1413   case MCExpr::Binary: {
1414     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1415     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1416     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1417     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1418 
1419     if (!LHS && !RHS)
1420       return nullptr;
1421 
1422     if (!LHS) LHS = BE->getLHS();
1423     if (!RHS) RHS = BE->getRHS();
1424 
1425     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1426       Variant = RHSVariant;
1427     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1428       Variant = LHSVariant;
1429     else if (LHSVariant == RHSVariant)
1430       Variant = LHSVariant;
1431     else
1432       return nullptr;
1433 
1434     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1435   }
1436   }
1437 
1438   llvm_unreachable("Invalid expression kind!");
1439 }
1440 
1441 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1442 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1443 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1444 /// FIXME: This is a hack.
1445 const MCExpr *PPCAsmParser::
1446 FixupVariantKind(const MCExpr *E) {
1447   MCContext &Context = getParser().getContext();
1448 
1449   switch (E->getKind()) {
1450   case MCExpr::Target:
1451   case MCExpr::Constant:
1452     return E;
1453 
1454   case MCExpr::SymbolRef: {
1455     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1456     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1457 
1458     switch (SRE->getKind()) {
1459     case MCSymbolRefExpr::VK_TLSGD:
1460       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1461       break;
1462     case MCSymbolRefExpr::VK_TLSLD:
1463       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1464       break;
1465     default:
1466       return E;
1467     }
1468     return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context);
1469   }
1470 
1471   case MCExpr::Unary: {
1472     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1473     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1474     if (Sub == UE->getSubExpr())
1475       return E;
1476     return MCUnaryExpr::create(UE->getOpcode(), Sub, Context);
1477   }
1478 
1479   case MCExpr::Binary: {
1480     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1481     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1482     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1483     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1484       return E;
1485     return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context);
1486   }
1487   }
1488 
1489   llvm_unreachable("Invalid expression kind!");
1490 }
1491 
1492 /// ParseExpression.  This differs from the default "parseExpression" in that
1493 /// it handles modifiers.
1494 bool PPCAsmParser::
1495 ParseExpression(const MCExpr *&EVal) {
1496 
1497   if (isDarwin())
1498     return ParseDarwinExpression(EVal);
1499 
1500   // (ELF Platforms)
1501   // Handle \code @l/@ha \endcode
1502   if (getParser().parseExpression(EVal))
1503     return true;
1504 
1505   EVal = FixupVariantKind(EVal);
1506 
1507   PPCMCExpr::VariantKind Variant;
1508   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1509   if (E)
1510     EVal = PPCMCExpr::create(Variant, E, false, getParser().getContext());
1511 
1512   return false;
1513 }
1514 
1515 /// ParseDarwinExpression.  (MachO Platforms)
1516 /// This differs from the default "parseExpression" in that it handles detection
1517 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1518 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1519 /// syntax form so it is done here.  TODO: Determine if there is merit in
1520 /// arranging for this to be done at a higher level.
1521 bool PPCAsmParser::
1522 ParseDarwinExpression(const MCExpr *&EVal) {
1523   MCAsmParser &Parser = getParser();
1524   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1525   switch (getLexer().getKind()) {
1526   default:
1527     break;
1528   case AsmToken::Identifier:
1529     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1530     // something starting with any other char should be part of the
1531     // asm syntax.  If handwritten asm includes an identifier like lo16,
1532     // then all bets are off - but no-one would do that, right?
1533     StringRef poss = Parser.getTok().getString();
1534     if (poss.equals_lower("lo16")) {
1535       Variant = PPCMCExpr::VK_PPC_LO;
1536     } else if (poss.equals_lower("hi16")) {
1537       Variant = PPCMCExpr::VK_PPC_HI;
1538     } else if (poss.equals_lower("ha16")) {
1539       Variant = PPCMCExpr::VK_PPC_HA;
1540     }
1541     if (Variant != PPCMCExpr::VK_PPC_None) {
1542       Parser.Lex(); // Eat the xx16
1543       if (getLexer().isNot(AsmToken::LParen))
1544         return Error(Parser.getTok().getLoc(), "expected '('");
1545       Parser.Lex(); // Eat the '('
1546     }
1547     break;
1548   }
1549 
1550   if (getParser().parseExpression(EVal))
1551     return true;
1552 
1553   if (Variant != PPCMCExpr::VK_PPC_None) {
1554     if (getLexer().isNot(AsmToken::RParen))
1555       return Error(Parser.getTok().getLoc(), "expected ')'");
1556     Parser.Lex(); // Eat the ')'
1557     EVal = PPCMCExpr::create(Variant, EVal, false, getParser().getContext());
1558   }
1559   return false;
1560 }
1561 
1562 /// ParseOperand
1563 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1564 /// rNN for MachO.
1565 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1566   MCAsmParser &Parser = getParser();
1567   SMLoc S = Parser.getTok().getLoc();
1568   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1569   const MCExpr *EVal;
1570 
1571   // Attempt to parse the next token as an immediate
1572   switch (getLexer().getKind()) {
1573   // Special handling for register names.  These are interpreted
1574   // as immediates corresponding to the register number.
1575   case AsmToken::Percent:
1576     Parser.Lex(); // Eat the '%'.
1577     unsigned RegNo;
1578     int64_t IntVal;
1579     if (MatchRegisterName(RegNo, IntVal))
1580       return Error(S, "invalid register name");
1581 
1582     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1583     return false;
1584 
1585   case AsmToken::Identifier:
1586   case AsmToken::LParen:
1587   case AsmToken::Plus:
1588   case AsmToken::Minus:
1589   case AsmToken::Integer:
1590   case AsmToken::Dot:
1591   case AsmToken::Dollar:
1592   case AsmToken::Exclaim:
1593   case AsmToken::Tilde:
1594     // Note that non-register-name identifiers from the compiler will begin
1595     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1596     // identifiers like r31foo - so we fall through in the event that parsing
1597     // a register name fails.
1598     if (isDarwin()) {
1599       unsigned RegNo;
1600       int64_t IntVal;
1601       if (!MatchRegisterName(RegNo, IntVal)) {
1602         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1603         return false;
1604       }
1605     }
1606     // All other expressions
1607 
1608     if (!ParseExpression(EVal))
1609       break;
1610     // Fall-through
1611     LLVM_FALLTHROUGH;
1612   default:
1613     return Error(S, "unknown operand");
1614   }
1615 
1616   // Push the parsed operand into the list of operands
1617   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1618 
1619   // Check whether this is a TLS call expression
1620   bool TLSCall = false;
1621   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1622     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1623 
1624   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1625     const MCExpr *TLSSym;
1626 
1627     Parser.Lex(); // Eat the '('.
1628     S = Parser.getTok().getLoc();
1629     if (ParseExpression(TLSSym))
1630       return Error(S, "invalid TLS call expression");
1631     if (getLexer().isNot(AsmToken::RParen))
1632       return Error(Parser.getTok().getLoc(), "missing ')'");
1633     E = Parser.getTok().getLoc();
1634     Parser.Lex(); // Eat the ')'.
1635 
1636     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1637   }
1638 
1639   // Otherwise, check for D-form memory operands
1640   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1641     Parser.Lex(); // Eat the '('.
1642     S = Parser.getTok().getLoc();
1643 
1644     int64_t IntVal;
1645     switch (getLexer().getKind()) {
1646     case AsmToken::Percent:
1647       Parser.Lex(); // Eat the '%'.
1648       unsigned RegNo;
1649       if (MatchRegisterName(RegNo, IntVal))
1650         return Error(S, "invalid register name");
1651       break;
1652 
1653     case AsmToken::Integer:
1654       if (isDarwin())
1655         return Error(S, "unexpected integer value");
1656       else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 ||
1657                IntVal > 31)
1658         return Error(S, "invalid register number");
1659       break;
1660    case AsmToken::Identifier:
1661     if (isDarwin()) {
1662       unsigned RegNo;
1663       if (!MatchRegisterName(RegNo, IntVal)) {
1664         break;
1665       }
1666     }
1667     LLVM_FALLTHROUGH;
1668 
1669     default:
1670       return Error(S, "invalid memory operand");
1671     }
1672 
1673     E = Parser.getTok().getLoc();
1674     if (parseToken(AsmToken::RParen, "missing ')'"))
1675       return true;
1676     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1677   }
1678 
1679   return false;
1680 }
1681 
1682 /// Parse an instruction mnemonic followed by its operands.
1683 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1684                                     SMLoc NameLoc, OperandVector &Operands) {
1685   // The first operand is the token for the instruction name.
1686   // If the next character is a '+' or '-', we need to add it to the
1687   // instruction name, to match what TableGen is doing.
1688   std::string NewOpcode;
1689   if (parseOptionalToken(AsmToken::Plus)) {
1690     NewOpcode = Name;
1691     NewOpcode += '+';
1692     Name = NewOpcode;
1693   }
1694   if (parseOptionalToken(AsmToken::Minus)) {
1695     NewOpcode = Name;
1696     NewOpcode += '-';
1697     Name = NewOpcode;
1698   }
1699   // If the instruction ends in a '.', we need to create a separate
1700   // token for it, to match what TableGen is doing.
1701   size_t Dot = Name.find('.');
1702   StringRef Mnemonic = Name.slice(0, Dot);
1703   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1704     Operands.push_back(
1705         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1706   else
1707     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1708   if (Dot != StringRef::npos) {
1709     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1710     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1711     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1712       Operands.push_back(
1713           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1714     else
1715       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1716   }
1717 
1718   // If there are no more operands then finish
1719   if (parseOptionalToken(AsmToken::EndOfStatement))
1720     return false;
1721 
1722   // Parse the first operand
1723   if (ParseOperand(Operands))
1724     return true;
1725 
1726   while (!parseOptionalToken(AsmToken::EndOfStatement)) {
1727     if (parseToken(AsmToken::Comma) || ParseOperand(Operands))
1728       return true;
1729   }
1730 
1731   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1732   // and dcbtst instructions differs for server vs. embedded cores.
1733   //  The syntax for dcbt is:
1734   //    dcbt ra, rb, th [server]
1735   //    dcbt th, ra, rb [embedded]
1736   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1737   //  server form to be the default, so swap the operands if we're parsing for
1738   //  an embedded core (they'll be swapped again upon printing).
1739   if (getSTI().getFeatureBits()[PPC::FeatureBookE] &&
1740       Operands.size() == 4 &&
1741       (Name == "dcbt" || Name == "dcbtst")) {
1742     std::swap(Operands[1], Operands[3]);
1743     std::swap(Operands[2], Operands[1]);
1744   }
1745 
1746   return false;
1747 }
1748 
1749 /// ParseDirective parses the PPC specific directives
1750 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1751   StringRef IDVal = DirectiveID.getIdentifier();
1752   if (isDarwin()) {
1753     if (IDVal == ".machine")
1754       ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1755     else
1756       return true;
1757   } else if (IDVal == ".word")
1758     ParseDirectiveWord(2, DirectiveID);
1759   else if (IDVal == ".llong")
1760     ParseDirectiveWord(8, DirectiveID);
1761   else if (IDVal == ".tc")
1762     ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID);
1763   else if (IDVal == ".machine")
1764     ParseDirectiveMachine(DirectiveID.getLoc());
1765   else if (IDVal == ".abiversion")
1766     ParseDirectiveAbiVersion(DirectiveID.getLoc());
1767   else if (IDVal == ".localentry")
1768     ParseDirectiveLocalEntry(DirectiveID.getLoc());
1769   else
1770     return true;
1771   return false;
1772 }
1773 
1774 /// ParseDirectiveWord
1775 ///  ::= .word [ expression (, expression)* ]
1776 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) {
1777   auto parseOp = [&]() -> bool {
1778     const MCExpr *Value;
1779     SMLoc ExprLoc = getParser().getTok().getLoc();
1780     if (getParser().parseExpression(Value))
1781       return true;
1782     if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) {
1783       assert(Size <= 8 && "Invalid size");
1784       uint64_t IntValue = MCE->getValue();
1785       if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue))
1786         return Error(ExprLoc, "literal value out of range for '" +
1787                                   ID.getIdentifier() + "' directive");
1788       getStreamer().EmitIntValue(IntValue, Size);
1789     } else
1790       getStreamer().EmitValue(Value, Size, ExprLoc);
1791     return false;
1792   };
1793 
1794   if (parseMany(parseOp))
1795     return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive");
1796   return false;
1797 }
1798 
1799 /// ParseDirectiveTC
1800 ///  ::= .tc [ symbol (, expression)* ]
1801 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) {
1802   MCAsmParser &Parser = getParser();
1803   // Skip TC symbol, which is only used with XCOFF.
1804   while (getLexer().isNot(AsmToken::EndOfStatement)
1805          && getLexer().isNot(AsmToken::Comma))
1806     Parser.Lex();
1807   if (parseToken(AsmToken::Comma))
1808     return addErrorSuffix(" in '.tc' directive");
1809 
1810   // Align to word size.
1811   getParser().getStreamer().EmitValueToAlignment(Size);
1812 
1813   // Emit expressions.
1814   return ParseDirectiveWord(Size, ID);
1815 }
1816 
1817 /// ParseDirectiveMachine (ELF platforms)
1818 ///  ::= .machine [ cpu | "push" | "pop" ]
1819 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1820   MCAsmParser &Parser = getParser();
1821   if (Parser.getTok().isNot(AsmToken::Identifier) &&
1822       Parser.getTok().isNot(AsmToken::String))
1823     return Error(L, "unexpected token in '.machine' directive");
1824 
1825   StringRef CPU = Parser.getTok().getIdentifier();
1826 
1827   // FIXME: Right now, the parser always allows any available
1828   // instruction, so the .machine directive is not useful.
1829   // Implement ".machine any" (by doing nothing) for the benefit
1830   // of existing assembler code.  Likewise, we can then implement
1831   // ".machine push" and ".machine pop" as no-op.
1832   if (CPU != "any" && CPU != "push" && CPU != "pop")
1833     return TokError("unrecognized machine type");
1834 
1835   Parser.Lex();
1836 
1837   if (parseToken(AsmToken::EndOfStatement))
1838     return addErrorSuffix(" in '.machine' directive");
1839 
1840   PPCTargetStreamer &TStreamer =
1841       *static_cast<PPCTargetStreamer *>(
1842            getParser().getStreamer().getTargetStreamer());
1843   TStreamer.emitMachine(CPU);
1844 
1845   return false;
1846 }
1847 
1848 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1849 ///  ::= .machine cpu-identifier
1850 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1851   MCAsmParser &Parser = getParser();
1852   if (Parser.getTok().isNot(AsmToken::Identifier) &&
1853       Parser.getTok().isNot(AsmToken::String))
1854     return Error(L, "unexpected token in directive");
1855 
1856   StringRef CPU = Parser.getTok().getIdentifier();
1857   Parser.Lex();
1858 
1859   // FIXME: this is only the 'default' set of cpu variants.
1860   // However we don't act on this information at present, this is simply
1861   // allowing parsing to proceed with minimal sanity checking.
1862   if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L,
1863             "unrecognized cpu type") ||
1864       check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L,
1865             "wrong cpu type specified for 64bit") ||
1866       check(!isPPC64() && CPU == "ppc64", L,
1867             "wrong cpu type specified for 32bit") ||
1868       parseToken(AsmToken::EndOfStatement))
1869     return addErrorSuffix(" in '.machine' directive");
1870   return false;
1871 }
1872 
1873 /// ParseDirectiveAbiVersion
1874 ///  ::= .abiversion constant-expression
1875 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1876   int64_t AbiVersion;
1877   if (check(getParser().parseAbsoluteExpression(AbiVersion), L,
1878             "expected constant expression") ||
1879       parseToken(AsmToken::EndOfStatement))
1880     return addErrorSuffix(" in '.abiversion' directive");
1881 
1882   PPCTargetStreamer &TStreamer =
1883       *static_cast<PPCTargetStreamer *>(
1884            getParser().getStreamer().getTargetStreamer());
1885   TStreamer.emitAbiVersion(AbiVersion);
1886 
1887   return false;
1888 }
1889 
1890 /// ParseDirectiveLocalEntry
1891 ///  ::= .localentry symbol, expression
1892 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1893   StringRef Name;
1894   if (getParser().parseIdentifier(Name))
1895     return Error(L, "expected identifier in '.localentry' directive");
1896 
1897   MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name));
1898   const MCExpr *Expr;
1899 
1900   if (parseToken(AsmToken::Comma) ||
1901       check(getParser().parseExpression(Expr), L, "expected expression") ||
1902       parseToken(AsmToken::EndOfStatement))
1903     return addErrorSuffix(" in '.localentry' directive");
1904 
1905   PPCTargetStreamer &TStreamer =
1906       *static_cast<PPCTargetStreamer *>(
1907            getParser().getStreamer().getTargetStreamer());
1908   TStreamer.emitLocalEntry(Sym, Expr);
1909 
1910   return false;
1911 }
1912 
1913 
1914 
1915 /// Force static initialization.
1916 extern "C" void LLVMInitializePowerPCAsmParser() {
1917   RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target());
1918   RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target());
1919   RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget());
1920 }
1921 
1922 #define GET_REGISTER_MATCHER
1923 #define GET_MATCHER_IMPLEMENTATION
1924 #include "PPCGenAsmMatcher.inc"
1925 
1926 // Define this matcher function after the auto-generated include so we
1927 // have the match class enum definitions.
1928 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1929                                                   unsigned Kind) {
1930   // If the kind is a token for a literal immediate, check if our asm
1931   // operand matches. This is for InstAliases which have a fixed-value
1932   // immediate in the syntax.
1933   int64_t ImmVal;
1934   switch (Kind) {
1935     case MCK_0: ImmVal = 0; break;
1936     case MCK_1: ImmVal = 1; break;
1937     case MCK_2: ImmVal = 2; break;
1938     case MCK_3: ImmVal = 3; break;
1939     case MCK_4: ImmVal = 4; break;
1940     case MCK_5: ImmVal = 5; break;
1941     case MCK_6: ImmVal = 6; break;
1942     case MCK_7: ImmVal = 7; break;
1943     default: return Match_InvalidOperand;
1944   }
1945 
1946   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1947   if (Op.isImm() && Op.getImm() == ImmVal)
1948     return Match_Success;
1949 
1950   return Match_InvalidOperand;
1951 }
1952 
1953 const MCExpr *
1954 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1955                                   MCSymbolRefExpr::VariantKind Variant,
1956                                   MCContext &Ctx) {
1957   switch (Variant) {
1958   case MCSymbolRefExpr::VK_PPC_LO:
1959     return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1960   case MCSymbolRefExpr::VK_PPC_HI:
1961     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1962   case MCSymbolRefExpr::VK_PPC_HA:
1963     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1964   case MCSymbolRefExpr::VK_PPC_HIGHER:
1965     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1966   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1967     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1968   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1969     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1970   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1971     return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1972   default:
1973     return nullptr;
1974   }
1975 }
1976