1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCContext.h"
19 #include "llvm/MC/MCExpr.h"
20 #include "llvm/MC/MCInst.h"
21 #include "llvm/MC/MCInstrInfo.h"
22 #include "llvm/MC/MCParser/MCAsmLexer.h"
23 #include "llvm/MC/MCParser/MCAsmParser.h"
24 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
25 #include "llvm/MC/MCRegisterInfo.h"
26 #include "llvm/MC/MCStreamer.h"
27 #include "llvm/MC/MCSubtargetInfo.h"
28 #include "llvm/MC/MCTargetAsmParser.h"
29 #include "llvm/Support/SourceMgr.h"
30 #include "llvm/Support/TargetRegistry.h"
31 #include "llvm/Support/raw_ostream.h"
32 
33 using namespace llvm;
34 
35 static const MCPhysReg RRegs[32] = {
36   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
37   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
38   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
39   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
40   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
41   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
42   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
43   PPC::R28, PPC::R29, PPC::R30, PPC::R31
44 };
45 static const MCPhysReg RRegsNoR0[32] = {
46   PPC::ZERO,
47             PPC::R1,  PPC::R2,  PPC::R3,
48   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
49   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
50   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
51   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
52   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
53   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
54   PPC::R28, PPC::R29, PPC::R30, PPC::R31
55 };
56 static const MCPhysReg XRegs[32] = {
57   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
58   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
59   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
60   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
61   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
62   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
63   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
64   PPC::X28, PPC::X29, PPC::X30, PPC::X31
65 };
66 static const MCPhysReg XRegsNoX0[32] = {
67   PPC::ZERO8,
68             PPC::X1,  PPC::X2,  PPC::X3,
69   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
70   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
71   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
72   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
73   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
74   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
75   PPC::X28, PPC::X29, PPC::X30, PPC::X31
76 };
77 static const MCPhysReg FRegs[32] = {
78   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
79   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
80   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
81   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
82   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
83   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
84   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
85   PPC::F28, PPC::F29, PPC::F30, PPC::F31
86 };
87 static const MCPhysReg VRegs[32] = {
88   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
89   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
90   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
91   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
92   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
93   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
94   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
95   PPC::V28, PPC::V29, PPC::V30, PPC::V31
96 };
97 static const MCPhysReg VSRegs[64] = {
98   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
99   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
100   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
101   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
102   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
103   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
104   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
105   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
106 
107   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
108   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
109   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
110   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
111   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
112   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
113   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
114   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
115 };
116 static const MCPhysReg VSFRegs[64] = {
117   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
118   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
119   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
120   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
121   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
122   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
123   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
124   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
125 
126   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
127   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
128   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
129   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
130   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
131   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
132   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
133   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
134 };
135 static unsigned QFRegs[32] = {
136   PPC::QF0,  PPC::QF1,  PPC::QF2,  PPC::QF3,
137   PPC::QF4,  PPC::QF5,  PPC::QF6,  PPC::QF7,
138   PPC::QF8,  PPC::QF9,  PPC::QF10, PPC::QF11,
139   PPC::QF12, PPC::QF13, PPC::QF14, PPC::QF15,
140   PPC::QF16, PPC::QF17, PPC::QF18, PPC::QF19,
141   PPC::QF20, PPC::QF21, PPC::QF22, PPC::QF23,
142   PPC::QF24, PPC::QF25, PPC::QF26, PPC::QF27,
143   PPC::QF28, PPC::QF29, PPC::QF30, PPC::QF31
144 };
145 static const MCPhysReg CRBITRegs[32] = {
146   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
147   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
148   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
149   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
150   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
151   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
152   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
153   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
154 };
155 static const MCPhysReg CRRegs[8] = {
156   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
157   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
158 };
159 
160 // Evaluate an expression containing condition register
161 // or condition register field symbols.  Returns positive
162 // value on success, or -1 on error.
163 static int64_t
164 EvaluateCRExpr(const MCExpr *E) {
165   switch (E->getKind()) {
166   case MCExpr::Target:
167     return -1;
168 
169   case MCExpr::Constant: {
170     int64_t Res = cast<MCConstantExpr>(E)->getValue();
171     return Res < 0 ? -1 : Res;
172   }
173 
174   case MCExpr::SymbolRef: {
175     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
176     StringRef Name = SRE->getSymbol().getName();
177 
178     if (Name == "lt") return 0;
179     if (Name == "gt") return 1;
180     if (Name == "eq") return 2;
181     if (Name == "so") return 3;
182     if (Name == "un") return 3;
183 
184     if (Name == "cr0") return 0;
185     if (Name == "cr1") return 1;
186     if (Name == "cr2") return 2;
187     if (Name == "cr3") return 3;
188     if (Name == "cr4") return 4;
189     if (Name == "cr5") return 5;
190     if (Name == "cr6") return 6;
191     if (Name == "cr7") return 7;
192 
193     return -1;
194   }
195 
196   case MCExpr::Unary:
197     return -1;
198 
199   case MCExpr::Binary: {
200     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
201     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
202     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
203     int64_t Res;
204 
205     if (LHSVal < 0 || RHSVal < 0)
206       return -1;
207 
208     switch (BE->getOpcode()) {
209     default: return -1;
210     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
211     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
212     }
213 
214     return Res < 0 ? -1 : Res;
215   }
216   }
217 
218   llvm_unreachable("Invalid expression kind!");
219 }
220 
221 namespace {
222 
223 struct PPCOperand;
224 
225 class PPCAsmParser : public MCTargetAsmParser {
226   MCSubtargetInfo &STI;
227   const MCInstrInfo &MII;
228   bool IsPPC64;
229   bool IsDarwin;
230 
231   void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); }
232   bool Error(SMLoc L, const Twine &Msg) { return getParser().Error(L, Msg); }
233 
234   bool isPPC64() const { return IsPPC64; }
235   bool isDarwin() const { return IsDarwin; }
236 
237   bool MatchRegisterName(const AsmToken &Tok,
238                          unsigned &RegNo, int64_t &IntVal);
239 
240   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
241 
242   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
243                                         PPCMCExpr::VariantKind &Variant);
244   const MCExpr *FixupVariantKind(const MCExpr *E);
245   bool ParseExpression(const MCExpr *&EVal);
246   bool ParseDarwinExpression(const MCExpr *&EVal);
247 
248   bool ParseOperand(OperandVector &Operands);
249 
250   bool ParseDirectiveWord(unsigned Size, SMLoc L);
251   bool ParseDirectiveTC(unsigned Size, SMLoc L);
252   bool ParseDirectiveMachine(SMLoc L);
253   bool ParseDarwinDirectiveMachine(SMLoc L);
254   bool ParseDirectiveAbiVersion(SMLoc L);
255   bool ParseDirectiveLocalEntry(SMLoc L);
256 
257   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
258                                OperandVector &Operands, MCStreamer &Out,
259                                uint64_t &ErrorInfo,
260                                bool MatchingInlineAsm) override;
261 
262   void ProcessInstruction(MCInst &Inst, const OperandVector &Ops);
263 
264   /// @name Auto-generated Match Functions
265   /// {
266 
267 #define GET_ASSEMBLER_HEADER
268 #include "PPCGenAsmMatcher.inc"
269 
270   /// }
271 
272 
273 public:
274   PPCAsmParser(MCSubtargetInfo &STI, MCAsmParser &, const MCInstrInfo &MII,
275                const MCTargetOptions &Options)
276       : MCTargetAsmParser(), STI(STI), MII(MII) {
277     // Check for 64-bit vs. 32-bit pointer mode.
278     Triple TheTriple(STI.getTargetTriple());
279     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
280                TheTriple.getArch() == Triple::ppc64le);
281     IsDarwin = TheTriple.isMacOSX();
282     // Initialize the set of available features.
283     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
284   }
285 
286   bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
287                         SMLoc NameLoc, OperandVector &Operands) override;
288 
289   bool ParseDirective(AsmToken DirectiveID) override;
290 
291   unsigned validateTargetOperandClass(MCParsedAsmOperand &Op,
292                                       unsigned Kind) override;
293 
294   const MCExpr *applyModifierToExpr(const MCExpr *E,
295                                     MCSymbolRefExpr::VariantKind,
296                                     MCContext &Ctx) override;
297 };
298 
299 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
300 /// instruction.
301 struct PPCOperand : public MCParsedAsmOperand {
302   enum KindTy {
303     Token,
304     Immediate,
305     ContextImmediate,
306     Expression,
307     TLSRegister
308   } Kind;
309 
310   SMLoc StartLoc, EndLoc;
311   bool IsPPC64;
312 
313   struct TokOp {
314     const char *Data;
315     unsigned Length;
316   };
317 
318   struct ImmOp {
319     int64_t Val;
320   };
321 
322   struct ExprOp {
323     const MCExpr *Val;
324     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
325   };
326 
327   struct TLSRegOp {
328     const MCSymbolRefExpr *Sym;
329   };
330 
331   union {
332     struct TokOp Tok;
333     struct ImmOp Imm;
334     struct ExprOp Expr;
335     struct TLSRegOp TLSReg;
336   };
337 
338   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
339 public:
340   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
341     Kind = o.Kind;
342     StartLoc = o.StartLoc;
343     EndLoc = o.EndLoc;
344     IsPPC64 = o.IsPPC64;
345     switch (Kind) {
346     case Token:
347       Tok = o.Tok;
348       break;
349     case Immediate:
350     case ContextImmediate:
351       Imm = o.Imm;
352       break;
353     case Expression:
354       Expr = o.Expr;
355       break;
356     case TLSRegister:
357       TLSReg = o.TLSReg;
358       break;
359     }
360   }
361 
362   /// getStartLoc - Get the location of the first token of this operand.
363   SMLoc getStartLoc() const override { return StartLoc; }
364 
365   /// getEndLoc - Get the location of the last token of this operand.
366   SMLoc getEndLoc() const override { return EndLoc; }
367 
368   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
369   bool isPPC64() const { return IsPPC64; }
370 
371   int64_t getImm() const {
372     assert(Kind == Immediate && "Invalid access!");
373     return Imm.Val;
374   }
375   int64_t getImmS16Context() const {
376     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
377     if (Kind == Immediate)
378       return Imm.Val;
379     return static_cast<int16_t>(Imm.Val);
380   }
381   int64_t getImmU16Context() const {
382     assert((Kind == Immediate || Kind == ContextImmediate) && "Invalid access!");
383     return Imm.Val;
384   }
385 
386   const MCExpr *getExpr() const {
387     assert(Kind == Expression && "Invalid access!");
388     return Expr.Val;
389   }
390 
391   int64_t getExprCRVal() const {
392     assert(Kind == Expression && "Invalid access!");
393     return Expr.CRVal;
394   }
395 
396   const MCExpr *getTLSReg() const {
397     assert(Kind == TLSRegister && "Invalid access!");
398     return TLSReg.Sym;
399   }
400 
401   unsigned getReg() const override {
402     assert(isRegNumber() && "Invalid access!");
403     return (unsigned) Imm.Val;
404   }
405 
406   unsigned getVSReg() const {
407     assert(isVSRegNumber() && "Invalid access!");
408     return (unsigned) Imm.Val;
409   }
410 
411   unsigned getCCReg() const {
412     assert(isCCRegNumber() && "Invalid access!");
413     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
414   }
415 
416   unsigned getCRBit() const {
417     assert(isCRBitNumber() && "Invalid access!");
418     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
419   }
420 
421   unsigned getCRBitMask() const {
422     assert(isCRBitMask() && "Invalid access!");
423     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
424   }
425 
426   bool isToken() const override { return Kind == Token; }
427   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
428   bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); }
429   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
430   bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); }
431   bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); }
432   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
433   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
434   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
435   bool isU6ImmX2() const { return Kind == Immediate &&
436                                   isUInt<6>(getImm()) &&
437                                   (getImm() & 1) == 0; }
438   bool isU7ImmX4() const { return Kind == Immediate &&
439                                   isUInt<7>(getImm()) &&
440                                   (getImm() & 3) == 0; }
441   bool isU8ImmX8() const { return Kind == Immediate &&
442                                   isUInt<8>(getImm()) &&
443                                   (getImm() & 7) == 0; }
444   bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); }
445   bool isU16Imm() const {
446     switch (Kind) {
447       case Expression:
448         return true;
449       case Immediate:
450       case ContextImmediate:
451         return isUInt<16>(getImmU16Context());
452       default:
453         return false;
454     }
455   }
456   bool isS16Imm() const {
457     switch (Kind) {
458       case Expression:
459         return true;
460       case Immediate:
461       case ContextImmediate:
462         return isInt<16>(getImmS16Context());
463       default:
464         return false;
465     }
466   }
467   bool isS16ImmX4() const { return Kind == Expression ||
468                                    (Kind == Immediate && isInt<16>(getImm()) &&
469                                     (getImm() & 3) == 0); }
470   bool isS17Imm() const {
471     switch (Kind) {
472       case Expression:
473         return true;
474       case Immediate:
475       case ContextImmediate:
476         return isInt<17>(getImmS16Context());
477       default:
478         return false;
479     }
480   }
481   bool isTLSReg() const { return Kind == TLSRegister; }
482   bool isDirectBr() const {
483     if (Kind == Expression)
484       return true;
485     if (Kind != Immediate)
486       return false;
487     // Operand must be 64-bit aligned, signed 27-bit immediate.
488     if ((getImm() & 3) != 0)
489       return false;
490     if (isInt<26>(getImm()))
491       return true;
492     if (!IsPPC64) {
493       // In 32-bit mode, large 32-bit quantities wrap around.
494       if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm())))
495         return true;
496     }
497     return false;
498   }
499   bool isCondBr() const { return Kind == Expression ||
500                                  (Kind == Immediate && isInt<16>(getImm()) &&
501                                   (getImm() & 3) == 0); }
502   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
503   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
504   bool isCCRegNumber() const { return (Kind == Expression
505                                        && isUInt<3>(getExprCRVal())) ||
506                                       (Kind == Immediate
507                                        && isUInt<3>(getImm())); }
508   bool isCRBitNumber() const { return (Kind == Expression
509                                        && isUInt<5>(getExprCRVal())) ||
510                                       (Kind == Immediate
511                                        && isUInt<5>(getImm())); }
512   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
513                                     isPowerOf2_32(getImm()); }
514   bool isMem() const override { return false; }
515   bool isReg() const override { return false; }
516 
517   void addRegOperands(MCInst &Inst, unsigned N) const {
518     llvm_unreachable("addRegOperands");
519   }
520 
521   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
522     assert(N == 1 && "Invalid number of operands!");
523     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
524   }
525 
526   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
527     assert(N == 1 && "Invalid number of operands!");
528     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
529   }
530 
531   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
532     assert(N == 1 && "Invalid number of operands!");
533     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
534   }
535 
536   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
537     assert(N == 1 && "Invalid number of operands!");
538     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
539   }
540 
541   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
542     if (isPPC64())
543       addRegG8RCOperands(Inst, N);
544     else
545       addRegGPRCOperands(Inst, N);
546   }
547 
548   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
549     if (isPPC64())
550       addRegG8RCNoX0Operands(Inst, N);
551     else
552       addRegGPRCNoR0Operands(Inst, N);
553   }
554 
555   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
556     assert(N == 1 && "Invalid number of operands!");
557     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
558   }
559 
560   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
561     assert(N == 1 && "Invalid number of operands!");
562     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
563   }
564 
565   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
566     assert(N == 1 && "Invalid number of operands!");
567     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
568   }
569 
570   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
571     assert(N == 1 && "Invalid number of operands!");
572     Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
573   }
574 
575   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
576     assert(N == 1 && "Invalid number of operands!");
577     Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
578   }
579 
580   void addRegQFRCOperands(MCInst &Inst, unsigned N) const {
581     assert(N == 1 && "Invalid number of operands!");
582     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
583   }
584 
585   void addRegQSRCOperands(MCInst &Inst, unsigned N) const {
586     assert(N == 1 && "Invalid number of operands!");
587     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
588   }
589 
590   void addRegQBRCOperands(MCInst &Inst, unsigned N) const {
591     assert(N == 1 && "Invalid number of operands!");
592     Inst.addOperand(MCOperand::CreateReg(QFRegs[getReg()]));
593   }
594 
595   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
596     assert(N == 1 && "Invalid number of operands!");
597     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
598   }
599 
600   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
601     assert(N == 1 && "Invalid number of operands!");
602     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
603   }
604 
605   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
606     assert(N == 1 && "Invalid number of operands!");
607     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
608   }
609 
610   void addImmOperands(MCInst &Inst, unsigned N) const {
611     assert(N == 1 && "Invalid number of operands!");
612     if (Kind == Immediate)
613       Inst.addOperand(MCOperand::CreateImm(getImm()));
614     else
615       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
616   }
617 
618   void addS16ImmOperands(MCInst &Inst, unsigned N) const {
619     assert(N == 1 && "Invalid number of operands!");
620     switch (Kind) {
621       case Immediate:
622         Inst.addOperand(MCOperand::CreateImm(getImm()));
623         break;
624       case ContextImmediate:
625         Inst.addOperand(MCOperand::CreateImm(getImmS16Context()));
626         break;
627       default:
628         Inst.addOperand(MCOperand::CreateExpr(getExpr()));
629         break;
630     }
631   }
632 
633   void addU16ImmOperands(MCInst &Inst, unsigned N) const {
634     assert(N == 1 && "Invalid number of operands!");
635     switch (Kind) {
636       case Immediate:
637         Inst.addOperand(MCOperand::CreateImm(getImm()));
638         break;
639       case ContextImmediate:
640         Inst.addOperand(MCOperand::CreateImm(getImmU16Context()));
641         break;
642       default:
643         Inst.addOperand(MCOperand::CreateExpr(getExpr()));
644         break;
645     }
646   }
647 
648   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
649     assert(N == 1 && "Invalid number of operands!");
650     if (Kind == Immediate)
651       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
652     else
653       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
654   }
655 
656   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
657     assert(N == 1 && "Invalid number of operands!");
658     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
659   }
660 
661   StringRef getToken() const {
662     assert(Kind == Token && "Invalid access!");
663     return StringRef(Tok.Data, Tok.Length);
664   }
665 
666   void print(raw_ostream &OS) const override;
667 
668   static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S,
669                                                  bool IsPPC64) {
670     auto Op = make_unique<PPCOperand>(Token);
671     Op->Tok.Data = Str.data();
672     Op->Tok.Length = Str.size();
673     Op->StartLoc = S;
674     Op->EndLoc = S;
675     Op->IsPPC64 = IsPPC64;
676     return Op;
677   }
678 
679   static std::unique_ptr<PPCOperand>
680   CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) {
681     // Allocate extra memory for the string and copy it.
682     // FIXME: This is incorrect, Operands are owned by unique_ptr with a default
683     // deleter which will destroy them by simply using "delete", not correctly
684     // calling operator delete on this extra memory after calling the dtor
685     // explicitly.
686     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
687     std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token));
688     Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1);
689     Op->Tok.Length = Str.size();
690     std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size());
691     Op->StartLoc = S;
692     Op->EndLoc = S;
693     Op->IsPPC64 = IsPPC64;
694     return Op;
695   }
696 
697   static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E,
698                                                bool IsPPC64) {
699     auto Op = make_unique<PPCOperand>(Immediate);
700     Op->Imm.Val = Val;
701     Op->StartLoc = S;
702     Op->EndLoc = E;
703     Op->IsPPC64 = IsPPC64;
704     return Op;
705   }
706 
707   static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S,
708                                                 SMLoc E, bool IsPPC64) {
709     auto Op = make_unique<PPCOperand>(Expression);
710     Op->Expr.Val = Val;
711     Op->Expr.CRVal = EvaluateCRExpr(Val);
712     Op->StartLoc = S;
713     Op->EndLoc = E;
714     Op->IsPPC64 = IsPPC64;
715     return Op;
716   }
717 
718   static std::unique_ptr<PPCOperand>
719   CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) {
720     auto Op = make_unique<PPCOperand>(TLSRegister);
721     Op->TLSReg.Sym = Sym;
722     Op->StartLoc = S;
723     Op->EndLoc = E;
724     Op->IsPPC64 = IsPPC64;
725     return Op;
726   }
727 
728   static std::unique_ptr<PPCOperand>
729   CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
730     auto Op = make_unique<PPCOperand>(ContextImmediate);
731     Op->Imm.Val = Val;
732     Op->StartLoc = S;
733     Op->EndLoc = E;
734     Op->IsPPC64 = IsPPC64;
735     return Op;
736   }
737 
738   static std::unique_ptr<PPCOperand>
739   CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) {
740     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
741       return CreateImm(CE->getValue(), S, E, IsPPC64);
742 
743     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
744       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
745         return CreateTLSReg(SRE, S, E, IsPPC64);
746 
747     if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) {
748       int64_t Res;
749       if (TE->EvaluateAsConstant(Res))
750         return CreateContextImm(Res, S, E, IsPPC64);
751     }
752 
753     return CreateExpr(Val, S, E, IsPPC64);
754   }
755 };
756 
757 } // end anonymous namespace.
758 
759 void PPCOperand::print(raw_ostream &OS) const {
760   switch (Kind) {
761   case Token:
762     OS << "'" << getToken() << "'";
763     break;
764   case Immediate:
765   case ContextImmediate:
766     OS << getImm();
767     break;
768   case Expression:
769     getExpr()->print(OS);
770     break;
771   case TLSRegister:
772     getTLSReg()->print(OS);
773     break;
774   }
775 }
776 
777 static void
778 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) {
779   if (Op.isImm()) {
780     Inst.addOperand(MCOperand::CreateImm(-Op.getImm()));
781     return;
782   }
783   const MCExpr *Expr = Op.getExpr();
784   if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) {
785     if (UnExpr->getOpcode() == MCUnaryExpr::Minus) {
786       Inst.addOperand(MCOperand::CreateExpr(UnExpr->getSubExpr()));
787       return;
788     }
789   } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) {
790     if (BinExpr->getOpcode() == MCBinaryExpr::Sub) {
791       const MCExpr *NE = MCBinaryExpr::CreateSub(BinExpr->getRHS(),
792                                                  BinExpr->getLHS(), Ctx);
793       Inst.addOperand(MCOperand::CreateExpr(NE));
794       return;
795     }
796   }
797   Inst.addOperand(MCOperand::CreateExpr(MCUnaryExpr::CreateMinus(Expr, Ctx)));
798 }
799 
800 void PPCAsmParser::ProcessInstruction(MCInst &Inst,
801                                       const OperandVector &Operands) {
802   int Opcode = Inst.getOpcode();
803   switch (Opcode) {
804   case PPC::DCBTx:
805   case PPC::DCBTT:
806   case PPC::DCBTSTx:
807   case PPC::DCBTSTT: {
808     MCInst TmpInst;
809     TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
810                       PPC::DCBT : PPC::DCBTST);
811     TmpInst.addOperand(MCOperand::CreateImm(
812       (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16));
813     TmpInst.addOperand(Inst.getOperand(0));
814     TmpInst.addOperand(Inst.getOperand(1));
815     Inst = TmpInst;
816     break;
817   }
818   case PPC::DCBTCT:
819   case PPC::DCBTDS: {
820     MCInst TmpInst;
821     TmpInst.setOpcode(PPC::DCBT);
822     TmpInst.addOperand(Inst.getOperand(2));
823     TmpInst.addOperand(Inst.getOperand(0));
824     TmpInst.addOperand(Inst.getOperand(1));
825     Inst = TmpInst;
826     break;
827   }
828   case PPC::DCBTSTCT:
829   case PPC::DCBTSTDS: {
830     MCInst TmpInst;
831     TmpInst.setOpcode(PPC::DCBTST);
832     TmpInst.addOperand(Inst.getOperand(2));
833     TmpInst.addOperand(Inst.getOperand(0));
834     TmpInst.addOperand(Inst.getOperand(1));
835     Inst = TmpInst;
836     break;
837   }
838   case PPC::LAx: {
839     MCInst TmpInst;
840     TmpInst.setOpcode(PPC::LA);
841     TmpInst.addOperand(Inst.getOperand(0));
842     TmpInst.addOperand(Inst.getOperand(2));
843     TmpInst.addOperand(Inst.getOperand(1));
844     Inst = TmpInst;
845     break;
846   }
847   case PPC::SUBI: {
848     MCInst TmpInst;
849     TmpInst.setOpcode(PPC::ADDI);
850     TmpInst.addOperand(Inst.getOperand(0));
851     TmpInst.addOperand(Inst.getOperand(1));
852     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
853     Inst = TmpInst;
854     break;
855   }
856   case PPC::SUBIS: {
857     MCInst TmpInst;
858     TmpInst.setOpcode(PPC::ADDIS);
859     TmpInst.addOperand(Inst.getOperand(0));
860     TmpInst.addOperand(Inst.getOperand(1));
861     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
862     Inst = TmpInst;
863     break;
864   }
865   case PPC::SUBIC: {
866     MCInst TmpInst;
867     TmpInst.setOpcode(PPC::ADDIC);
868     TmpInst.addOperand(Inst.getOperand(0));
869     TmpInst.addOperand(Inst.getOperand(1));
870     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
871     Inst = TmpInst;
872     break;
873   }
874   case PPC::SUBICo: {
875     MCInst TmpInst;
876     TmpInst.setOpcode(PPC::ADDICo);
877     TmpInst.addOperand(Inst.getOperand(0));
878     TmpInst.addOperand(Inst.getOperand(1));
879     addNegOperand(TmpInst, Inst.getOperand(2), getContext());
880     Inst = TmpInst;
881     break;
882   }
883   case PPC::EXTLWI:
884   case PPC::EXTLWIo: {
885     MCInst TmpInst;
886     int64_t N = Inst.getOperand(2).getImm();
887     int64_t B = Inst.getOperand(3).getImm();
888     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
889     TmpInst.addOperand(Inst.getOperand(0));
890     TmpInst.addOperand(Inst.getOperand(1));
891     TmpInst.addOperand(MCOperand::CreateImm(B));
892     TmpInst.addOperand(MCOperand::CreateImm(0));
893     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
894     Inst = TmpInst;
895     break;
896   }
897   case PPC::EXTRWI:
898   case PPC::EXTRWIo: {
899     MCInst TmpInst;
900     int64_t N = Inst.getOperand(2).getImm();
901     int64_t B = Inst.getOperand(3).getImm();
902     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
903     TmpInst.addOperand(Inst.getOperand(0));
904     TmpInst.addOperand(Inst.getOperand(1));
905     TmpInst.addOperand(MCOperand::CreateImm(B + N));
906     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
907     TmpInst.addOperand(MCOperand::CreateImm(31));
908     Inst = TmpInst;
909     break;
910   }
911   case PPC::INSLWI:
912   case PPC::INSLWIo: {
913     MCInst TmpInst;
914     int64_t N = Inst.getOperand(2).getImm();
915     int64_t B = Inst.getOperand(3).getImm();
916     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
917     TmpInst.addOperand(Inst.getOperand(0));
918     TmpInst.addOperand(Inst.getOperand(0));
919     TmpInst.addOperand(Inst.getOperand(1));
920     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
921     TmpInst.addOperand(MCOperand::CreateImm(B));
922     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
923     Inst = TmpInst;
924     break;
925   }
926   case PPC::INSRWI:
927   case PPC::INSRWIo: {
928     MCInst TmpInst;
929     int64_t N = Inst.getOperand(2).getImm();
930     int64_t B = Inst.getOperand(3).getImm();
931     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
932     TmpInst.addOperand(Inst.getOperand(0));
933     TmpInst.addOperand(Inst.getOperand(0));
934     TmpInst.addOperand(Inst.getOperand(1));
935     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
936     TmpInst.addOperand(MCOperand::CreateImm(B));
937     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
938     Inst = TmpInst;
939     break;
940   }
941   case PPC::ROTRWI:
942   case PPC::ROTRWIo: {
943     MCInst TmpInst;
944     int64_t N = Inst.getOperand(2).getImm();
945     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
946     TmpInst.addOperand(Inst.getOperand(0));
947     TmpInst.addOperand(Inst.getOperand(1));
948     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
949     TmpInst.addOperand(MCOperand::CreateImm(0));
950     TmpInst.addOperand(MCOperand::CreateImm(31));
951     Inst = TmpInst;
952     break;
953   }
954   case PPC::SLWI:
955   case PPC::SLWIo: {
956     MCInst TmpInst;
957     int64_t N = Inst.getOperand(2).getImm();
958     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
959     TmpInst.addOperand(Inst.getOperand(0));
960     TmpInst.addOperand(Inst.getOperand(1));
961     TmpInst.addOperand(MCOperand::CreateImm(N));
962     TmpInst.addOperand(MCOperand::CreateImm(0));
963     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
964     Inst = TmpInst;
965     break;
966   }
967   case PPC::SRWI:
968   case PPC::SRWIo: {
969     MCInst TmpInst;
970     int64_t N = Inst.getOperand(2).getImm();
971     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
972     TmpInst.addOperand(Inst.getOperand(0));
973     TmpInst.addOperand(Inst.getOperand(1));
974     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
975     TmpInst.addOperand(MCOperand::CreateImm(N));
976     TmpInst.addOperand(MCOperand::CreateImm(31));
977     Inst = TmpInst;
978     break;
979   }
980   case PPC::CLRRWI:
981   case PPC::CLRRWIo: {
982     MCInst TmpInst;
983     int64_t N = Inst.getOperand(2).getImm();
984     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
985     TmpInst.addOperand(Inst.getOperand(0));
986     TmpInst.addOperand(Inst.getOperand(1));
987     TmpInst.addOperand(MCOperand::CreateImm(0));
988     TmpInst.addOperand(MCOperand::CreateImm(0));
989     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
990     Inst = TmpInst;
991     break;
992   }
993   case PPC::CLRLSLWI:
994   case PPC::CLRLSLWIo: {
995     MCInst TmpInst;
996     int64_t B = Inst.getOperand(2).getImm();
997     int64_t N = Inst.getOperand(3).getImm();
998     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
999     TmpInst.addOperand(Inst.getOperand(0));
1000     TmpInst.addOperand(Inst.getOperand(1));
1001     TmpInst.addOperand(MCOperand::CreateImm(N));
1002     TmpInst.addOperand(MCOperand::CreateImm(B - N));
1003     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
1004     Inst = TmpInst;
1005     break;
1006   }
1007   case PPC::EXTLDI:
1008   case PPC::EXTLDIo: {
1009     MCInst TmpInst;
1010     int64_t N = Inst.getOperand(2).getImm();
1011     int64_t B = Inst.getOperand(3).getImm();
1012     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
1013     TmpInst.addOperand(Inst.getOperand(0));
1014     TmpInst.addOperand(Inst.getOperand(1));
1015     TmpInst.addOperand(MCOperand::CreateImm(B));
1016     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
1017     Inst = TmpInst;
1018     break;
1019   }
1020   case PPC::EXTRDI:
1021   case PPC::EXTRDIo: {
1022     MCInst TmpInst;
1023     int64_t N = Inst.getOperand(2).getImm();
1024     int64_t B = Inst.getOperand(3).getImm();
1025     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
1026     TmpInst.addOperand(Inst.getOperand(0));
1027     TmpInst.addOperand(Inst.getOperand(1));
1028     TmpInst.addOperand(MCOperand::CreateImm(B + N));
1029     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1030     Inst = TmpInst;
1031     break;
1032   }
1033   case PPC::INSRDI:
1034   case PPC::INSRDIo: {
1035     MCInst TmpInst;
1036     int64_t N = Inst.getOperand(2).getImm();
1037     int64_t B = Inst.getOperand(3).getImm();
1038     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
1039     TmpInst.addOperand(Inst.getOperand(0));
1040     TmpInst.addOperand(Inst.getOperand(0));
1041     TmpInst.addOperand(Inst.getOperand(1));
1042     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
1043     TmpInst.addOperand(MCOperand::CreateImm(B));
1044     Inst = TmpInst;
1045     break;
1046   }
1047   case PPC::ROTRDI:
1048   case PPC::ROTRDIo: {
1049     MCInst TmpInst;
1050     int64_t N = Inst.getOperand(2).getImm();
1051     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
1052     TmpInst.addOperand(Inst.getOperand(0));
1053     TmpInst.addOperand(Inst.getOperand(1));
1054     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1055     TmpInst.addOperand(MCOperand::CreateImm(0));
1056     Inst = TmpInst;
1057     break;
1058   }
1059   case PPC::SLDI:
1060   case PPC::SLDIo: {
1061     MCInst TmpInst;
1062     int64_t N = Inst.getOperand(2).getImm();
1063     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
1064     TmpInst.addOperand(Inst.getOperand(0));
1065     TmpInst.addOperand(Inst.getOperand(1));
1066     TmpInst.addOperand(MCOperand::CreateImm(N));
1067     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1068     Inst = TmpInst;
1069     break;
1070   }
1071   case PPC::SRDI:
1072   case PPC::SRDIo: {
1073     MCInst TmpInst;
1074     int64_t N = Inst.getOperand(2).getImm();
1075     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
1076     TmpInst.addOperand(Inst.getOperand(0));
1077     TmpInst.addOperand(Inst.getOperand(1));
1078     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
1079     TmpInst.addOperand(MCOperand::CreateImm(N));
1080     Inst = TmpInst;
1081     break;
1082   }
1083   case PPC::CLRRDI:
1084   case PPC::CLRRDIo: {
1085     MCInst TmpInst;
1086     int64_t N = Inst.getOperand(2).getImm();
1087     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
1088     TmpInst.addOperand(Inst.getOperand(0));
1089     TmpInst.addOperand(Inst.getOperand(1));
1090     TmpInst.addOperand(MCOperand::CreateImm(0));
1091     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
1092     Inst = TmpInst;
1093     break;
1094   }
1095   case PPC::CLRLSLDI:
1096   case PPC::CLRLSLDIo: {
1097     MCInst TmpInst;
1098     int64_t B = Inst.getOperand(2).getImm();
1099     int64_t N = Inst.getOperand(3).getImm();
1100     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
1101     TmpInst.addOperand(Inst.getOperand(0));
1102     TmpInst.addOperand(Inst.getOperand(1));
1103     TmpInst.addOperand(MCOperand::CreateImm(N));
1104     TmpInst.addOperand(MCOperand::CreateImm(B - N));
1105     Inst = TmpInst;
1106     break;
1107   }
1108   case PPC::RLWINMbm:
1109   case PPC::RLWINMobm: {
1110     unsigned MB, ME;
1111     int64_t BM = Inst.getOperand(3).getImm();
1112     if (!isRunOfOnes(BM, MB, ME))
1113       break;
1114 
1115     MCInst TmpInst;
1116     TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINMo);
1117     TmpInst.addOperand(Inst.getOperand(0));
1118     TmpInst.addOperand(Inst.getOperand(1));
1119     TmpInst.addOperand(Inst.getOperand(2));
1120     TmpInst.addOperand(MCOperand::CreateImm(MB));
1121     TmpInst.addOperand(MCOperand::CreateImm(ME));
1122     Inst = TmpInst;
1123     break;
1124   }
1125   case PPC::RLWIMIbm:
1126   case PPC::RLWIMIobm: {
1127     unsigned MB, ME;
1128     int64_t BM = Inst.getOperand(3).getImm();
1129     if (!isRunOfOnes(BM, MB, ME))
1130       break;
1131 
1132     MCInst TmpInst;
1133     TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMIo);
1134     TmpInst.addOperand(Inst.getOperand(0));
1135     TmpInst.addOperand(Inst.getOperand(0)); // The tied operand.
1136     TmpInst.addOperand(Inst.getOperand(1));
1137     TmpInst.addOperand(Inst.getOperand(2));
1138     TmpInst.addOperand(MCOperand::CreateImm(MB));
1139     TmpInst.addOperand(MCOperand::CreateImm(ME));
1140     Inst = TmpInst;
1141     break;
1142   }
1143   case PPC::RLWNMbm:
1144   case PPC::RLWNMobm: {
1145     unsigned MB, ME;
1146     int64_t BM = Inst.getOperand(3).getImm();
1147     if (!isRunOfOnes(BM, MB, ME))
1148       break;
1149 
1150     MCInst TmpInst;
1151     TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNMo);
1152     TmpInst.addOperand(Inst.getOperand(0));
1153     TmpInst.addOperand(Inst.getOperand(1));
1154     TmpInst.addOperand(Inst.getOperand(2));
1155     TmpInst.addOperand(MCOperand::CreateImm(MB));
1156     TmpInst.addOperand(MCOperand::CreateImm(ME));
1157     Inst = TmpInst;
1158     break;
1159   }
1160   }
1161 }
1162 
1163 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
1164                                            OperandVector &Operands,
1165                                            MCStreamer &Out, uint64_t &ErrorInfo,
1166                                            bool MatchingInlineAsm) {
1167   MCInst Inst;
1168 
1169   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
1170   case Match_Success:
1171     // Post-process instructions (typically extended mnemonics)
1172     ProcessInstruction(Inst, Operands);
1173     Inst.setLoc(IDLoc);
1174     Out.EmitInstruction(Inst, STI);
1175     return false;
1176   case Match_MissingFeature:
1177     return Error(IDLoc, "instruction use requires an option to be enabled");
1178   case Match_MnemonicFail:
1179     return Error(IDLoc, "unrecognized instruction mnemonic");
1180   case Match_InvalidOperand: {
1181     SMLoc ErrorLoc = IDLoc;
1182     if (ErrorInfo != ~0ULL) {
1183       if (ErrorInfo >= Operands.size())
1184         return Error(IDLoc, "too few operands for instruction");
1185 
1186       ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc();
1187       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
1188     }
1189 
1190     return Error(ErrorLoc, "invalid operand for instruction");
1191   }
1192   }
1193 
1194   llvm_unreachable("Implement any new match types added!");
1195 }
1196 
1197 bool PPCAsmParser::
1198 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
1199   if (Tok.is(AsmToken::Identifier)) {
1200     StringRef Name = Tok.getString();
1201 
1202     if (Name.equals_lower("lr")) {
1203       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
1204       IntVal = 8;
1205       return false;
1206     } else if (Name.equals_lower("ctr")) {
1207       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
1208       IntVal = 9;
1209       return false;
1210     } else if (Name.equals_lower("vrsave")) {
1211       RegNo = PPC::VRSAVE;
1212       IntVal = 256;
1213       return false;
1214     } else if (Name.startswith_lower("r") &&
1215                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1216       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
1217       return false;
1218     } else if (Name.startswith_lower("f") &&
1219                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1220       RegNo = FRegs[IntVal];
1221       return false;
1222     } else if (Name.startswith_lower("vs") &&
1223                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) {
1224       RegNo = VSRegs[IntVal];
1225       return false;
1226     } else if (Name.startswith_lower("v") &&
1227                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1228       RegNo = VRegs[IntVal];
1229       return false;
1230     } else if (Name.startswith_lower("q") &&
1231                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
1232       RegNo = QFRegs[IntVal];
1233       return false;
1234     } else if (Name.startswith_lower("cr") &&
1235                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
1236       RegNo = CRRegs[IntVal];
1237       return false;
1238     }
1239   }
1240 
1241   return true;
1242 }
1243 
1244 bool PPCAsmParser::
1245 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
1246   MCAsmParser &Parser = getParser();
1247   const AsmToken &Tok = Parser.getTok();
1248   StartLoc = Tok.getLoc();
1249   EndLoc = Tok.getEndLoc();
1250   RegNo = 0;
1251   int64_t IntVal;
1252 
1253   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1254     Parser.Lex(); // Eat identifier token.
1255     return false;
1256   }
1257 
1258   return Error(StartLoc, "invalid register name");
1259 }
1260 
1261 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1262 /// the expression and check for VK_PPC_LO/HI/HA
1263 /// symbol variants.  If all symbols with modifier use the same
1264 /// variant, return the corresponding PPCMCExpr::VariantKind,
1265 /// and a modified expression using the default symbol variant.
1266 /// Otherwise, return NULL.
1267 const MCExpr *PPCAsmParser::
1268 ExtractModifierFromExpr(const MCExpr *E,
1269                         PPCMCExpr::VariantKind &Variant) {
1270   MCContext &Context = getParser().getContext();
1271   Variant = PPCMCExpr::VK_PPC_None;
1272 
1273   switch (E->getKind()) {
1274   case MCExpr::Target:
1275   case MCExpr::Constant:
1276     return nullptr;
1277 
1278   case MCExpr::SymbolRef: {
1279     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1280 
1281     switch (SRE->getKind()) {
1282     case MCSymbolRefExpr::VK_PPC_LO:
1283       Variant = PPCMCExpr::VK_PPC_LO;
1284       break;
1285     case MCSymbolRefExpr::VK_PPC_HI:
1286       Variant = PPCMCExpr::VK_PPC_HI;
1287       break;
1288     case MCSymbolRefExpr::VK_PPC_HA:
1289       Variant = PPCMCExpr::VK_PPC_HA;
1290       break;
1291     case MCSymbolRefExpr::VK_PPC_HIGHER:
1292       Variant = PPCMCExpr::VK_PPC_HIGHER;
1293       break;
1294     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1295       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1296       break;
1297     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1298       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1299       break;
1300     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1301       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1302       break;
1303     default:
1304       return nullptr;
1305     }
1306 
1307     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1308   }
1309 
1310   case MCExpr::Unary: {
1311     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1312     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1313     if (!Sub)
1314       return nullptr;
1315     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1316   }
1317 
1318   case MCExpr::Binary: {
1319     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1320     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1321     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1322     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1323 
1324     if (!LHS && !RHS)
1325       return nullptr;
1326 
1327     if (!LHS) LHS = BE->getLHS();
1328     if (!RHS) RHS = BE->getRHS();
1329 
1330     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1331       Variant = RHSVariant;
1332     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1333       Variant = LHSVariant;
1334     else if (LHSVariant == RHSVariant)
1335       Variant = LHSVariant;
1336     else
1337       return nullptr;
1338 
1339     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1340   }
1341   }
1342 
1343   llvm_unreachable("Invalid expression kind!");
1344 }
1345 
1346 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1347 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1348 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1349 /// FIXME: This is a hack.
1350 const MCExpr *PPCAsmParser::
1351 FixupVariantKind(const MCExpr *E) {
1352   MCContext &Context = getParser().getContext();
1353 
1354   switch (E->getKind()) {
1355   case MCExpr::Target:
1356   case MCExpr::Constant:
1357     return E;
1358 
1359   case MCExpr::SymbolRef: {
1360     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1361     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1362 
1363     switch (SRE->getKind()) {
1364     case MCSymbolRefExpr::VK_TLSGD:
1365       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1366       break;
1367     case MCSymbolRefExpr::VK_TLSLD:
1368       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1369       break;
1370     default:
1371       return E;
1372     }
1373     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1374   }
1375 
1376   case MCExpr::Unary: {
1377     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1378     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1379     if (Sub == UE->getSubExpr())
1380       return E;
1381     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1382   }
1383 
1384   case MCExpr::Binary: {
1385     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1386     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1387     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1388     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1389       return E;
1390     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1391   }
1392   }
1393 
1394   llvm_unreachable("Invalid expression kind!");
1395 }
1396 
1397 /// ParseExpression.  This differs from the default "parseExpression" in that
1398 /// it handles modifiers.
1399 bool PPCAsmParser::
1400 ParseExpression(const MCExpr *&EVal) {
1401 
1402   if (isDarwin())
1403     return ParseDarwinExpression(EVal);
1404 
1405   // (ELF Platforms)
1406   // Handle \code @l/@ha \endcode
1407   if (getParser().parseExpression(EVal))
1408     return true;
1409 
1410   EVal = FixupVariantKind(EVal);
1411 
1412   PPCMCExpr::VariantKind Variant;
1413   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1414   if (E)
1415     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1416 
1417   return false;
1418 }
1419 
1420 /// ParseDarwinExpression.  (MachO Platforms)
1421 /// This differs from the default "parseExpression" in that it handles detection
1422 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1423 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1424 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1425 /// for this to be done at a higher level.
1426 bool PPCAsmParser::
1427 ParseDarwinExpression(const MCExpr *&EVal) {
1428   MCAsmParser &Parser = getParser();
1429   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1430   switch (getLexer().getKind()) {
1431   default:
1432     break;
1433   case AsmToken::Identifier:
1434     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1435     // something starting with any other char should be part of the
1436     // asm syntax.  If handwritten asm includes an identifier like lo16,
1437     // then all bets are off - but no-one would do that, right?
1438     StringRef poss = Parser.getTok().getString();
1439     if (poss.equals_lower("lo16")) {
1440       Variant = PPCMCExpr::VK_PPC_LO;
1441     } else if (poss.equals_lower("hi16")) {
1442       Variant = PPCMCExpr::VK_PPC_HI;
1443     } else if (poss.equals_lower("ha16")) {
1444       Variant = PPCMCExpr::VK_PPC_HA;
1445     }
1446     if (Variant != PPCMCExpr::VK_PPC_None) {
1447       Parser.Lex(); // Eat the xx16
1448       if (getLexer().isNot(AsmToken::LParen))
1449         return Error(Parser.getTok().getLoc(), "expected '('");
1450       Parser.Lex(); // Eat the '('
1451     }
1452     break;
1453   }
1454 
1455   if (getParser().parseExpression(EVal))
1456     return true;
1457 
1458   if (Variant != PPCMCExpr::VK_PPC_None) {
1459     if (getLexer().isNot(AsmToken::RParen))
1460       return Error(Parser.getTok().getLoc(), "expected ')'");
1461     Parser.Lex(); // Eat the ')'
1462     EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1463   }
1464   return false;
1465 }
1466 
1467 /// ParseOperand
1468 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1469 /// rNN for MachO.
1470 bool PPCAsmParser::ParseOperand(OperandVector &Operands) {
1471   MCAsmParser &Parser = getParser();
1472   SMLoc S = Parser.getTok().getLoc();
1473   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1474   const MCExpr *EVal;
1475 
1476   // Attempt to parse the next token as an immediate
1477   switch (getLexer().getKind()) {
1478   // Special handling for register names.  These are interpreted
1479   // as immediates corresponding to the register number.
1480   case AsmToken::Percent:
1481     Parser.Lex(); // Eat the '%'.
1482     unsigned RegNo;
1483     int64_t IntVal;
1484     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1485       Parser.Lex(); // Eat the identifier token.
1486       Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1487       return false;
1488     }
1489     return Error(S, "invalid register name");
1490 
1491   case AsmToken::Identifier:
1492     // Note that non-register-name identifiers from the compiler will begin
1493     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1494     // identifiers like r31foo - so we fall through in the event that parsing
1495     // a register name fails.
1496     if (isDarwin()) {
1497       unsigned RegNo;
1498       int64_t IntVal;
1499       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1500         Parser.Lex(); // Eat the identifier token.
1501         Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1502         return false;
1503       }
1504     }
1505   // Fall-through to process non-register-name identifiers as expression.
1506   // All other expressions
1507   case AsmToken::LParen:
1508   case AsmToken::Plus:
1509   case AsmToken::Minus:
1510   case AsmToken::Integer:
1511   case AsmToken::Dot:
1512   case AsmToken::Dollar:
1513   case AsmToken::Exclaim:
1514   case AsmToken::Tilde:
1515     if (!ParseExpression(EVal))
1516       break;
1517     /* fall through */
1518   default:
1519     return Error(S, "unknown operand");
1520   }
1521 
1522   // Push the parsed operand into the list of operands
1523   Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()));
1524 
1525   // Check whether this is a TLS call expression
1526   bool TLSCall = false;
1527   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1528     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1529 
1530   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1531     const MCExpr *TLSSym;
1532 
1533     Parser.Lex(); // Eat the '('.
1534     S = Parser.getTok().getLoc();
1535     if (ParseExpression(TLSSym))
1536       return Error(S, "invalid TLS call expression");
1537     if (getLexer().isNot(AsmToken::RParen))
1538       return Error(Parser.getTok().getLoc(), "missing ')'");
1539     E = Parser.getTok().getLoc();
1540     Parser.Lex(); // Eat the ')'.
1541 
1542     Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()));
1543   }
1544 
1545   // Otherwise, check for D-form memory operands
1546   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1547     Parser.Lex(); // Eat the '('.
1548     S = Parser.getTok().getLoc();
1549 
1550     int64_t IntVal;
1551     switch (getLexer().getKind()) {
1552     case AsmToken::Percent:
1553       Parser.Lex(); // Eat the '%'.
1554       unsigned RegNo;
1555       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1556         return Error(S, "invalid register name");
1557       Parser.Lex(); // Eat the identifier token.
1558       break;
1559 
1560     case AsmToken::Integer:
1561       if (!isDarwin()) {
1562         if (getParser().parseAbsoluteExpression(IntVal) ||
1563           IntVal < 0 || IntVal > 31)
1564         return Error(S, "invalid register number");
1565       } else {
1566         return Error(S, "unexpected integer value");
1567       }
1568       break;
1569 
1570    case AsmToken::Identifier:
1571     if (isDarwin()) {
1572       unsigned RegNo;
1573       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1574         Parser.Lex(); // Eat the identifier token.
1575         break;
1576       }
1577     }
1578     // Fall-through..
1579 
1580     default:
1581       return Error(S, "invalid memory operand");
1582     }
1583 
1584     if (getLexer().isNot(AsmToken::RParen))
1585       return Error(Parser.getTok().getLoc(), "missing ')'");
1586     E = Parser.getTok().getLoc();
1587     Parser.Lex(); // Eat the ')'.
1588 
1589     Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64()));
1590   }
1591 
1592   return false;
1593 }
1594 
1595 /// Parse an instruction mnemonic followed by its operands.
1596 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name,
1597                                     SMLoc NameLoc, OperandVector &Operands) {
1598   // The first operand is the token for the instruction name.
1599   // If the next character is a '+' or '-', we need to add it to the
1600   // instruction name, to match what TableGen is doing.
1601   std::string NewOpcode;
1602   if (getLexer().is(AsmToken::Plus)) {
1603     getLexer().Lex();
1604     NewOpcode = Name;
1605     NewOpcode += '+';
1606     Name = NewOpcode;
1607   }
1608   if (getLexer().is(AsmToken::Minus)) {
1609     getLexer().Lex();
1610     NewOpcode = Name;
1611     NewOpcode += '-';
1612     Name = NewOpcode;
1613   }
1614   // If the instruction ends in a '.', we need to create a separate
1615   // token for it, to match what TableGen is doing.
1616   size_t Dot = Name.find('.');
1617   StringRef Mnemonic = Name.slice(0, Dot);
1618   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1619     Operands.push_back(
1620         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1621   else
1622     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1623   if (Dot != StringRef::npos) {
1624     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1625     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1626     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1627       Operands.push_back(
1628           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1629     else
1630       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1631   }
1632 
1633   // If there are no more operands then finish
1634   if (getLexer().is(AsmToken::EndOfStatement))
1635     return false;
1636 
1637   // Parse the first operand
1638   if (ParseOperand(Operands))
1639     return true;
1640 
1641   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1642          getLexer().is(AsmToken::Comma)) {
1643     // Consume the comma token
1644     getLexer().Lex();
1645 
1646     // Parse the next operand
1647     if (ParseOperand(Operands))
1648       return true;
1649   }
1650 
1651   // We'll now deal with an unfortunate special case: the syntax for the dcbt
1652   // and dcbtst instructions differs for server vs. embedded cores.
1653   //  The syntax for dcbt is:
1654   //    dcbt ra, rb, th [server]
1655   //    dcbt th, ra, rb [embedded]
1656   //  where th can be omitted when it is 0. dcbtst is the same. We take the
1657   //  server form to be the default, so swap the operands if we're parsing for
1658   //  an embedded core (they'll be swapped again upon printing).
1659   if ((STI.getFeatureBits() & PPC::FeatureBookE) != 0 &&
1660       Operands.size() == 4 &&
1661       (Name == "dcbt" || Name == "dcbtst")) {
1662     std::swap(Operands[1], Operands[3]);
1663     std::swap(Operands[2], Operands[1]);
1664   }
1665 
1666   return false;
1667 }
1668 
1669 /// ParseDirective parses the PPC specific directives
1670 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1671   StringRef IDVal = DirectiveID.getIdentifier();
1672   if (!isDarwin()) {
1673     if (IDVal == ".word")
1674       return ParseDirectiveWord(2, DirectiveID.getLoc());
1675     if (IDVal == ".llong")
1676       return ParseDirectiveWord(8, DirectiveID.getLoc());
1677     if (IDVal == ".tc")
1678       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1679     if (IDVal == ".machine")
1680       return ParseDirectiveMachine(DirectiveID.getLoc());
1681     if (IDVal == ".abiversion")
1682       return ParseDirectiveAbiVersion(DirectiveID.getLoc());
1683     if (IDVal == ".localentry")
1684       return ParseDirectiveLocalEntry(DirectiveID.getLoc());
1685   } else {
1686     if (IDVal == ".machine")
1687       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1688   }
1689   return true;
1690 }
1691 
1692 /// ParseDirectiveWord
1693 ///  ::= .word [ expression (, expression)* ]
1694 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1695   MCAsmParser &Parser = getParser();
1696   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1697     for (;;) {
1698       const MCExpr *Value;
1699       if (getParser().parseExpression(Value))
1700         return false;
1701 
1702       getParser().getStreamer().EmitValue(Value, Size);
1703 
1704       if (getLexer().is(AsmToken::EndOfStatement))
1705         break;
1706 
1707       if (getLexer().isNot(AsmToken::Comma))
1708         return Error(L, "unexpected token in directive");
1709       Parser.Lex();
1710     }
1711   }
1712 
1713   Parser.Lex();
1714   return false;
1715 }
1716 
1717 /// ParseDirectiveTC
1718 ///  ::= .tc [ symbol (, expression)* ]
1719 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1720   MCAsmParser &Parser = getParser();
1721   // Skip TC symbol, which is only used with XCOFF.
1722   while (getLexer().isNot(AsmToken::EndOfStatement)
1723          && getLexer().isNot(AsmToken::Comma))
1724     Parser.Lex();
1725   if (getLexer().isNot(AsmToken::Comma)) {
1726     Error(L, "unexpected token in directive");
1727     return false;
1728   }
1729   Parser.Lex();
1730 
1731   // Align to word size.
1732   getParser().getStreamer().EmitValueToAlignment(Size);
1733 
1734   // Emit expressions.
1735   return ParseDirectiveWord(Size, L);
1736 }
1737 
1738 /// ParseDirectiveMachine (ELF platforms)
1739 ///  ::= .machine [ cpu | "push" | "pop" ]
1740 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1741   MCAsmParser &Parser = getParser();
1742   if (getLexer().isNot(AsmToken::Identifier) &&
1743       getLexer().isNot(AsmToken::String)) {
1744     Error(L, "unexpected token in directive");
1745     return false;
1746   }
1747 
1748   StringRef CPU = Parser.getTok().getIdentifier();
1749   Parser.Lex();
1750 
1751   // FIXME: Right now, the parser always allows any available
1752   // instruction, so the .machine directive is not useful.
1753   // Implement ".machine any" (by doing nothing) for the benefit
1754   // of existing assembler code.  Likewise, we can then implement
1755   // ".machine push" and ".machine pop" as no-op.
1756   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1757     Error(L, "unrecognized machine type");
1758     return false;
1759   }
1760 
1761   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1762     Error(L, "unexpected token in directive");
1763     return false;
1764   }
1765   PPCTargetStreamer &TStreamer =
1766       *static_cast<PPCTargetStreamer *>(
1767            getParser().getStreamer().getTargetStreamer());
1768   TStreamer.emitMachine(CPU);
1769 
1770   return false;
1771 }
1772 
1773 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1774 ///  ::= .machine cpu-identifier
1775 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1776   MCAsmParser &Parser = getParser();
1777   if (getLexer().isNot(AsmToken::Identifier) &&
1778       getLexer().isNot(AsmToken::String)) {
1779     Error(L, "unexpected token in directive");
1780     return false;
1781   }
1782 
1783   StringRef CPU = Parser.getTok().getIdentifier();
1784   Parser.Lex();
1785 
1786   // FIXME: this is only the 'default' set of cpu variants.
1787   // However we don't act on this information at present, this is simply
1788   // allowing parsing to proceed with minimal sanity checking.
1789   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1790     Error(L, "unrecognized cpu type");
1791     return false;
1792   }
1793 
1794   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1795     Error(L, "wrong cpu type specified for 64bit");
1796     return false;
1797   }
1798   if (!isPPC64() && CPU == "ppc64") {
1799     Error(L, "wrong cpu type specified for 32bit");
1800     return false;
1801   }
1802 
1803   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1804     Error(L, "unexpected token in directive");
1805     return false;
1806   }
1807 
1808   return false;
1809 }
1810 
1811 /// ParseDirectiveAbiVersion
1812 ///  ::= .abiversion constant-expression
1813 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) {
1814   int64_t AbiVersion;
1815   if (getParser().parseAbsoluteExpression(AbiVersion)){
1816     Error(L, "expected constant expression");
1817     return false;
1818   }
1819   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1820     Error(L, "unexpected token in directive");
1821     return false;
1822   }
1823 
1824   PPCTargetStreamer &TStreamer =
1825       *static_cast<PPCTargetStreamer *>(
1826            getParser().getStreamer().getTargetStreamer());
1827   TStreamer.emitAbiVersion(AbiVersion);
1828 
1829   return false;
1830 }
1831 
1832 /// ParseDirectiveLocalEntry
1833 ///  ::= .localentry symbol, expression
1834 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) {
1835   StringRef Name;
1836   if (getParser().parseIdentifier(Name)) {
1837     Error(L, "expected identifier in directive");
1838     return false;
1839   }
1840   MCSymbol *Sym = getContext().GetOrCreateSymbol(Name);
1841 
1842   if (getLexer().isNot(AsmToken::Comma)) {
1843     Error(L, "unexpected token in directive");
1844     return false;
1845   }
1846   Lex();
1847 
1848   const MCExpr *Expr;
1849   if (getParser().parseExpression(Expr)) {
1850     Error(L, "expected expression");
1851     return false;
1852   }
1853 
1854   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1855     Error(L, "unexpected token in directive");
1856     return false;
1857   }
1858 
1859   PPCTargetStreamer &TStreamer =
1860       *static_cast<PPCTargetStreamer *>(
1861            getParser().getStreamer().getTargetStreamer());
1862   TStreamer.emitLocalEntry(Sym, Expr);
1863 
1864   return false;
1865 }
1866 
1867 
1868 
1869 /// Force static initialization.
1870 extern "C" void LLVMInitializePowerPCAsmParser() {
1871   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1872   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1873   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1874 }
1875 
1876 #define GET_REGISTER_MATCHER
1877 #define GET_MATCHER_IMPLEMENTATION
1878 #include "PPCGenAsmMatcher.inc"
1879 
1880 // Define this matcher function after the auto-generated include so we
1881 // have the match class enum definitions.
1882 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp,
1883                                                   unsigned Kind) {
1884   // If the kind is a token for a literal immediate, check if our asm
1885   // operand matches. This is for InstAliases which have a fixed-value
1886   // immediate in the syntax.
1887   int64_t ImmVal;
1888   switch (Kind) {
1889     case MCK_0: ImmVal = 0; break;
1890     case MCK_1: ImmVal = 1; break;
1891     case MCK_2: ImmVal = 2; break;
1892     case MCK_3: ImmVal = 3; break;
1893     case MCK_4: ImmVal = 4; break;
1894     case MCK_5: ImmVal = 5; break;
1895     case MCK_6: ImmVal = 6; break;
1896     case MCK_7: ImmVal = 7; break;
1897     default: return Match_InvalidOperand;
1898   }
1899 
1900   PPCOperand &Op = static_cast<PPCOperand &>(AsmOp);
1901   if (Op.isImm() && Op.getImm() == ImmVal)
1902     return Match_Success;
1903 
1904   return Match_InvalidOperand;
1905 }
1906 
1907 const MCExpr *
1908 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1909                                   MCSymbolRefExpr::VariantKind Variant,
1910                                   MCContext &Ctx) {
1911   switch (Variant) {
1912   case MCSymbolRefExpr::VK_PPC_LO:
1913     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1914   case MCSymbolRefExpr::VK_PPC_HI:
1915     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1916   case MCSymbolRefExpr::VK_PPC_HA:
1917     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1918   case MCSymbolRefExpr::VK_PPC_HIGHER:
1919     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1920   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1921     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1922   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1923     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1924   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1925     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1926   default:
1927     return nullptr;
1928   }
1929 }
1930