1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "PPCTargetStreamer.h"
13 #include "llvm/ADT/STLExtras.h"
14 #include "llvm/ADT/SmallString.h"
15 #include "llvm/ADT/SmallVector.h"
16 #include "llvm/ADT/StringSwitch.h"
17 #include "llvm/ADT/Twine.h"
18 #include "llvm/MC/MCExpr.h"
19 #include "llvm/MC/MCInst.h"
20 #include "llvm/MC/MCInstrInfo.h"
21 #include "llvm/MC/MCParser/MCAsmLexer.h"
22 #include "llvm/MC/MCParser/MCAsmParser.h"
23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
24 #include "llvm/MC/MCRegisterInfo.h"
25 #include "llvm/MC/MCStreamer.h"
26 #include "llvm/MC/MCSubtargetInfo.h"
27 #include "llvm/MC/MCTargetAsmParser.h"
28 #include "llvm/Support/SourceMgr.h"
29 #include "llvm/Support/TargetRegistry.h"
30 #include "llvm/Support/raw_ostream.h"
31 
32 using namespace llvm;
33 
34 namespace {
35 
36 static unsigned RRegs[32] = {
37   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
38   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
39   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
40   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
41   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
42   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
43   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
44   PPC::R28, PPC::R29, PPC::R30, PPC::R31
45 };
46 static unsigned RRegsNoR0[32] = {
47   PPC::ZERO,
48             PPC::R1,  PPC::R2,  PPC::R3,
49   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
50   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
51   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
52   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
53   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
54   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
55   PPC::R28, PPC::R29, PPC::R30, PPC::R31
56 };
57 static unsigned XRegs[32] = {
58   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
59   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
60   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
61   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
62   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
63   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
64   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
65   PPC::X28, PPC::X29, PPC::X30, PPC::X31
66 };
67 static unsigned XRegsNoX0[32] = {
68   PPC::ZERO8,
69             PPC::X1,  PPC::X2,  PPC::X3,
70   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
71   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
72   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
73   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
74   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
75   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
76   PPC::X28, PPC::X29, PPC::X30, PPC::X31
77 };
78 static unsigned FRegs[32] = {
79   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
80   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
81   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
82   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
83   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
84   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
85   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
86   PPC::F28, PPC::F29, PPC::F30, PPC::F31
87 };
88 static unsigned VRegs[32] = {
89   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
90   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
91   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
92   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
93   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
94   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
95   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
96   PPC::V28, PPC::V29, PPC::V30, PPC::V31
97 };
98 static unsigned VSRegs[64] = {
99   PPC::VSL0,  PPC::VSL1,  PPC::VSL2,  PPC::VSL3,
100   PPC::VSL4,  PPC::VSL5,  PPC::VSL6,  PPC::VSL7,
101   PPC::VSL8,  PPC::VSL9,  PPC::VSL10, PPC::VSL11,
102   PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15,
103   PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19,
104   PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23,
105   PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27,
106   PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31,
107 
108   PPC::VSH0,  PPC::VSH1,  PPC::VSH2,  PPC::VSH3,
109   PPC::VSH4,  PPC::VSH5,  PPC::VSH6,  PPC::VSH7,
110   PPC::VSH8,  PPC::VSH9,  PPC::VSH10, PPC::VSH11,
111   PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15,
112   PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19,
113   PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23,
114   PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27,
115   PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31
116 };
117 static unsigned VSFRegs[64] = {
118   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
119   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
120   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
121   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
122   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
123   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
124   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
125   PPC::F28, PPC::F29, PPC::F30, PPC::F31,
126 
127   PPC::VF0,  PPC::VF1,  PPC::VF2,  PPC::VF3,
128   PPC::VF4,  PPC::VF5,  PPC::VF6,  PPC::VF7,
129   PPC::VF8,  PPC::VF9,  PPC::VF10, PPC::VF11,
130   PPC::VF12, PPC::VF13, PPC::VF14, PPC::VF15,
131   PPC::VF16, PPC::VF17, PPC::VF18, PPC::VF19,
132   PPC::VF20, PPC::VF21, PPC::VF22, PPC::VF23,
133   PPC::VF24, PPC::VF25, PPC::VF26, PPC::VF27,
134   PPC::VF28, PPC::VF29, PPC::VF30, PPC::VF31
135 };
136 static unsigned CRBITRegs[32] = {
137   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
138   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
139   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
140   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
141   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
142   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
143   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
144   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
145 };
146 static unsigned CRRegs[8] = {
147   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
148   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
149 };
150 
151 // Evaluate an expression containing condition register
152 // or condition register field symbols.  Returns positive
153 // value on success, or -1 on error.
154 static int64_t
155 EvaluateCRExpr(const MCExpr *E) {
156   switch (E->getKind()) {
157   case MCExpr::Target:
158     return -1;
159 
160   case MCExpr::Constant: {
161     int64_t Res = cast<MCConstantExpr>(E)->getValue();
162     return Res < 0 ? -1 : Res;
163   }
164 
165   case MCExpr::SymbolRef: {
166     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
167     StringRef Name = SRE->getSymbol().getName();
168 
169     if (Name == "lt") return 0;
170     if (Name == "gt") return 1;
171     if (Name == "eq") return 2;
172     if (Name == "so") return 3;
173     if (Name == "un") return 3;
174 
175     if (Name == "cr0") return 0;
176     if (Name == "cr1") return 1;
177     if (Name == "cr2") return 2;
178     if (Name == "cr3") return 3;
179     if (Name == "cr4") return 4;
180     if (Name == "cr5") return 5;
181     if (Name == "cr6") return 6;
182     if (Name == "cr7") return 7;
183 
184     return -1;
185   }
186 
187   case MCExpr::Unary:
188     return -1;
189 
190   case MCExpr::Binary: {
191     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
192     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
193     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
194     int64_t Res;
195 
196     if (LHSVal < 0 || RHSVal < 0)
197       return -1;
198 
199     switch (BE->getOpcode()) {
200     default: return -1;
201     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
202     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
203     }
204 
205     return Res < 0 ? -1 : Res;
206   }
207   }
208 
209   llvm_unreachable("Invalid expression kind!");
210 }
211 
212 struct PPCOperand;
213 
214 class PPCAsmParser : public MCTargetAsmParser {
215   MCSubtargetInfo &STI;
216   MCAsmParser &Parser;
217   const MCInstrInfo &MII;
218   bool IsPPC64;
219   bool IsDarwin;
220 
221   MCAsmParser &getParser() const { return Parser; }
222   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
223 
224   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
225   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
226 
227   bool isPPC64() const { return IsPPC64; }
228   bool isDarwin() const { return IsDarwin; }
229 
230   bool MatchRegisterName(const AsmToken &Tok,
231                          unsigned &RegNo, int64_t &IntVal);
232 
233   bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override;
234 
235   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
236                                         PPCMCExpr::VariantKind &Variant);
237   const MCExpr *FixupVariantKind(const MCExpr *E);
238   bool ParseExpression(const MCExpr *&EVal);
239   bool ParseDarwinExpression(const MCExpr *&EVal);
240 
241   bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
242 
243   bool ParseDirectiveWord(unsigned Size, SMLoc L);
244   bool ParseDirectiveTC(unsigned Size, SMLoc L);
245   bool ParseDirectiveMachine(SMLoc L);
246   bool ParseDarwinDirectiveMachine(SMLoc L);
247 
248   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
249                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
250                                MCStreamer &Out, unsigned &ErrorInfo,
251                                bool MatchingInlineAsm) override;
252 
253   void ProcessInstruction(MCInst &Inst,
254                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
255 
256   /// @name Auto-generated Match Functions
257   /// {
258 
259 #define GET_ASSEMBLER_HEADER
260 #include "PPCGenAsmMatcher.inc"
261 
262   /// }
263 
264 
265 public:
266   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser,
267                const MCInstrInfo &_MII,
268                const MCTargetOptions &Options)
269       : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) {
270     // Check for 64-bit vs. 32-bit pointer mode.
271     Triple TheTriple(STI.getTargetTriple());
272     IsPPC64 = (TheTriple.getArch() == Triple::ppc64 ||
273                TheTriple.getArch() == Triple::ppc64le);
274     IsDarwin = TheTriple.isMacOSX();
275     // Initialize the set of available features.
276     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
277   }
278 
279   bool ParseInstruction(ParseInstructionInfo &Info,
280                         StringRef Name, SMLoc NameLoc,
281                         SmallVectorImpl<MCParsedAsmOperand*> &Operands) override;
282 
283   bool ParseDirective(AsmToken DirectiveID) override;
284 
285   unsigned validateTargetOperandClass(MCParsedAsmOperand *Op,
286                                       unsigned Kind) override;
287 
288   const MCExpr *applyModifierToExpr(const MCExpr *E,
289                                     MCSymbolRefExpr::VariantKind,
290                                     MCContext &Ctx) override;
291 };
292 
293 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
294 /// instruction.
295 struct PPCOperand : public MCParsedAsmOperand {
296   enum KindTy {
297     Token,
298     Immediate,
299     Expression,
300     TLSRegister
301   } Kind;
302 
303   SMLoc StartLoc, EndLoc;
304   bool IsPPC64;
305 
306   struct TokOp {
307     const char *Data;
308     unsigned Length;
309   };
310 
311   struct ImmOp {
312     int64_t Val;
313   };
314 
315   struct ExprOp {
316     const MCExpr *Val;
317     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
318   };
319 
320   struct TLSRegOp {
321     const MCSymbolRefExpr *Sym;
322   };
323 
324   union {
325     struct TokOp Tok;
326     struct ImmOp Imm;
327     struct ExprOp Expr;
328     struct TLSRegOp TLSReg;
329   };
330 
331   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
332 public:
333   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
334     Kind = o.Kind;
335     StartLoc = o.StartLoc;
336     EndLoc = o.EndLoc;
337     IsPPC64 = o.IsPPC64;
338     switch (Kind) {
339     case Token:
340       Tok = o.Tok;
341       break;
342     case Immediate:
343       Imm = o.Imm;
344       break;
345     case Expression:
346       Expr = o.Expr;
347       break;
348     case TLSRegister:
349       TLSReg = o.TLSReg;
350       break;
351     }
352   }
353 
354   /// getStartLoc - Get the location of the first token of this operand.
355   SMLoc getStartLoc() const override { return StartLoc; }
356 
357   /// getEndLoc - Get the location of the last token of this operand.
358   SMLoc getEndLoc() const override { return EndLoc; }
359 
360   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
361   bool isPPC64() const { return IsPPC64; }
362 
363   int64_t getImm() const {
364     assert(Kind == Immediate && "Invalid access!");
365     return Imm.Val;
366   }
367 
368   const MCExpr *getExpr() const {
369     assert(Kind == Expression && "Invalid access!");
370     return Expr.Val;
371   }
372 
373   int64_t getExprCRVal() const {
374     assert(Kind == Expression && "Invalid access!");
375     return Expr.CRVal;
376   }
377 
378   const MCExpr *getTLSReg() const {
379     assert(Kind == TLSRegister && "Invalid access!");
380     return TLSReg.Sym;
381   }
382 
383   unsigned getReg() const override {
384     assert(isRegNumber() && "Invalid access!");
385     return (unsigned) Imm.Val;
386   }
387 
388   unsigned getVSReg() const {
389     assert(isVSRegNumber() && "Invalid access!");
390     return (unsigned) Imm.Val;
391   }
392 
393   unsigned getCCReg() const {
394     assert(isCCRegNumber() && "Invalid access!");
395     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
396   }
397 
398   unsigned getCRBit() const {
399     assert(isCRBitNumber() && "Invalid access!");
400     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
401   }
402 
403   unsigned getCRBitMask() const {
404     assert(isCRBitMask() && "Invalid access!");
405     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
406   }
407 
408   bool isToken() const override { return Kind == Token; }
409   bool isImm() const override { return Kind == Immediate || Kind == Expression; }
410   bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); }
411   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
412   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
413   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
414   bool isU16Imm() const { return Kind == Expression ||
415                                  (Kind == Immediate && isUInt<16>(getImm())); }
416   bool isS16Imm() const { return Kind == Expression ||
417                                  (Kind == Immediate && isInt<16>(getImm())); }
418   bool isS16ImmX4() const { return Kind == Expression ||
419                                    (Kind == Immediate && isInt<16>(getImm()) &&
420                                     (getImm() & 3) == 0); }
421   bool isS17Imm() const { return Kind == Expression ||
422                                  (Kind == Immediate && isInt<17>(getImm())); }
423   bool isTLSReg() const { return Kind == TLSRegister; }
424   bool isDirectBr() const { return Kind == Expression ||
425                                    (Kind == Immediate && isInt<26>(getImm()) &&
426                                     (getImm() & 3) == 0); }
427   bool isCondBr() const { return Kind == Expression ||
428                                  (Kind == Immediate && isInt<16>(getImm()) &&
429                                   (getImm() & 3) == 0); }
430   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
431   bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); }
432   bool isCCRegNumber() const { return (Kind == Expression
433                                        && isUInt<3>(getExprCRVal())) ||
434                                       (Kind == Immediate
435                                        && isUInt<3>(getImm())); }
436   bool isCRBitNumber() const { return (Kind == Expression
437                                        && isUInt<5>(getExprCRVal())) ||
438                                       (Kind == Immediate
439                                        && isUInt<5>(getImm())); }
440   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
441                                     isPowerOf2_32(getImm()); }
442   bool isMem() const override { return false; }
443   bool isReg() const override { return false; }
444 
445   void addRegOperands(MCInst &Inst, unsigned N) const {
446     llvm_unreachable("addRegOperands");
447   }
448 
449   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
450     assert(N == 1 && "Invalid number of operands!");
451     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
452   }
453 
454   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
455     assert(N == 1 && "Invalid number of operands!");
456     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
457   }
458 
459   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
460     assert(N == 1 && "Invalid number of operands!");
461     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
462   }
463 
464   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
465     assert(N == 1 && "Invalid number of operands!");
466     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
467   }
468 
469   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
470     if (isPPC64())
471       addRegG8RCOperands(Inst, N);
472     else
473       addRegGPRCOperands(Inst, N);
474   }
475 
476   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
477     if (isPPC64())
478       addRegG8RCNoX0Operands(Inst, N);
479     else
480       addRegGPRCNoR0Operands(Inst, N);
481   }
482 
483   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
484     assert(N == 1 && "Invalid number of operands!");
485     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
486   }
487 
488   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
489     assert(N == 1 && "Invalid number of operands!");
490     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
491   }
492 
493   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
494     assert(N == 1 && "Invalid number of operands!");
495     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
496   }
497 
498   void addRegVSRCOperands(MCInst &Inst, unsigned N) const {
499     assert(N == 1 && "Invalid number of operands!");
500     Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()]));
501   }
502 
503   void addRegVSFRCOperands(MCInst &Inst, unsigned N) const {
504     assert(N == 1 && "Invalid number of operands!");
505     Inst.addOperand(MCOperand::CreateReg(VSFRegs[getVSReg()]));
506   }
507 
508   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
509     assert(N == 1 && "Invalid number of operands!");
510     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
511   }
512 
513   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
514     assert(N == 1 && "Invalid number of operands!");
515     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
516   }
517 
518   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
519     assert(N == 1 && "Invalid number of operands!");
520     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
521   }
522 
523   void addImmOperands(MCInst &Inst, unsigned N) const {
524     assert(N == 1 && "Invalid number of operands!");
525     if (Kind == Immediate)
526       Inst.addOperand(MCOperand::CreateImm(getImm()));
527     else
528       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
529   }
530 
531   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
532     assert(N == 1 && "Invalid number of operands!");
533     if (Kind == Immediate)
534       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
535     else
536       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
537   }
538 
539   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
540     assert(N == 1 && "Invalid number of operands!");
541     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
542   }
543 
544   StringRef getToken() const {
545     assert(Kind == Token && "Invalid access!");
546     return StringRef(Tok.Data, Tok.Length);
547   }
548 
549   void print(raw_ostream &OS) const override;
550 
551   static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
552     PPCOperand *Op = new PPCOperand(Token);
553     Op->Tok.Data = Str.data();
554     Op->Tok.Length = Str.size();
555     Op->StartLoc = S;
556     Op->EndLoc = S;
557     Op->IsPPC64 = IsPPC64;
558     return Op;
559   }
560 
561   static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S,
562                                                bool IsPPC64) {
563     // Allocate extra memory for the string and copy it.
564     void *Mem = ::operator new(sizeof(PPCOperand) + Str.size());
565     PPCOperand *Op = new (Mem) PPCOperand(Token);
566     Op->Tok.Data = (const char *)(Op + 1);
567     Op->Tok.Length = Str.size();
568     std::memcpy((char *)(Op + 1), Str.data(), Str.size());
569     Op->StartLoc = S;
570     Op->EndLoc = S;
571     Op->IsPPC64 = IsPPC64;
572     return Op;
573   }
574 
575   static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
576     PPCOperand *Op = new PPCOperand(Immediate);
577     Op->Imm.Val = Val;
578     Op->StartLoc = S;
579     Op->EndLoc = E;
580     Op->IsPPC64 = IsPPC64;
581     return Op;
582   }
583 
584   static PPCOperand *CreateExpr(const MCExpr *Val,
585                                 SMLoc S, SMLoc E, bool IsPPC64) {
586     PPCOperand *Op = new PPCOperand(Expression);
587     Op->Expr.Val = Val;
588     Op->Expr.CRVal = EvaluateCRExpr(Val);
589     Op->StartLoc = S;
590     Op->EndLoc = E;
591     Op->IsPPC64 = IsPPC64;
592     return Op;
593   }
594 
595   static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
596                                   SMLoc S, SMLoc E, bool IsPPC64) {
597     PPCOperand *Op = new PPCOperand(TLSRegister);
598     Op->TLSReg.Sym = Sym;
599     Op->StartLoc = S;
600     Op->EndLoc = E;
601     Op->IsPPC64 = IsPPC64;
602     return Op;
603   }
604 
605   static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
606                                       SMLoc S, SMLoc E, bool IsPPC64) {
607     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
608       return CreateImm(CE->getValue(), S, E, IsPPC64);
609 
610     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
611       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
612         return CreateTLSReg(SRE, S, E, IsPPC64);
613 
614     return CreateExpr(Val, S, E, IsPPC64);
615   }
616 };
617 
618 } // end anonymous namespace.
619 
620 void PPCOperand::print(raw_ostream &OS) const {
621   switch (Kind) {
622   case Token:
623     OS << "'" << getToken() << "'";
624     break;
625   case Immediate:
626     OS << getImm();
627     break;
628   case Expression:
629     getExpr()->print(OS);
630     break;
631   case TLSRegister:
632     getTLSReg()->print(OS);
633     break;
634   }
635 }
636 
637 
638 void PPCAsmParser::
639 ProcessInstruction(MCInst &Inst,
640                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
641   int Opcode = Inst.getOpcode();
642   switch (Opcode) {
643   case PPC::LAx: {
644     MCInst TmpInst;
645     TmpInst.setOpcode(PPC::LA);
646     TmpInst.addOperand(Inst.getOperand(0));
647     TmpInst.addOperand(Inst.getOperand(2));
648     TmpInst.addOperand(Inst.getOperand(1));
649     Inst = TmpInst;
650     break;
651   }
652   case PPC::SUBI: {
653     MCInst TmpInst;
654     int64_t N = Inst.getOperand(2).getImm();
655     TmpInst.setOpcode(PPC::ADDI);
656     TmpInst.addOperand(Inst.getOperand(0));
657     TmpInst.addOperand(Inst.getOperand(1));
658     TmpInst.addOperand(MCOperand::CreateImm(-N));
659     Inst = TmpInst;
660     break;
661   }
662   case PPC::SUBIS: {
663     MCInst TmpInst;
664     int64_t N = Inst.getOperand(2).getImm();
665     TmpInst.setOpcode(PPC::ADDIS);
666     TmpInst.addOperand(Inst.getOperand(0));
667     TmpInst.addOperand(Inst.getOperand(1));
668     TmpInst.addOperand(MCOperand::CreateImm(-N));
669     Inst = TmpInst;
670     break;
671   }
672   case PPC::SUBIC: {
673     MCInst TmpInst;
674     int64_t N = Inst.getOperand(2).getImm();
675     TmpInst.setOpcode(PPC::ADDIC);
676     TmpInst.addOperand(Inst.getOperand(0));
677     TmpInst.addOperand(Inst.getOperand(1));
678     TmpInst.addOperand(MCOperand::CreateImm(-N));
679     Inst = TmpInst;
680     break;
681   }
682   case PPC::SUBICo: {
683     MCInst TmpInst;
684     int64_t N = Inst.getOperand(2).getImm();
685     TmpInst.setOpcode(PPC::ADDICo);
686     TmpInst.addOperand(Inst.getOperand(0));
687     TmpInst.addOperand(Inst.getOperand(1));
688     TmpInst.addOperand(MCOperand::CreateImm(-N));
689     Inst = TmpInst;
690     break;
691   }
692   case PPC::EXTLWI:
693   case PPC::EXTLWIo: {
694     MCInst TmpInst;
695     int64_t N = Inst.getOperand(2).getImm();
696     int64_t B = Inst.getOperand(3).getImm();
697     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
698     TmpInst.addOperand(Inst.getOperand(0));
699     TmpInst.addOperand(Inst.getOperand(1));
700     TmpInst.addOperand(MCOperand::CreateImm(B));
701     TmpInst.addOperand(MCOperand::CreateImm(0));
702     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
703     Inst = TmpInst;
704     break;
705   }
706   case PPC::EXTRWI:
707   case PPC::EXTRWIo: {
708     MCInst TmpInst;
709     int64_t N = Inst.getOperand(2).getImm();
710     int64_t B = Inst.getOperand(3).getImm();
711     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
712     TmpInst.addOperand(Inst.getOperand(0));
713     TmpInst.addOperand(Inst.getOperand(1));
714     TmpInst.addOperand(MCOperand::CreateImm(B + N));
715     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
716     TmpInst.addOperand(MCOperand::CreateImm(31));
717     Inst = TmpInst;
718     break;
719   }
720   case PPC::INSLWI:
721   case PPC::INSLWIo: {
722     MCInst TmpInst;
723     int64_t N = Inst.getOperand(2).getImm();
724     int64_t B = Inst.getOperand(3).getImm();
725     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
726     TmpInst.addOperand(Inst.getOperand(0));
727     TmpInst.addOperand(Inst.getOperand(0));
728     TmpInst.addOperand(Inst.getOperand(1));
729     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
730     TmpInst.addOperand(MCOperand::CreateImm(B));
731     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
732     Inst = TmpInst;
733     break;
734   }
735   case PPC::INSRWI:
736   case PPC::INSRWIo: {
737     MCInst TmpInst;
738     int64_t N = Inst.getOperand(2).getImm();
739     int64_t B = Inst.getOperand(3).getImm();
740     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
741     TmpInst.addOperand(Inst.getOperand(0));
742     TmpInst.addOperand(Inst.getOperand(0));
743     TmpInst.addOperand(Inst.getOperand(1));
744     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
745     TmpInst.addOperand(MCOperand::CreateImm(B));
746     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
747     Inst = TmpInst;
748     break;
749   }
750   case PPC::ROTRWI:
751   case PPC::ROTRWIo: {
752     MCInst TmpInst;
753     int64_t N = Inst.getOperand(2).getImm();
754     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
755     TmpInst.addOperand(Inst.getOperand(0));
756     TmpInst.addOperand(Inst.getOperand(1));
757     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
758     TmpInst.addOperand(MCOperand::CreateImm(0));
759     TmpInst.addOperand(MCOperand::CreateImm(31));
760     Inst = TmpInst;
761     break;
762   }
763   case PPC::SLWI:
764   case PPC::SLWIo: {
765     MCInst TmpInst;
766     int64_t N = Inst.getOperand(2).getImm();
767     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
768     TmpInst.addOperand(Inst.getOperand(0));
769     TmpInst.addOperand(Inst.getOperand(1));
770     TmpInst.addOperand(MCOperand::CreateImm(N));
771     TmpInst.addOperand(MCOperand::CreateImm(0));
772     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
773     Inst = TmpInst;
774     break;
775   }
776   case PPC::SRWI:
777   case PPC::SRWIo: {
778     MCInst TmpInst;
779     int64_t N = Inst.getOperand(2).getImm();
780     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
781     TmpInst.addOperand(Inst.getOperand(0));
782     TmpInst.addOperand(Inst.getOperand(1));
783     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
784     TmpInst.addOperand(MCOperand::CreateImm(N));
785     TmpInst.addOperand(MCOperand::CreateImm(31));
786     Inst = TmpInst;
787     break;
788   }
789   case PPC::CLRRWI:
790   case PPC::CLRRWIo: {
791     MCInst TmpInst;
792     int64_t N = Inst.getOperand(2).getImm();
793     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
794     TmpInst.addOperand(Inst.getOperand(0));
795     TmpInst.addOperand(Inst.getOperand(1));
796     TmpInst.addOperand(MCOperand::CreateImm(0));
797     TmpInst.addOperand(MCOperand::CreateImm(0));
798     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
799     Inst = TmpInst;
800     break;
801   }
802   case PPC::CLRLSLWI:
803   case PPC::CLRLSLWIo: {
804     MCInst TmpInst;
805     int64_t B = Inst.getOperand(2).getImm();
806     int64_t N = Inst.getOperand(3).getImm();
807     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
808     TmpInst.addOperand(Inst.getOperand(0));
809     TmpInst.addOperand(Inst.getOperand(1));
810     TmpInst.addOperand(MCOperand::CreateImm(N));
811     TmpInst.addOperand(MCOperand::CreateImm(B - N));
812     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
813     Inst = TmpInst;
814     break;
815   }
816   case PPC::EXTLDI:
817   case PPC::EXTLDIo: {
818     MCInst TmpInst;
819     int64_t N = Inst.getOperand(2).getImm();
820     int64_t B = Inst.getOperand(3).getImm();
821     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
822     TmpInst.addOperand(Inst.getOperand(0));
823     TmpInst.addOperand(Inst.getOperand(1));
824     TmpInst.addOperand(MCOperand::CreateImm(B));
825     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
826     Inst = TmpInst;
827     break;
828   }
829   case PPC::EXTRDI:
830   case PPC::EXTRDIo: {
831     MCInst TmpInst;
832     int64_t N = Inst.getOperand(2).getImm();
833     int64_t B = Inst.getOperand(3).getImm();
834     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
835     TmpInst.addOperand(Inst.getOperand(0));
836     TmpInst.addOperand(Inst.getOperand(1));
837     TmpInst.addOperand(MCOperand::CreateImm(B + N));
838     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
839     Inst = TmpInst;
840     break;
841   }
842   case PPC::INSRDI:
843   case PPC::INSRDIo: {
844     MCInst TmpInst;
845     int64_t N = Inst.getOperand(2).getImm();
846     int64_t B = Inst.getOperand(3).getImm();
847     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
848     TmpInst.addOperand(Inst.getOperand(0));
849     TmpInst.addOperand(Inst.getOperand(0));
850     TmpInst.addOperand(Inst.getOperand(1));
851     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
852     TmpInst.addOperand(MCOperand::CreateImm(B));
853     Inst = TmpInst;
854     break;
855   }
856   case PPC::ROTRDI:
857   case PPC::ROTRDIo: {
858     MCInst TmpInst;
859     int64_t N = Inst.getOperand(2).getImm();
860     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
861     TmpInst.addOperand(Inst.getOperand(0));
862     TmpInst.addOperand(Inst.getOperand(1));
863     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
864     TmpInst.addOperand(MCOperand::CreateImm(0));
865     Inst = TmpInst;
866     break;
867   }
868   case PPC::SLDI:
869   case PPC::SLDIo: {
870     MCInst TmpInst;
871     int64_t N = Inst.getOperand(2).getImm();
872     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
873     TmpInst.addOperand(Inst.getOperand(0));
874     TmpInst.addOperand(Inst.getOperand(1));
875     TmpInst.addOperand(MCOperand::CreateImm(N));
876     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
877     Inst = TmpInst;
878     break;
879   }
880   case PPC::SRDI:
881   case PPC::SRDIo: {
882     MCInst TmpInst;
883     int64_t N = Inst.getOperand(2).getImm();
884     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
885     TmpInst.addOperand(Inst.getOperand(0));
886     TmpInst.addOperand(Inst.getOperand(1));
887     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
888     TmpInst.addOperand(MCOperand::CreateImm(N));
889     Inst = TmpInst;
890     break;
891   }
892   case PPC::CLRRDI:
893   case PPC::CLRRDIo: {
894     MCInst TmpInst;
895     int64_t N = Inst.getOperand(2).getImm();
896     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
897     TmpInst.addOperand(Inst.getOperand(0));
898     TmpInst.addOperand(Inst.getOperand(1));
899     TmpInst.addOperand(MCOperand::CreateImm(0));
900     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
901     Inst = TmpInst;
902     break;
903   }
904   case PPC::CLRLSLDI:
905   case PPC::CLRLSLDIo: {
906     MCInst TmpInst;
907     int64_t B = Inst.getOperand(2).getImm();
908     int64_t N = Inst.getOperand(3).getImm();
909     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
910     TmpInst.addOperand(Inst.getOperand(0));
911     TmpInst.addOperand(Inst.getOperand(1));
912     TmpInst.addOperand(MCOperand::CreateImm(N));
913     TmpInst.addOperand(MCOperand::CreateImm(B - N));
914     Inst = TmpInst;
915     break;
916   }
917   }
918 }
919 
920 bool PPCAsmParser::
921 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
922                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
923                         MCStreamer &Out, unsigned &ErrorInfo,
924                         bool MatchingInlineAsm) {
925   MCInst Inst;
926 
927   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
928   default: break;
929   case Match_Success:
930     // Post-process instructions (typically extended mnemonics)
931     ProcessInstruction(Inst, Operands);
932     Inst.setLoc(IDLoc);
933     Out.EmitInstruction(Inst, STI);
934     return false;
935   case Match_MissingFeature:
936     return Error(IDLoc, "instruction use requires an option to be enabled");
937   case Match_MnemonicFail:
938       return Error(IDLoc, "unrecognized instruction mnemonic");
939   case Match_InvalidOperand: {
940     SMLoc ErrorLoc = IDLoc;
941     if (ErrorInfo != ~0U) {
942       if (ErrorInfo >= Operands.size())
943         return Error(IDLoc, "too few operands for instruction");
944 
945       ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
946       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
947     }
948 
949     return Error(ErrorLoc, "invalid operand for instruction");
950   }
951   }
952 
953   llvm_unreachable("Implement any new match types added!");
954 }
955 
956 bool PPCAsmParser::
957 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
958   if (Tok.is(AsmToken::Identifier)) {
959     StringRef Name = Tok.getString();
960 
961     if (Name.equals_lower("lr")) {
962       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
963       IntVal = 8;
964       return false;
965     } else if (Name.equals_lower("ctr")) {
966       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
967       IntVal = 9;
968       return false;
969     } else if (Name.equals_lower("vrsave")) {
970       RegNo = PPC::VRSAVE;
971       IntVal = 256;
972       return false;
973     } else if (Name.startswith_lower("r") &&
974                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
975       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
976       return false;
977     } else if (Name.startswith_lower("f") &&
978                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
979       RegNo = FRegs[IntVal];
980       return false;
981     } else if (Name.startswith_lower("v") &&
982                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
983       RegNo = VRegs[IntVal];
984       return false;
985     } else if (Name.startswith_lower("cr") &&
986                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
987       RegNo = CRRegs[IntVal];
988       return false;
989     }
990   }
991 
992   return true;
993 }
994 
995 bool PPCAsmParser::
996 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
997   const AsmToken &Tok = Parser.getTok();
998   StartLoc = Tok.getLoc();
999   EndLoc = Tok.getEndLoc();
1000   RegNo = 0;
1001   int64_t IntVal;
1002 
1003   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
1004     Parser.Lex(); // Eat identifier token.
1005     return false;
1006   }
1007 
1008   return Error(StartLoc, "invalid register name");
1009 }
1010 
1011 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
1012 /// the expression and check for VK_PPC_LO/HI/HA
1013 /// symbol variants.  If all symbols with modifier use the same
1014 /// variant, return the corresponding PPCMCExpr::VariantKind,
1015 /// and a modified expression using the default symbol variant.
1016 /// Otherwise, return NULL.
1017 const MCExpr *PPCAsmParser::
1018 ExtractModifierFromExpr(const MCExpr *E,
1019                         PPCMCExpr::VariantKind &Variant) {
1020   MCContext &Context = getParser().getContext();
1021   Variant = PPCMCExpr::VK_PPC_None;
1022 
1023   switch (E->getKind()) {
1024   case MCExpr::Target:
1025   case MCExpr::Constant:
1026     return nullptr;
1027 
1028   case MCExpr::SymbolRef: {
1029     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1030 
1031     switch (SRE->getKind()) {
1032     case MCSymbolRefExpr::VK_PPC_LO:
1033       Variant = PPCMCExpr::VK_PPC_LO;
1034       break;
1035     case MCSymbolRefExpr::VK_PPC_HI:
1036       Variant = PPCMCExpr::VK_PPC_HI;
1037       break;
1038     case MCSymbolRefExpr::VK_PPC_HA:
1039       Variant = PPCMCExpr::VK_PPC_HA;
1040       break;
1041     case MCSymbolRefExpr::VK_PPC_HIGHER:
1042       Variant = PPCMCExpr::VK_PPC_HIGHER;
1043       break;
1044     case MCSymbolRefExpr::VK_PPC_HIGHERA:
1045       Variant = PPCMCExpr::VK_PPC_HIGHERA;
1046       break;
1047     case MCSymbolRefExpr::VK_PPC_HIGHEST:
1048       Variant = PPCMCExpr::VK_PPC_HIGHEST;
1049       break;
1050     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1051       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
1052       break;
1053     default:
1054       return nullptr;
1055     }
1056 
1057     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
1058   }
1059 
1060   case MCExpr::Unary: {
1061     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1062     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
1063     if (!Sub)
1064       return nullptr;
1065     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1066   }
1067 
1068   case MCExpr::Binary: {
1069     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1070     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
1071     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
1072     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
1073 
1074     if (!LHS && !RHS)
1075       return nullptr;
1076 
1077     if (!LHS) LHS = BE->getLHS();
1078     if (!RHS) RHS = BE->getRHS();
1079 
1080     if (LHSVariant == PPCMCExpr::VK_PPC_None)
1081       Variant = RHSVariant;
1082     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
1083       Variant = LHSVariant;
1084     else if (LHSVariant == RHSVariant)
1085       Variant = LHSVariant;
1086     else
1087       return nullptr;
1088 
1089     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1090   }
1091   }
1092 
1093   llvm_unreachable("Invalid expression kind!");
1094 }
1095 
1096 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace
1097 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD.  This is necessary to avoid having
1098 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT.
1099 /// FIXME: This is a hack.
1100 const MCExpr *PPCAsmParser::
1101 FixupVariantKind(const MCExpr *E) {
1102   MCContext &Context = getParser().getContext();
1103 
1104   switch (E->getKind()) {
1105   case MCExpr::Target:
1106   case MCExpr::Constant:
1107     return E;
1108 
1109   case MCExpr::SymbolRef: {
1110     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
1111     MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None;
1112 
1113     switch (SRE->getKind()) {
1114     case MCSymbolRefExpr::VK_TLSGD:
1115       Variant = MCSymbolRefExpr::VK_PPC_TLSGD;
1116       break;
1117     case MCSymbolRefExpr::VK_TLSLD:
1118       Variant = MCSymbolRefExpr::VK_PPC_TLSLD;
1119       break;
1120     default:
1121       return E;
1122     }
1123     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context);
1124   }
1125 
1126   case MCExpr::Unary: {
1127     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
1128     const MCExpr *Sub = FixupVariantKind(UE->getSubExpr());
1129     if (Sub == UE->getSubExpr())
1130       return E;
1131     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
1132   }
1133 
1134   case MCExpr::Binary: {
1135     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
1136     const MCExpr *LHS = FixupVariantKind(BE->getLHS());
1137     const MCExpr *RHS = FixupVariantKind(BE->getRHS());
1138     if (LHS == BE->getLHS() && RHS == BE->getRHS())
1139       return E;
1140     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1141   }
1142   }
1143 
1144   llvm_unreachable("Invalid expression kind!");
1145 }
1146 
1147 /// ParseExpression.  This differs from the default "parseExpression" in that
1148 /// it handles modifiers.
1149 bool PPCAsmParser::
1150 ParseExpression(const MCExpr *&EVal) {
1151 
1152   if (isDarwin())
1153     return ParseDarwinExpression(EVal);
1154 
1155   // (ELF Platforms)
1156   // Handle \code @l/@ha \endcode
1157   if (getParser().parseExpression(EVal))
1158     return true;
1159 
1160   EVal = FixupVariantKind(EVal);
1161 
1162   PPCMCExpr::VariantKind Variant;
1163   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1164   if (E)
1165     EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext());
1166 
1167   return false;
1168 }
1169 
1170 /// ParseDarwinExpression.  (MachO Platforms)
1171 /// This differs from the default "parseExpression" in that it handles detection
1172 /// of the \code hi16(), ha16() and lo16() \endcode modifiers.  At present,
1173 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO
1174 /// syntax form so it is done here.  TODO: Determine if there is merit in arranging
1175 /// for this to be done at a higher level.
1176 bool PPCAsmParser::
1177 ParseDarwinExpression(const MCExpr *&EVal) {
1178   PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None;
1179   switch (getLexer().getKind()) {
1180   default:
1181     break;
1182   case AsmToken::Identifier:
1183     // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus
1184     // something starting with any other char should be part of the
1185     // asm syntax.  If handwritten asm includes an identifier like lo16,
1186     // then all bets are off - but no-one would do that, right?
1187     StringRef poss = Parser.getTok().getString();
1188     if (poss.equals_lower("lo16")) {
1189       Variant = PPCMCExpr::VK_PPC_LO;
1190     } else if (poss.equals_lower("hi16")) {
1191       Variant = PPCMCExpr::VK_PPC_HI;
1192     } else if (poss.equals_lower("ha16")) {
1193       Variant = PPCMCExpr::VK_PPC_HA;
1194     }
1195     if (Variant != PPCMCExpr::VK_PPC_None) {
1196       Parser.Lex(); // Eat the xx16
1197       if (getLexer().isNot(AsmToken::LParen))
1198         return Error(Parser.getTok().getLoc(), "expected '('");
1199       Parser.Lex(); // Eat the '('
1200     }
1201     break;
1202   }
1203 
1204   if (getParser().parseExpression(EVal))
1205     return true;
1206 
1207   if (Variant != PPCMCExpr::VK_PPC_None) {
1208     if (getLexer().isNot(AsmToken::RParen))
1209       return Error(Parser.getTok().getLoc(), "expected ')'");
1210     Parser.Lex(); // Eat the ')'
1211     EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext());
1212   }
1213   return false;
1214 }
1215 
1216 /// ParseOperand
1217 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and
1218 /// rNN for MachO.
1219 bool PPCAsmParser::
1220 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1221   SMLoc S = Parser.getTok().getLoc();
1222   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1223   const MCExpr *EVal;
1224   PPCOperand *Op;
1225 
1226   // Attempt to parse the next token as an immediate
1227   switch (getLexer().getKind()) {
1228   // Special handling for register names.  These are interpreted
1229   // as immediates corresponding to the register number.
1230   case AsmToken::Percent:
1231     Parser.Lex(); // Eat the '%'.
1232     unsigned RegNo;
1233     int64_t IntVal;
1234     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1235       Parser.Lex(); // Eat the identifier token.
1236       Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1237       Operands.push_back(Op);
1238       return false;
1239     }
1240     return Error(S, "invalid register name");
1241 
1242   case AsmToken::Identifier:
1243     // Note that non-register-name identifiers from the compiler will begin
1244     // with '_', 'L'/'l' or '"'.  Of course, handwritten asm could include
1245     // identifiers like r31foo - so we fall through in the event that parsing
1246     // a register name fails.
1247     if (isDarwin()) {
1248       unsigned RegNo;
1249       int64_t IntVal;
1250       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1251         Parser.Lex(); // Eat the identifier token.
1252         Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1253         Operands.push_back(Op);
1254         return false;
1255       }
1256     }
1257   // Fall-through to process non-register-name identifiers as expression.
1258   // All other expressions
1259   case AsmToken::LParen:
1260   case AsmToken::Plus:
1261   case AsmToken::Minus:
1262   case AsmToken::Integer:
1263   case AsmToken::Dot:
1264   case AsmToken::Dollar:
1265   case AsmToken::Exclaim:
1266   case AsmToken::Tilde:
1267     if (!ParseExpression(EVal))
1268       break;
1269     /* fall through */
1270   default:
1271     return Error(S, "unknown operand");
1272   }
1273 
1274   // Push the parsed operand into the list of operands
1275   Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1276   Operands.push_back(Op);
1277 
1278   // Check whether this is a TLS call expression
1279   bool TLSCall = false;
1280   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1281     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1282 
1283   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1284     const MCExpr *TLSSym;
1285 
1286     Parser.Lex(); // Eat the '('.
1287     S = Parser.getTok().getLoc();
1288     if (ParseExpression(TLSSym))
1289       return Error(S, "invalid TLS call expression");
1290     if (getLexer().isNot(AsmToken::RParen))
1291       return Error(Parser.getTok().getLoc(), "missing ')'");
1292     E = Parser.getTok().getLoc();
1293     Parser.Lex(); // Eat the ')'.
1294 
1295     Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1296     Operands.push_back(Op);
1297   }
1298 
1299   // Otherwise, check for D-form memory operands
1300   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1301     Parser.Lex(); // Eat the '('.
1302     S = Parser.getTok().getLoc();
1303 
1304     int64_t IntVal;
1305     switch (getLexer().getKind()) {
1306     case AsmToken::Percent:
1307       Parser.Lex(); // Eat the '%'.
1308       unsigned RegNo;
1309       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1310         return Error(S, "invalid register name");
1311       Parser.Lex(); // Eat the identifier token.
1312       break;
1313 
1314     case AsmToken::Integer:
1315       if (!isDarwin()) {
1316         if (getParser().parseAbsoluteExpression(IntVal) ||
1317           IntVal < 0 || IntVal > 31)
1318         return Error(S, "invalid register number");
1319       } else {
1320         return Error(S, "unexpected integer value");
1321       }
1322       break;
1323 
1324    case AsmToken::Identifier:
1325     if (isDarwin()) {
1326       unsigned RegNo;
1327       if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1328         Parser.Lex(); // Eat the identifier token.
1329         break;
1330       }
1331     }
1332     // Fall-through..
1333 
1334     default:
1335       return Error(S, "invalid memory operand");
1336     }
1337 
1338     if (getLexer().isNot(AsmToken::RParen))
1339       return Error(Parser.getTok().getLoc(), "missing ')'");
1340     E = Parser.getTok().getLoc();
1341     Parser.Lex(); // Eat the ')'.
1342 
1343     Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1344     Operands.push_back(Op);
1345   }
1346 
1347   return false;
1348 }
1349 
1350 /// Parse an instruction mnemonic followed by its operands.
1351 bool PPCAsmParser::
1352 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1353                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1354   // The first operand is the token for the instruction name.
1355   // If the next character is a '+' or '-', we need to add it to the
1356   // instruction name, to match what TableGen is doing.
1357   std::string NewOpcode;
1358   if (getLexer().is(AsmToken::Plus)) {
1359     getLexer().Lex();
1360     NewOpcode = Name;
1361     NewOpcode += '+';
1362     Name = NewOpcode;
1363   }
1364   if (getLexer().is(AsmToken::Minus)) {
1365     getLexer().Lex();
1366     NewOpcode = Name;
1367     NewOpcode += '-';
1368     Name = NewOpcode;
1369   }
1370   // If the instruction ends in a '.', we need to create a separate
1371   // token for it, to match what TableGen is doing.
1372   size_t Dot = Name.find('.');
1373   StringRef Mnemonic = Name.slice(0, Dot);
1374   if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1375     Operands.push_back(
1376         PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64()));
1377   else
1378     Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1379   if (Dot != StringRef::npos) {
1380     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1381     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1382     if (!NewOpcode.empty()) // Underlying memory for Name is volatile.
1383       Operands.push_back(
1384           PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64()));
1385     else
1386       Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1387   }
1388 
1389   // If there are no more operands then finish
1390   if (getLexer().is(AsmToken::EndOfStatement))
1391     return false;
1392 
1393   // Parse the first operand
1394   if (ParseOperand(Operands))
1395     return true;
1396 
1397   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1398          getLexer().is(AsmToken::Comma)) {
1399     // Consume the comma token
1400     getLexer().Lex();
1401 
1402     // Parse the next operand
1403     if (ParseOperand(Operands))
1404       return true;
1405   }
1406 
1407   return false;
1408 }
1409 
1410 /// ParseDirective parses the PPC specific directives
1411 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1412   StringRef IDVal = DirectiveID.getIdentifier();
1413   if (!isDarwin()) {
1414     if (IDVal == ".word")
1415       return ParseDirectiveWord(2, DirectiveID.getLoc());
1416     if (IDVal == ".llong")
1417       return ParseDirectiveWord(8, DirectiveID.getLoc());
1418     if (IDVal == ".tc")
1419       return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1420     if (IDVal == ".machine")
1421       return ParseDirectiveMachine(DirectiveID.getLoc());
1422   } else {
1423     if (IDVal == ".machine")
1424       return ParseDarwinDirectiveMachine(DirectiveID.getLoc());
1425   }
1426   return true;
1427 }
1428 
1429 /// ParseDirectiveWord
1430 ///  ::= .word [ expression (, expression)* ]
1431 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1432   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1433     for (;;) {
1434       const MCExpr *Value;
1435       if (getParser().parseExpression(Value))
1436         return false;
1437 
1438       getParser().getStreamer().EmitValue(Value, Size);
1439 
1440       if (getLexer().is(AsmToken::EndOfStatement))
1441         break;
1442 
1443       if (getLexer().isNot(AsmToken::Comma))
1444         return Error(L, "unexpected token in directive");
1445       Parser.Lex();
1446     }
1447   }
1448 
1449   Parser.Lex();
1450   return false;
1451 }
1452 
1453 /// ParseDirectiveTC
1454 ///  ::= .tc [ symbol (, expression)* ]
1455 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1456   // Skip TC symbol, which is only used with XCOFF.
1457   while (getLexer().isNot(AsmToken::EndOfStatement)
1458          && getLexer().isNot(AsmToken::Comma))
1459     Parser.Lex();
1460   if (getLexer().isNot(AsmToken::Comma)) {
1461     Error(L, "unexpected token in directive");
1462     return false;
1463   }
1464   Parser.Lex();
1465 
1466   // Align to word size.
1467   getParser().getStreamer().EmitValueToAlignment(Size);
1468 
1469   // Emit expressions.
1470   return ParseDirectiveWord(Size, L);
1471 }
1472 
1473 /// ParseDirectiveMachine (ELF platforms)
1474 ///  ::= .machine [ cpu | "push" | "pop" ]
1475 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) {
1476   if (getLexer().isNot(AsmToken::Identifier) &&
1477       getLexer().isNot(AsmToken::String)) {
1478     Error(L, "unexpected token in directive");
1479     return false;
1480   }
1481 
1482   StringRef CPU = Parser.getTok().getIdentifier();
1483   Parser.Lex();
1484 
1485   // FIXME: Right now, the parser always allows any available
1486   // instruction, so the .machine directive is not useful.
1487   // Implement ".machine any" (by doing nothing) for the benefit
1488   // of existing assembler code.  Likewise, we can then implement
1489   // ".machine push" and ".machine pop" as no-op.
1490   if (CPU != "any" && CPU != "push" && CPU != "pop") {
1491     Error(L, "unrecognized machine type");
1492     return false;
1493   }
1494 
1495   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1496     Error(L, "unexpected token in directive");
1497     return false;
1498   }
1499   PPCTargetStreamer &TStreamer =
1500       *static_cast<PPCTargetStreamer *>(
1501            getParser().getStreamer().getTargetStreamer());
1502   TStreamer.emitMachine(CPU);
1503 
1504   return false;
1505 }
1506 
1507 /// ParseDarwinDirectiveMachine (Mach-o platforms)
1508 ///  ::= .machine cpu-identifier
1509 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) {
1510   if (getLexer().isNot(AsmToken::Identifier) &&
1511       getLexer().isNot(AsmToken::String)) {
1512     Error(L, "unexpected token in directive");
1513     return false;
1514   }
1515 
1516   StringRef CPU = Parser.getTok().getIdentifier();
1517   Parser.Lex();
1518 
1519   // FIXME: this is only the 'default' set of cpu variants.
1520   // However we don't act on this information at present, this is simply
1521   // allowing parsing to proceed with minimal sanity checking.
1522   if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") {
1523     Error(L, "unrecognized cpu type");
1524     return false;
1525   }
1526 
1527   if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) {
1528     Error(L, "wrong cpu type specified for 64bit");
1529     return false;
1530   }
1531   if (!isPPC64() && CPU == "ppc64") {
1532     Error(L, "wrong cpu type specified for 32bit");
1533     return false;
1534   }
1535 
1536   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1537     Error(L, "unexpected token in directive");
1538     return false;
1539   }
1540 
1541   return false;
1542 }
1543 
1544 /// Force static initialization.
1545 extern "C" void LLVMInitializePowerPCAsmParser() {
1546   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1547   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1548   RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget);
1549 }
1550 
1551 #define GET_REGISTER_MATCHER
1552 #define GET_MATCHER_IMPLEMENTATION
1553 #include "PPCGenAsmMatcher.inc"
1554 
1555 // Define this matcher function after the auto-generated include so we
1556 // have the match class enum definitions.
1557 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp,
1558                                                   unsigned Kind) {
1559   // If the kind is a token for a literal immediate, check if our asm
1560   // operand matches. This is for InstAliases which have a fixed-value
1561   // immediate in the syntax.
1562   int64_t ImmVal;
1563   switch (Kind) {
1564     case MCK_0: ImmVal = 0; break;
1565     case MCK_1: ImmVal = 1; break;
1566     case MCK_2: ImmVal = 2; break;
1567     case MCK_3: ImmVal = 3; break;
1568     default: return Match_InvalidOperand;
1569   }
1570 
1571   PPCOperand *Op = static_cast<PPCOperand*>(AsmOp);
1572   if (Op->isImm() && Op->getImm() == ImmVal)
1573     return Match_Success;
1574 
1575   return Match_InvalidOperand;
1576 }
1577 
1578 const MCExpr *
1579 PPCAsmParser::applyModifierToExpr(const MCExpr *E,
1580                                   MCSymbolRefExpr::VariantKind Variant,
1581                                   MCContext &Ctx) {
1582   switch (Variant) {
1583   case MCSymbolRefExpr::VK_PPC_LO:
1584     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx);
1585   case MCSymbolRefExpr::VK_PPC_HI:
1586     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx);
1587   case MCSymbolRefExpr::VK_PPC_HA:
1588     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx);
1589   case MCSymbolRefExpr::VK_PPC_HIGHER:
1590     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx);
1591   case MCSymbolRefExpr::VK_PPC_HIGHERA:
1592     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx);
1593   case MCSymbolRefExpr::VK_PPC_HIGHEST:
1594     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx);
1595   case MCSymbolRefExpr::VK_PPC_HIGHESTA:
1596     return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx);
1597   default:
1598     return nullptr;
1599   }
1600 }
1601