1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "MCTargetDesc/PPCMCExpr.h" 12 #include "PPCTargetStreamer.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/SmallString.h" 15 #include "llvm/ADT/SmallVector.h" 16 #include "llvm/ADT/StringSwitch.h" 17 #include "llvm/ADT/Twine.h" 18 #include "llvm/MC/MCExpr.h" 19 #include "llvm/MC/MCInst.h" 20 #include "llvm/MC/MCInstrInfo.h" 21 #include "llvm/MC/MCParser/MCAsmLexer.h" 22 #include "llvm/MC/MCParser/MCAsmParser.h" 23 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 24 #include "llvm/MC/MCRegisterInfo.h" 25 #include "llvm/MC/MCStreamer.h" 26 #include "llvm/MC/MCSubtargetInfo.h" 27 #include "llvm/MC/MCTargetAsmParser.h" 28 #include "llvm/Support/SourceMgr.h" 29 #include "llvm/Support/TargetRegistry.h" 30 #include "llvm/Support/raw_ostream.h" 31 32 using namespace llvm; 33 34 namespace { 35 36 static unsigned RRegs[32] = { 37 PPC::R0, PPC::R1, PPC::R2, PPC::R3, 38 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 39 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 40 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 41 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 42 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 43 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 44 PPC::R28, PPC::R29, PPC::R30, PPC::R31 45 }; 46 static unsigned RRegsNoR0[32] = { 47 PPC::ZERO, 48 PPC::R1, PPC::R2, PPC::R3, 49 PPC::R4, PPC::R5, PPC::R6, PPC::R7, 50 PPC::R8, PPC::R9, PPC::R10, PPC::R11, 51 PPC::R12, PPC::R13, PPC::R14, PPC::R15, 52 PPC::R16, PPC::R17, PPC::R18, PPC::R19, 53 PPC::R20, PPC::R21, PPC::R22, PPC::R23, 54 PPC::R24, PPC::R25, PPC::R26, PPC::R27, 55 PPC::R28, PPC::R29, PPC::R30, PPC::R31 56 }; 57 static unsigned XRegs[32] = { 58 PPC::X0, PPC::X1, PPC::X2, PPC::X3, 59 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 60 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 61 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 62 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 63 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 64 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 65 PPC::X28, PPC::X29, PPC::X30, PPC::X31 66 }; 67 static unsigned XRegsNoX0[32] = { 68 PPC::ZERO8, 69 PPC::X1, PPC::X2, PPC::X3, 70 PPC::X4, PPC::X5, PPC::X6, PPC::X7, 71 PPC::X8, PPC::X9, PPC::X10, PPC::X11, 72 PPC::X12, PPC::X13, PPC::X14, PPC::X15, 73 PPC::X16, PPC::X17, PPC::X18, PPC::X19, 74 PPC::X20, PPC::X21, PPC::X22, PPC::X23, 75 PPC::X24, PPC::X25, PPC::X26, PPC::X27, 76 PPC::X28, PPC::X29, PPC::X30, PPC::X31 77 }; 78 static unsigned FRegs[32] = { 79 PPC::F0, PPC::F1, PPC::F2, PPC::F3, 80 PPC::F4, PPC::F5, PPC::F6, PPC::F7, 81 PPC::F8, PPC::F9, PPC::F10, PPC::F11, 82 PPC::F12, PPC::F13, PPC::F14, PPC::F15, 83 PPC::F16, PPC::F17, PPC::F18, PPC::F19, 84 PPC::F20, PPC::F21, PPC::F22, PPC::F23, 85 PPC::F24, PPC::F25, PPC::F26, PPC::F27, 86 PPC::F28, PPC::F29, PPC::F30, PPC::F31 87 }; 88 static unsigned VRegs[32] = { 89 PPC::V0, PPC::V1, PPC::V2, PPC::V3, 90 PPC::V4, PPC::V5, PPC::V6, PPC::V7, 91 PPC::V8, PPC::V9, PPC::V10, PPC::V11, 92 PPC::V12, PPC::V13, PPC::V14, PPC::V15, 93 PPC::V16, PPC::V17, PPC::V18, PPC::V19, 94 PPC::V20, PPC::V21, PPC::V22, PPC::V23, 95 PPC::V24, PPC::V25, PPC::V26, PPC::V27, 96 PPC::V28, PPC::V29, PPC::V30, PPC::V31 97 }; 98 static unsigned VSRegs[64] = { 99 PPC::VSL0, PPC::VSL1, PPC::VSL2, PPC::VSL3, 100 PPC::VSL4, PPC::VSL5, PPC::VSL6, PPC::VSL7, 101 PPC::VSL8, PPC::VSL9, PPC::VSL10, PPC::VSL11, 102 PPC::VSL12, PPC::VSL13, PPC::VSL14, PPC::VSL15, 103 PPC::VSL16, PPC::VSL17, PPC::VSL18, PPC::VSL19, 104 PPC::VSL20, PPC::VSL21, PPC::VSL22, PPC::VSL23, 105 PPC::VSL24, PPC::VSL25, PPC::VSL26, PPC::VSL27, 106 PPC::VSL28, PPC::VSL29, PPC::VSL30, PPC::VSL31, 107 108 PPC::VSH0, PPC::VSH1, PPC::VSH2, PPC::VSH3, 109 PPC::VSH4, PPC::VSH5, PPC::VSH6, PPC::VSH7, 110 PPC::VSH8, PPC::VSH9, PPC::VSH10, PPC::VSH11, 111 PPC::VSH12, PPC::VSH13, PPC::VSH14, PPC::VSH15, 112 PPC::VSH16, PPC::VSH17, PPC::VSH18, PPC::VSH19, 113 PPC::VSH20, PPC::VSH21, PPC::VSH22, PPC::VSH23, 114 PPC::VSH24, PPC::VSH25, PPC::VSH26, PPC::VSH27, 115 PPC::VSH28, PPC::VSH29, PPC::VSH30, PPC::VSH31 116 }; 117 static unsigned CRBITRegs[32] = { 118 PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN, 119 PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN, 120 PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN, 121 PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN, 122 PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN, 123 PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN, 124 PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN, 125 PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN 126 }; 127 static unsigned CRRegs[8] = { 128 PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3, 129 PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7 130 }; 131 132 // Evaluate an expression containing condition register 133 // or condition register field symbols. Returns positive 134 // value on success, or -1 on error. 135 static int64_t 136 EvaluateCRExpr(const MCExpr *E) { 137 switch (E->getKind()) { 138 case MCExpr::Target: 139 return -1; 140 141 case MCExpr::Constant: { 142 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 143 return Res < 0 ? -1 : Res; 144 } 145 146 case MCExpr::SymbolRef: { 147 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 148 StringRef Name = SRE->getSymbol().getName(); 149 150 if (Name == "lt") return 0; 151 if (Name == "gt") return 1; 152 if (Name == "eq") return 2; 153 if (Name == "so") return 3; 154 if (Name == "un") return 3; 155 156 if (Name == "cr0") return 0; 157 if (Name == "cr1") return 1; 158 if (Name == "cr2") return 2; 159 if (Name == "cr3") return 3; 160 if (Name == "cr4") return 4; 161 if (Name == "cr5") return 5; 162 if (Name == "cr6") return 6; 163 if (Name == "cr7") return 7; 164 165 return -1; 166 } 167 168 case MCExpr::Unary: 169 return -1; 170 171 case MCExpr::Binary: { 172 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 173 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 174 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 175 int64_t Res; 176 177 if (LHSVal < 0 || RHSVal < 0) 178 return -1; 179 180 switch (BE->getOpcode()) { 181 default: return -1; 182 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 183 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 184 } 185 186 return Res < 0 ? -1 : Res; 187 } 188 } 189 190 llvm_unreachable("Invalid expression kind!"); 191 } 192 193 struct PPCOperand; 194 195 class PPCAsmParser : public MCTargetAsmParser { 196 MCSubtargetInfo &STI; 197 MCAsmParser &Parser; 198 const MCInstrInfo &MII; 199 bool IsPPC64; 200 bool IsDarwin; 201 202 MCAsmParser &getParser() const { return Parser; } 203 MCAsmLexer &getLexer() const { return Parser.getLexer(); } 204 205 void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); } 206 bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); } 207 208 bool isPPC64() const { return IsPPC64; } 209 bool isDarwin() const { return IsDarwin; } 210 211 bool MatchRegisterName(const AsmToken &Tok, 212 unsigned &RegNo, int64_t &IntVal); 213 214 virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc); 215 216 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 217 PPCMCExpr::VariantKind &Variant); 218 const MCExpr *FixupVariantKind(const MCExpr *E); 219 bool ParseExpression(const MCExpr *&EVal); 220 bool ParseDarwinExpression(const MCExpr *&EVal); 221 222 bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands); 223 224 bool ParseDirectiveWord(unsigned Size, SMLoc L); 225 bool ParseDirectiveTC(unsigned Size, SMLoc L); 226 bool ParseDirectiveMachine(SMLoc L); 227 bool ParseDarwinDirectiveMachine(SMLoc L); 228 229 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 230 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 231 MCStreamer &Out, unsigned &ErrorInfo, 232 bool MatchingInlineAsm); 233 234 void ProcessInstruction(MCInst &Inst, 235 const SmallVectorImpl<MCParsedAsmOperand*> &Ops); 236 237 /// @name Auto-generated Match Functions 238 /// { 239 240 #define GET_ASSEMBLER_HEADER 241 #include "PPCGenAsmMatcher.inc" 242 243 /// } 244 245 246 public: 247 PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser, 248 const MCInstrInfo &_MII) 249 : MCTargetAsmParser(), STI(_STI), Parser(_Parser), MII(_MII) { 250 // Check for 64-bit vs. 32-bit pointer mode. 251 Triple TheTriple(STI.getTargetTriple()); 252 IsPPC64 = (TheTriple.getArch() == Triple::ppc64 || 253 TheTriple.getArch() == Triple::ppc64le); 254 IsDarwin = TheTriple.isMacOSX(); 255 // Initialize the set of available features. 256 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 257 } 258 259 virtual bool ParseInstruction(ParseInstructionInfo &Info, 260 StringRef Name, SMLoc NameLoc, 261 SmallVectorImpl<MCParsedAsmOperand*> &Operands); 262 263 virtual bool ParseDirective(AsmToken DirectiveID); 264 265 unsigned validateTargetOperandClass(MCParsedAsmOperand *Op, unsigned Kind); 266 267 virtual const MCExpr *applyModifierToExpr(const MCExpr *E, 268 MCSymbolRefExpr::VariantKind, 269 MCContext &Ctx); 270 }; 271 272 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 273 /// instruction. 274 struct PPCOperand : public MCParsedAsmOperand { 275 enum KindTy { 276 Token, 277 Immediate, 278 Expression, 279 TLSRegister 280 } Kind; 281 282 SMLoc StartLoc, EndLoc; 283 bool IsPPC64; 284 285 struct TokOp { 286 const char *Data; 287 unsigned Length; 288 }; 289 290 struct ImmOp { 291 int64_t Val; 292 }; 293 294 struct ExprOp { 295 const MCExpr *Val; 296 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 297 }; 298 299 struct TLSRegOp { 300 const MCSymbolRefExpr *Sym; 301 }; 302 303 union { 304 struct TokOp Tok; 305 struct ImmOp Imm; 306 struct ExprOp Expr; 307 struct TLSRegOp TLSReg; 308 }; 309 310 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 311 public: 312 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 313 Kind = o.Kind; 314 StartLoc = o.StartLoc; 315 EndLoc = o.EndLoc; 316 IsPPC64 = o.IsPPC64; 317 switch (Kind) { 318 case Token: 319 Tok = o.Tok; 320 break; 321 case Immediate: 322 Imm = o.Imm; 323 break; 324 case Expression: 325 Expr = o.Expr; 326 break; 327 case TLSRegister: 328 TLSReg = o.TLSReg; 329 break; 330 } 331 } 332 333 /// getStartLoc - Get the location of the first token of this operand. 334 SMLoc getStartLoc() const { return StartLoc; } 335 336 /// getEndLoc - Get the location of the last token of this operand. 337 SMLoc getEndLoc() const { return EndLoc; } 338 339 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 340 bool isPPC64() const { return IsPPC64; } 341 342 int64_t getImm() const { 343 assert(Kind == Immediate && "Invalid access!"); 344 return Imm.Val; 345 } 346 347 const MCExpr *getExpr() const { 348 assert(Kind == Expression && "Invalid access!"); 349 return Expr.Val; 350 } 351 352 int64_t getExprCRVal() const { 353 assert(Kind == Expression && "Invalid access!"); 354 return Expr.CRVal; 355 } 356 357 const MCExpr *getTLSReg() const { 358 assert(Kind == TLSRegister && "Invalid access!"); 359 return TLSReg.Sym; 360 } 361 362 unsigned getReg() const { 363 assert(isRegNumber() && "Invalid access!"); 364 return (unsigned) Imm.Val; 365 } 366 367 unsigned getVSReg() const { 368 assert(isVSRegNumber() && "Invalid access!"); 369 return (unsigned) Imm.Val; 370 } 371 372 unsigned getCCReg() const { 373 assert(isCCRegNumber() && "Invalid access!"); 374 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 375 } 376 377 unsigned getCRBit() const { 378 assert(isCRBitNumber() && "Invalid access!"); 379 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 380 } 381 382 unsigned getCRBitMask() const { 383 assert(isCRBitMask() && "Invalid access!"); 384 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 385 } 386 387 bool isToken() const { return Kind == Token; } 388 bool isImm() const { return Kind == Immediate || Kind == Expression; } 389 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 390 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 391 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 392 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 393 bool isU16Imm() const { return Kind == Expression || 394 (Kind == Immediate && isUInt<16>(getImm())); } 395 bool isS16Imm() const { return Kind == Expression || 396 (Kind == Immediate && isInt<16>(getImm())); } 397 bool isS16ImmX4() const { return Kind == Expression || 398 (Kind == Immediate && isInt<16>(getImm()) && 399 (getImm() & 3) == 0); } 400 bool isS17Imm() const { return Kind == Expression || 401 (Kind == Immediate && isInt<17>(getImm())); } 402 bool isTLSReg() const { return Kind == TLSRegister; } 403 bool isDirectBr() const { return Kind == Expression || 404 (Kind == Immediate && isInt<26>(getImm()) && 405 (getImm() & 3) == 0); } 406 bool isCondBr() const { return Kind == Expression || 407 (Kind == Immediate && isInt<16>(getImm()) && 408 (getImm() & 3) == 0); } 409 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 410 bool isVSRegNumber() const { return Kind == Immediate && isUInt<6>(getImm()); } 411 bool isCCRegNumber() const { return (Kind == Expression 412 && isUInt<3>(getExprCRVal())) || 413 (Kind == Immediate 414 && isUInt<3>(getImm())); } 415 bool isCRBitNumber() const { return (Kind == Expression 416 && isUInt<5>(getExprCRVal())) || 417 (Kind == Immediate 418 && isUInt<5>(getImm())); } 419 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 420 isPowerOf2_32(getImm()); } 421 bool isMem() const { return false; } 422 bool isReg() const { return false; } 423 424 void addRegOperands(MCInst &Inst, unsigned N) const { 425 llvm_unreachable("addRegOperands"); 426 } 427 428 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 429 assert(N == 1 && "Invalid number of operands!"); 430 Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()])); 431 } 432 433 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 434 assert(N == 1 && "Invalid number of operands!"); 435 Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()])); 436 } 437 438 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 439 assert(N == 1 && "Invalid number of operands!"); 440 Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()])); 441 } 442 443 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 444 assert(N == 1 && "Invalid number of operands!"); 445 Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()])); 446 } 447 448 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 449 if (isPPC64()) 450 addRegG8RCOperands(Inst, N); 451 else 452 addRegGPRCOperands(Inst, N); 453 } 454 455 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 456 if (isPPC64()) 457 addRegG8RCNoX0Operands(Inst, N); 458 else 459 addRegGPRCNoR0Operands(Inst, N); 460 } 461 462 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 463 assert(N == 1 && "Invalid number of operands!"); 464 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 465 } 466 467 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 468 assert(N == 1 && "Invalid number of operands!"); 469 Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()])); 470 } 471 472 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 473 assert(N == 1 && "Invalid number of operands!"); 474 Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()])); 475 } 476 477 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 478 assert(N == 1 && "Invalid number of operands!"); 479 Inst.addOperand(MCOperand::CreateReg(VSRegs[getVSReg()])); 480 } 481 482 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 483 assert(N == 1 && "Invalid number of operands!"); 484 Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()])); 485 } 486 487 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 488 assert(N == 1 && "Invalid number of operands!"); 489 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()])); 490 } 491 492 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 493 assert(N == 1 && "Invalid number of operands!"); 494 Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()])); 495 } 496 497 void addImmOperands(MCInst &Inst, unsigned N) const { 498 assert(N == 1 && "Invalid number of operands!"); 499 if (Kind == Immediate) 500 Inst.addOperand(MCOperand::CreateImm(getImm())); 501 else 502 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 503 } 504 505 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 506 assert(N == 1 && "Invalid number of operands!"); 507 if (Kind == Immediate) 508 Inst.addOperand(MCOperand::CreateImm(getImm() / 4)); 509 else 510 Inst.addOperand(MCOperand::CreateExpr(getExpr())); 511 } 512 513 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 514 assert(N == 1 && "Invalid number of operands!"); 515 Inst.addOperand(MCOperand::CreateExpr(getTLSReg())); 516 } 517 518 StringRef getToken() const { 519 assert(Kind == Token && "Invalid access!"); 520 return StringRef(Tok.Data, Tok.Length); 521 } 522 523 virtual void print(raw_ostream &OS) const; 524 525 static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) { 526 PPCOperand *Op = new PPCOperand(Token); 527 Op->Tok.Data = Str.data(); 528 Op->Tok.Length = Str.size(); 529 Op->StartLoc = S; 530 Op->EndLoc = S; 531 Op->IsPPC64 = IsPPC64; 532 return Op; 533 } 534 535 static PPCOperand *CreateTokenWithStringCopy(StringRef Str, SMLoc S, 536 bool IsPPC64) { 537 // Allocate extra memory for the string and copy it. 538 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 539 PPCOperand *Op = new (Mem) PPCOperand(Token); 540 Op->Tok.Data = (const char *)(Op + 1); 541 Op->Tok.Length = Str.size(); 542 std::memcpy((char *)(Op + 1), Str.data(), Str.size()); 543 Op->StartLoc = S; 544 Op->EndLoc = S; 545 Op->IsPPC64 = IsPPC64; 546 return Op; 547 } 548 549 static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 550 PPCOperand *Op = new PPCOperand(Immediate); 551 Op->Imm.Val = Val; 552 Op->StartLoc = S; 553 Op->EndLoc = E; 554 Op->IsPPC64 = IsPPC64; 555 return Op; 556 } 557 558 static PPCOperand *CreateExpr(const MCExpr *Val, 559 SMLoc S, SMLoc E, bool IsPPC64) { 560 PPCOperand *Op = new PPCOperand(Expression); 561 Op->Expr.Val = Val; 562 Op->Expr.CRVal = EvaluateCRExpr(Val); 563 Op->StartLoc = S; 564 Op->EndLoc = E; 565 Op->IsPPC64 = IsPPC64; 566 return Op; 567 } 568 569 static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym, 570 SMLoc S, SMLoc E, bool IsPPC64) { 571 PPCOperand *Op = new PPCOperand(TLSRegister); 572 Op->TLSReg.Sym = Sym; 573 Op->StartLoc = S; 574 Op->EndLoc = E; 575 Op->IsPPC64 = IsPPC64; 576 return Op; 577 } 578 579 static PPCOperand *CreateFromMCExpr(const MCExpr *Val, 580 SMLoc S, SMLoc E, bool IsPPC64) { 581 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 582 return CreateImm(CE->getValue(), S, E, IsPPC64); 583 584 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 585 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS) 586 return CreateTLSReg(SRE, S, E, IsPPC64); 587 588 return CreateExpr(Val, S, E, IsPPC64); 589 } 590 }; 591 592 } // end anonymous namespace. 593 594 void PPCOperand::print(raw_ostream &OS) const { 595 switch (Kind) { 596 case Token: 597 OS << "'" << getToken() << "'"; 598 break; 599 case Immediate: 600 OS << getImm(); 601 break; 602 case Expression: 603 getExpr()->print(OS); 604 break; 605 case TLSRegister: 606 getTLSReg()->print(OS); 607 break; 608 } 609 } 610 611 612 void PPCAsmParser:: 613 ProcessInstruction(MCInst &Inst, 614 const SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 615 int Opcode = Inst.getOpcode(); 616 switch (Opcode) { 617 case PPC::LAx: { 618 MCInst TmpInst; 619 TmpInst.setOpcode(PPC::LA); 620 TmpInst.addOperand(Inst.getOperand(0)); 621 TmpInst.addOperand(Inst.getOperand(2)); 622 TmpInst.addOperand(Inst.getOperand(1)); 623 Inst = TmpInst; 624 break; 625 } 626 case PPC::SUBI: { 627 MCInst TmpInst; 628 int64_t N = Inst.getOperand(2).getImm(); 629 TmpInst.setOpcode(PPC::ADDI); 630 TmpInst.addOperand(Inst.getOperand(0)); 631 TmpInst.addOperand(Inst.getOperand(1)); 632 TmpInst.addOperand(MCOperand::CreateImm(-N)); 633 Inst = TmpInst; 634 break; 635 } 636 case PPC::SUBIS: { 637 MCInst TmpInst; 638 int64_t N = Inst.getOperand(2).getImm(); 639 TmpInst.setOpcode(PPC::ADDIS); 640 TmpInst.addOperand(Inst.getOperand(0)); 641 TmpInst.addOperand(Inst.getOperand(1)); 642 TmpInst.addOperand(MCOperand::CreateImm(-N)); 643 Inst = TmpInst; 644 break; 645 } 646 case PPC::SUBIC: { 647 MCInst TmpInst; 648 int64_t N = Inst.getOperand(2).getImm(); 649 TmpInst.setOpcode(PPC::ADDIC); 650 TmpInst.addOperand(Inst.getOperand(0)); 651 TmpInst.addOperand(Inst.getOperand(1)); 652 TmpInst.addOperand(MCOperand::CreateImm(-N)); 653 Inst = TmpInst; 654 break; 655 } 656 case PPC::SUBICo: { 657 MCInst TmpInst; 658 int64_t N = Inst.getOperand(2).getImm(); 659 TmpInst.setOpcode(PPC::ADDICo); 660 TmpInst.addOperand(Inst.getOperand(0)); 661 TmpInst.addOperand(Inst.getOperand(1)); 662 TmpInst.addOperand(MCOperand::CreateImm(-N)); 663 Inst = TmpInst; 664 break; 665 } 666 case PPC::EXTLWI: 667 case PPC::EXTLWIo: { 668 MCInst TmpInst; 669 int64_t N = Inst.getOperand(2).getImm(); 670 int64_t B = Inst.getOperand(3).getImm(); 671 TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo); 672 TmpInst.addOperand(Inst.getOperand(0)); 673 TmpInst.addOperand(Inst.getOperand(1)); 674 TmpInst.addOperand(MCOperand::CreateImm(B)); 675 TmpInst.addOperand(MCOperand::CreateImm(0)); 676 TmpInst.addOperand(MCOperand::CreateImm(N - 1)); 677 Inst = TmpInst; 678 break; 679 } 680 case PPC::EXTRWI: 681 case PPC::EXTRWIo: { 682 MCInst TmpInst; 683 int64_t N = Inst.getOperand(2).getImm(); 684 int64_t B = Inst.getOperand(3).getImm(); 685 TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo); 686 TmpInst.addOperand(Inst.getOperand(0)); 687 TmpInst.addOperand(Inst.getOperand(1)); 688 TmpInst.addOperand(MCOperand::CreateImm(B + N)); 689 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 690 TmpInst.addOperand(MCOperand::CreateImm(31)); 691 Inst = TmpInst; 692 break; 693 } 694 case PPC::INSLWI: 695 case PPC::INSLWIo: { 696 MCInst TmpInst; 697 int64_t N = Inst.getOperand(2).getImm(); 698 int64_t B = Inst.getOperand(3).getImm(); 699 TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo); 700 TmpInst.addOperand(Inst.getOperand(0)); 701 TmpInst.addOperand(Inst.getOperand(0)); 702 TmpInst.addOperand(Inst.getOperand(1)); 703 TmpInst.addOperand(MCOperand::CreateImm(32 - B)); 704 TmpInst.addOperand(MCOperand::CreateImm(B)); 705 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); 706 Inst = TmpInst; 707 break; 708 } 709 case PPC::INSRWI: 710 case PPC::INSRWIo: { 711 MCInst TmpInst; 712 int64_t N = Inst.getOperand(2).getImm(); 713 int64_t B = Inst.getOperand(3).getImm(); 714 TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo); 715 TmpInst.addOperand(Inst.getOperand(0)); 716 TmpInst.addOperand(Inst.getOperand(0)); 717 TmpInst.addOperand(Inst.getOperand(1)); 718 TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N))); 719 TmpInst.addOperand(MCOperand::CreateImm(B)); 720 TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1)); 721 Inst = TmpInst; 722 break; 723 } 724 case PPC::ROTRWI: 725 case PPC::ROTRWIo: { 726 MCInst TmpInst; 727 int64_t N = Inst.getOperand(2).getImm(); 728 TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo); 729 TmpInst.addOperand(Inst.getOperand(0)); 730 TmpInst.addOperand(Inst.getOperand(1)); 731 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 732 TmpInst.addOperand(MCOperand::CreateImm(0)); 733 TmpInst.addOperand(MCOperand::CreateImm(31)); 734 Inst = TmpInst; 735 break; 736 } 737 case PPC::SLWI: 738 case PPC::SLWIo: { 739 MCInst TmpInst; 740 int64_t N = Inst.getOperand(2).getImm(); 741 TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo); 742 TmpInst.addOperand(Inst.getOperand(0)); 743 TmpInst.addOperand(Inst.getOperand(1)); 744 TmpInst.addOperand(MCOperand::CreateImm(N)); 745 TmpInst.addOperand(MCOperand::CreateImm(0)); 746 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 747 Inst = TmpInst; 748 break; 749 } 750 case PPC::SRWI: 751 case PPC::SRWIo: { 752 MCInst TmpInst; 753 int64_t N = Inst.getOperand(2).getImm(); 754 TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo); 755 TmpInst.addOperand(Inst.getOperand(0)); 756 TmpInst.addOperand(Inst.getOperand(1)); 757 TmpInst.addOperand(MCOperand::CreateImm(32 - N)); 758 TmpInst.addOperand(MCOperand::CreateImm(N)); 759 TmpInst.addOperand(MCOperand::CreateImm(31)); 760 Inst = TmpInst; 761 break; 762 } 763 case PPC::CLRRWI: 764 case PPC::CLRRWIo: { 765 MCInst TmpInst; 766 int64_t N = Inst.getOperand(2).getImm(); 767 TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo); 768 TmpInst.addOperand(Inst.getOperand(0)); 769 TmpInst.addOperand(Inst.getOperand(1)); 770 TmpInst.addOperand(MCOperand::CreateImm(0)); 771 TmpInst.addOperand(MCOperand::CreateImm(0)); 772 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 773 Inst = TmpInst; 774 break; 775 } 776 case PPC::CLRLSLWI: 777 case PPC::CLRLSLWIo: { 778 MCInst TmpInst; 779 int64_t B = Inst.getOperand(2).getImm(); 780 int64_t N = Inst.getOperand(3).getImm(); 781 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo); 782 TmpInst.addOperand(Inst.getOperand(0)); 783 TmpInst.addOperand(Inst.getOperand(1)); 784 TmpInst.addOperand(MCOperand::CreateImm(N)); 785 TmpInst.addOperand(MCOperand::CreateImm(B - N)); 786 TmpInst.addOperand(MCOperand::CreateImm(31 - N)); 787 Inst = TmpInst; 788 break; 789 } 790 case PPC::EXTLDI: 791 case PPC::EXTLDIo: { 792 MCInst TmpInst; 793 int64_t N = Inst.getOperand(2).getImm(); 794 int64_t B = Inst.getOperand(3).getImm(); 795 TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo); 796 TmpInst.addOperand(Inst.getOperand(0)); 797 TmpInst.addOperand(Inst.getOperand(1)); 798 TmpInst.addOperand(MCOperand::CreateImm(B)); 799 TmpInst.addOperand(MCOperand::CreateImm(N - 1)); 800 Inst = TmpInst; 801 break; 802 } 803 case PPC::EXTRDI: 804 case PPC::EXTRDIo: { 805 MCInst TmpInst; 806 int64_t N = Inst.getOperand(2).getImm(); 807 int64_t B = Inst.getOperand(3).getImm(); 808 TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo); 809 TmpInst.addOperand(Inst.getOperand(0)); 810 TmpInst.addOperand(Inst.getOperand(1)); 811 TmpInst.addOperand(MCOperand::CreateImm(B + N)); 812 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 813 Inst = TmpInst; 814 break; 815 } 816 case PPC::INSRDI: 817 case PPC::INSRDIo: { 818 MCInst TmpInst; 819 int64_t N = Inst.getOperand(2).getImm(); 820 int64_t B = Inst.getOperand(3).getImm(); 821 TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo); 822 TmpInst.addOperand(Inst.getOperand(0)); 823 TmpInst.addOperand(Inst.getOperand(0)); 824 TmpInst.addOperand(Inst.getOperand(1)); 825 TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N))); 826 TmpInst.addOperand(MCOperand::CreateImm(B)); 827 Inst = TmpInst; 828 break; 829 } 830 case PPC::ROTRDI: 831 case PPC::ROTRDIo: { 832 MCInst TmpInst; 833 int64_t N = Inst.getOperand(2).getImm(); 834 TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo); 835 TmpInst.addOperand(Inst.getOperand(0)); 836 TmpInst.addOperand(Inst.getOperand(1)); 837 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 838 TmpInst.addOperand(MCOperand::CreateImm(0)); 839 Inst = TmpInst; 840 break; 841 } 842 case PPC::SLDI: 843 case PPC::SLDIo: { 844 MCInst TmpInst; 845 int64_t N = Inst.getOperand(2).getImm(); 846 TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo); 847 TmpInst.addOperand(Inst.getOperand(0)); 848 TmpInst.addOperand(Inst.getOperand(1)); 849 TmpInst.addOperand(MCOperand::CreateImm(N)); 850 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 851 Inst = TmpInst; 852 break; 853 } 854 case PPC::SRDI: 855 case PPC::SRDIo: { 856 MCInst TmpInst; 857 int64_t N = Inst.getOperand(2).getImm(); 858 TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo); 859 TmpInst.addOperand(Inst.getOperand(0)); 860 TmpInst.addOperand(Inst.getOperand(1)); 861 TmpInst.addOperand(MCOperand::CreateImm(64 - N)); 862 TmpInst.addOperand(MCOperand::CreateImm(N)); 863 Inst = TmpInst; 864 break; 865 } 866 case PPC::CLRRDI: 867 case PPC::CLRRDIo: { 868 MCInst TmpInst; 869 int64_t N = Inst.getOperand(2).getImm(); 870 TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo); 871 TmpInst.addOperand(Inst.getOperand(0)); 872 TmpInst.addOperand(Inst.getOperand(1)); 873 TmpInst.addOperand(MCOperand::CreateImm(0)); 874 TmpInst.addOperand(MCOperand::CreateImm(63 - N)); 875 Inst = TmpInst; 876 break; 877 } 878 case PPC::CLRLSLDI: 879 case PPC::CLRLSLDIo: { 880 MCInst TmpInst; 881 int64_t B = Inst.getOperand(2).getImm(); 882 int64_t N = Inst.getOperand(3).getImm(); 883 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo); 884 TmpInst.addOperand(Inst.getOperand(0)); 885 TmpInst.addOperand(Inst.getOperand(1)); 886 TmpInst.addOperand(MCOperand::CreateImm(N)); 887 TmpInst.addOperand(MCOperand::CreateImm(B - N)); 888 Inst = TmpInst; 889 break; 890 } 891 } 892 } 893 894 bool PPCAsmParser:: 895 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 896 SmallVectorImpl<MCParsedAsmOperand*> &Operands, 897 MCStreamer &Out, unsigned &ErrorInfo, 898 bool MatchingInlineAsm) { 899 MCInst Inst; 900 901 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 902 default: break; 903 case Match_Success: 904 // Post-process instructions (typically extended mnemonics) 905 ProcessInstruction(Inst, Operands); 906 Inst.setLoc(IDLoc); 907 Out.EmitInstruction(Inst, STI); 908 return false; 909 case Match_MissingFeature: 910 return Error(IDLoc, "instruction use requires an option to be enabled"); 911 case Match_MnemonicFail: 912 return Error(IDLoc, "unrecognized instruction mnemonic"); 913 case Match_InvalidOperand: { 914 SMLoc ErrorLoc = IDLoc; 915 if (ErrorInfo != ~0U) { 916 if (ErrorInfo >= Operands.size()) 917 return Error(IDLoc, "too few operands for instruction"); 918 919 ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc(); 920 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 921 } 922 923 return Error(ErrorLoc, "invalid operand for instruction"); 924 } 925 } 926 927 llvm_unreachable("Implement any new match types added!"); 928 } 929 930 bool PPCAsmParser:: 931 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) { 932 if (Tok.is(AsmToken::Identifier)) { 933 StringRef Name = Tok.getString(); 934 935 if (Name.equals_lower("lr")) { 936 RegNo = isPPC64()? PPC::LR8 : PPC::LR; 937 IntVal = 8; 938 return false; 939 } else if (Name.equals_lower("ctr")) { 940 RegNo = isPPC64()? PPC::CTR8 : PPC::CTR; 941 IntVal = 9; 942 return false; 943 } else if (Name.equals_lower("vrsave")) { 944 RegNo = PPC::VRSAVE; 945 IntVal = 256; 946 return false; 947 } else if (Name.startswith_lower("r") && 948 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 949 RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal]; 950 return false; 951 } else if (Name.startswith_lower("f") && 952 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 953 RegNo = FRegs[IntVal]; 954 return false; 955 } else if (Name.startswith_lower("v") && 956 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 957 RegNo = VRegs[IntVal]; 958 return false; 959 } else if (Name.startswith_lower("cr") && 960 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 961 RegNo = CRRegs[IntVal]; 962 return false; 963 } 964 } 965 966 return true; 967 } 968 969 bool PPCAsmParser:: 970 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 971 const AsmToken &Tok = Parser.getTok(); 972 StartLoc = Tok.getLoc(); 973 EndLoc = Tok.getEndLoc(); 974 RegNo = 0; 975 int64_t IntVal; 976 977 if (!MatchRegisterName(Tok, RegNo, IntVal)) { 978 Parser.Lex(); // Eat identifier token. 979 return false; 980 } 981 982 return Error(StartLoc, "invalid register name"); 983 } 984 985 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 986 /// the expression and check for VK_PPC_LO/HI/HA 987 /// symbol variants. If all symbols with modifier use the same 988 /// variant, return the corresponding PPCMCExpr::VariantKind, 989 /// and a modified expression using the default symbol variant. 990 /// Otherwise, return NULL. 991 const MCExpr *PPCAsmParser:: 992 ExtractModifierFromExpr(const MCExpr *E, 993 PPCMCExpr::VariantKind &Variant) { 994 MCContext &Context = getParser().getContext(); 995 Variant = PPCMCExpr::VK_PPC_None; 996 997 switch (E->getKind()) { 998 case MCExpr::Target: 999 case MCExpr::Constant: 1000 return 0; 1001 1002 case MCExpr::SymbolRef: { 1003 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1004 1005 switch (SRE->getKind()) { 1006 case MCSymbolRefExpr::VK_PPC_LO: 1007 Variant = PPCMCExpr::VK_PPC_LO; 1008 break; 1009 case MCSymbolRefExpr::VK_PPC_HI: 1010 Variant = PPCMCExpr::VK_PPC_HI; 1011 break; 1012 case MCSymbolRefExpr::VK_PPC_HA: 1013 Variant = PPCMCExpr::VK_PPC_HA; 1014 break; 1015 case MCSymbolRefExpr::VK_PPC_HIGHER: 1016 Variant = PPCMCExpr::VK_PPC_HIGHER; 1017 break; 1018 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1019 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1020 break; 1021 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1022 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1023 break; 1024 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1025 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1026 break; 1027 default: 1028 return 0; 1029 } 1030 1031 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context); 1032 } 1033 1034 case MCExpr::Unary: { 1035 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1036 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1037 if (!Sub) 1038 return 0; 1039 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); 1040 } 1041 1042 case MCExpr::Binary: { 1043 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1044 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1045 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1046 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1047 1048 if (!LHS && !RHS) 1049 return 0; 1050 1051 if (!LHS) LHS = BE->getLHS(); 1052 if (!RHS) RHS = BE->getRHS(); 1053 1054 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1055 Variant = RHSVariant; 1056 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1057 Variant = LHSVariant; 1058 else if (LHSVariant == RHSVariant) 1059 Variant = LHSVariant; 1060 else 1061 return 0; 1062 1063 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); 1064 } 1065 } 1066 1067 llvm_unreachable("Invalid expression kind!"); 1068 } 1069 1070 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1071 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1072 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1073 /// FIXME: This is a hack. 1074 const MCExpr *PPCAsmParser:: 1075 FixupVariantKind(const MCExpr *E) { 1076 MCContext &Context = getParser().getContext(); 1077 1078 switch (E->getKind()) { 1079 case MCExpr::Target: 1080 case MCExpr::Constant: 1081 return E; 1082 1083 case MCExpr::SymbolRef: { 1084 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1085 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1086 1087 switch (SRE->getKind()) { 1088 case MCSymbolRefExpr::VK_TLSGD: 1089 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1090 break; 1091 case MCSymbolRefExpr::VK_TLSLD: 1092 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1093 break; 1094 default: 1095 return E; 1096 } 1097 return MCSymbolRefExpr::Create(&SRE->getSymbol(), Variant, Context); 1098 } 1099 1100 case MCExpr::Unary: { 1101 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1102 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1103 if (Sub == UE->getSubExpr()) 1104 return E; 1105 return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context); 1106 } 1107 1108 case MCExpr::Binary: { 1109 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1110 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1111 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1112 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1113 return E; 1114 return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context); 1115 } 1116 } 1117 1118 llvm_unreachable("Invalid expression kind!"); 1119 } 1120 1121 /// ParseExpression. This differs from the default "parseExpression" in that 1122 /// it handles modifiers. 1123 bool PPCAsmParser:: 1124 ParseExpression(const MCExpr *&EVal) { 1125 1126 if (isDarwin()) 1127 return ParseDarwinExpression(EVal); 1128 1129 // (ELF Platforms) 1130 // Handle \code @l/@ha \endcode 1131 if (getParser().parseExpression(EVal)) 1132 return true; 1133 1134 EVal = FixupVariantKind(EVal); 1135 1136 PPCMCExpr::VariantKind Variant; 1137 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1138 if (E) 1139 EVal = PPCMCExpr::Create(Variant, E, false, getParser().getContext()); 1140 1141 return false; 1142 } 1143 1144 /// ParseDarwinExpression. (MachO Platforms) 1145 /// This differs from the default "parseExpression" in that it handles detection 1146 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1147 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1148 /// syntax form so it is done here. TODO: Determine if there is merit in arranging 1149 /// for this to be done at a higher level. 1150 bool PPCAsmParser:: 1151 ParseDarwinExpression(const MCExpr *&EVal) { 1152 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1153 switch (getLexer().getKind()) { 1154 default: 1155 break; 1156 case AsmToken::Identifier: 1157 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1158 // something starting with any other char should be part of the 1159 // asm syntax. If handwritten asm includes an identifier like lo16, 1160 // then all bets are off - but no-one would do that, right? 1161 StringRef poss = Parser.getTok().getString(); 1162 if (poss.equals_lower("lo16")) { 1163 Variant = PPCMCExpr::VK_PPC_LO; 1164 } else if (poss.equals_lower("hi16")) { 1165 Variant = PPCMCExpr::VK_PPC_HI; 1166 } else if (poss.equals_lower("ha16")) { 1167 Variant = PPCMCExpr::VK_PPC_HA; 1168 } 1169 if (Variant != PPCMCExpr::VK_PPC_None) { 1170 Parser.Lex(); // Eat the xx16 1171 if (getLexer().isNot(AsmToken::LParen)) 1172 return Error(Parser.getTok().getLoc(), "expected '('"); 1173 Parser.Lex(); // Eat the '(' 1174 } 1175 break; 1176 } 1177 1178 if (getParser().parseExpression(EVal)) 1179 return true; 1180 1181 if (Variant != PPCMCExpr::VK_PPC_None) { 1182 if (getLexer().isNot(AsmToken::RParen)) 1183 return Error(Parser.getTok().getLoc(), "expected ')'"); 1184 Parser.Lex(); // Eat the ')' 1185 EVal = PPCMCExpr::Create(Variant, EVal, false, getParser().getContext()); 1186 } 1187 return false; 1188 } 1189 1190 /// ParseOperand 1191 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1192 /// rNN for MachO. 1193 bool PPCAsmParser:: 1194 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1195 SMLoc S = Parser.getTok().getLoc(); 1196 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1197 const MCExpr *EVal; 1198 PPCOperand *Op; 1199 1200 // Attempt to parse the next token as an immediate 1201 switch (getLexer().getKind()) { 1202 // Special handling for register names. These are interpreted 1203 // as immediates corresponding to the register number. 1204 case AsmToken::Percent: 1205 Parser.Lex(); // Eat the '%'. 1206 unsigned RegNo; 1207 int64_t IntVal; 1208 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1209 Parser.Lex(); // Eat the identifier token. 1210 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1211 Operands.push_back(Op); 1212 return false; 1213 } 1214 return Error(S, "invalid register name"); 1215 1216 case AsmToken::Identifier: 1217 // Note that non-register-name identifiers from the compiler will begin 1218 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1219 // identifiers like r31foo - so we fall through in the event that parsing 1220 // a register name fails. 1221 if (isDarwin()) { 1222 unsigned RegNo; 1223 int64_t IntVal; 1224 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1225 Parser.Lex(); // Eat the identifier token. 1226 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1227 Operands.push_back(Op); 1228 return false; 1229 } 1230 } 1231 // Fall-through to process non-register-name identifiers as expression. 1232 // All other expressions 1233 case AsmToken::LParen: 1234 case AsmToken::Plus: 1235 case AsmToken::Minus: 1236 case AsmToken::Integer: 1237 case AsmToken::Dot: 1238 case AsmToken::Dollar: 1239 case AsmToken::Exclaim: 1240 case AsmToken::Tilde: 1241 if (!ParseExpression(EVal)) 1242 break; 1243 /* fall through */ 1244 default: 1245 return Error(S, "unknown operand"); 1246 } 1247 1248 // Push the parsed operand into the list of operands 1249 Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64()); 1250 Operands.push_back(Op); 1251 1252 // Check whether this is a TLS call expression 1253 bool TLSCall = false; 1254 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1255 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1256 1257 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1258 const MCExpr *TLSSym; 1259 1260 Parser.Lex(); // Eat the '('. 1261 S = Parser.getTok().getLoc(); 1262 if (ParseExpression(TLSSym)) 1263 return Error(S, "invalid TLS call expression"); 1264 if (getLexer().isNot(AsmToken::RParen)) 1265 return Error(Parser.getTok().getLoc(), "missing ')'"); 1266 E = Parser.getTok().getLoc(); 1267 Parser.Lex(); // Eat the ')'. 1268 1269 Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64()); 1270 Operands.push_back(Op); 1271 } 1272 1273 // Otherwise, check for D-form memory operands 1274 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1275 Parser.Lex(); // Eat the '('. 1276 S = Parser.getTok().getLoc(); 1277 1278 int64_t IntVal; 1279 switch (getLexer().getKind()) { 1280 case AsmToken::Percent: 1281 Parser.Lex(); // Eat the '%'. 1282 unsigned RegNo; 1283 if (MatchRegisterName(Parser.getTok(), RegNo, IntVal)) 1284 return Error(S, "invalid register name"); 1285 Parser.Lex(); // Eat the identifier token. 1286 break; 1287 1288 case AsmToken::Integer: 1289 if (!isDarwin()) { 1290 if (getParser().parseAbsoluteExpression(IntVal) || 1291 IntVal < 0 || IntVal > 31) 1292 return Error(S, "invalid register number"); 1293 } else { 1294 return Error(S, "unexpected integer value"); 1295 } 1296 break; 1297 1298 case AsmToken::Identifier: 1299 if (isDarwin()) { 1300 unsigned RegNo; 1301 if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) { 1302 Parser.Lex(); // Eat the identifier token. 1303 break; 1304 } 1305 } 1306 // Fall-through.. 1307 1308 default: 1309 return Error(S, "invalid memory operand"); 1310 } 1311 1312 if (getLexer().isNot(AsmToken::RParen)) 1313 return Error(Parser.getTok().getLoc(), "missing ')'"); 1314 E = Parser.getTok().getLoc(); 1315 Parser.Lex(); // Eat the ')'. 1316 1317 Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64()); 1318 Operands.push_back(Op); 1319 } 1320 1321 return false; 1322 } 1323 1324 /// Parse an instruction mnemonic followed by its operands. 1325 bool PPCAsmParser:: 1326 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc, 1327 SmallVectorImpl<MCParsedAsmOperand*> &Operands) { 1328 // The first operand is the token for the instruction name. 1329 // If the next character is a '+' or '-', we need to add it to the 1330 // instruction name, to match what TableGen is doing. 1331 std::string NewOpcode; 1332 if (getLexer().is(AsmToken::Plus)) { 1333 getLexer().Lex(); 1334 NewOpcode = Name; 1335 NewOpcode += '+'; 1336 Name = NewOpcode; 1337 } 1338 if (getLexer().is(AsmToken::Minus)) { 1339 getLexer().Lex(); 1340 NewOpcode = Name; 1341 NewOpcode += '-'; 1342 Name = NewOpcode; 1343 } 1344 // If the instruction ends in a '.', we need to create a separate 1345 // token for it, to match what TableGen is doing. 1346 size_t Dot = Name.find('.'); 1347 StringRef Mnemonic = Name.slice(0, Dot); 1348 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1349 Operands.push_back( 1350 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1351 else 1352 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1353 if (Dot != StringRef::npos) { 1354 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1355 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1356 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1357 Operands.push_back( 1358 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1359 else 1360 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1361 } 1362 1363 // If there are no more operands then finish 1364 if (getLexer().is(AsmToken::EndOfStatement)) 1365 return false; 1366 1367 // Parse the first operand 1368 if (ParseOperand(Operands)) 1369 return true; 1370 1371 while (getLexer().isNot(AsmToken::EndOfStatement) && 1372 getLexer().is(AsmToken::Comma)) { 1373 // Consume the comma token 1374 getLexer().Lex(); 1375 1376 // Parse the next operand 1377 if (ParseOperand(Operands)) 1378 return true; 1379 } 1380 1381 return false; 1382 } 1383 1384 /// ParseDirective parses the PPC specific directives 1385 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1386 StringRef IDVal = DirectiveID.getIdentifier(); 1387 if (!isDarwin()) { 1388 if (IDVal == ".word") 1389 return ParseDirectiveWord(2, DirectiveID.getLoc()); 1390 if (IDVal == ".llong") 1391 return ParseDirectiveWord(8, DirectiveID.getLoc()); 1392 if (IDVal == ".tc") 1393 return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc()); 1394 if (IDVal == ".machine") 1395 return ParseDirectiveMachine(DirectiveID.getLoc()); 1396 } else { 1397 if (IDVal == ".machine") 1398 return ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1399 } 1400 return true; 1401 } 1402 1403 /// ParseDirectiveWord 1404 /// ::= .word [ expression (, expression)* ] 1405 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) { 1406 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1407 for (;;) { 1408 const MCExpr *Value; 1409 if (getParser().parseExpression(Value)) 1410 return false; 1411 1412 getParser().getStreamer().EmitValue(Value, Size); 1413 1414 if (getLexer().is(AsmToken::EndOfStatement)) 1415 break; 1416 1417 if (getLexer().isNot(AsmToken::Comma)) 1418 return Error(L, "unexpected token in directive"); 1419 Parser.Lex(); 1420 } 1421 } 1422 1423 Parser.Lex(); 1424 return false; 1425 } 1426 1427 /// ParseDirectiveTC 1428 /// ::= .tc [ symbol (, expression)* ] 1429 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) { 1430 // Skip TC symbol, which is only used with XCOFF. 1431 while (getLexer().isNot(AsmToken::EndOfStatement) 1432 && getLexer().isNot(AsmToken::Comma)) 1433 Parser.Lex(); 1434 if (getLexer().isNot(AsmToken::Comma)) { 1435 Error(L, "unexpected token in directive"); 1436 return false; 1437 } 1438 Parser.Lex(); 1439 1440 // Align to word size. 1441 getParser().getStreamer().EmitValueToAlignment(Size); 1442 1443 // Emit expressions. 1444 return ParseDirectiveWord(Size, L); 1445 } 1446 1447 /// ParseDirectiveMachine (ELF platforms) 1448 /// ::= .machine [ cpu | "push" | "pop" ] 1449 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1450 if (getLexer().isNot(AsmToken::Identifier) && 1451 getLexer().isNot(AsmToken::String)) { 1452 Error(L, "unexpected token in directive"); 1453 return false; 1454 } 1455 1456 StringRef CPU = Parser.getTok().getIdentifier(); 1457 Parser.Lex(); 1458 1459 // FIXME: Right now, the parser always allows any available 1460 // instruction, so the .machine directive is not useful. 1461 // Implement ".machine any" (by doing nothing) for the benefit 1462 // of existing assembler code. Likewise, we can then implement 1463 // ".machine push" and ".machine pop" as no-op. 1464 if (CPU != "any" && CPU != "push" && CPU != "pop") { 1465 Error(L, "unrecognized machine type"); 1466 return false; 1467 } 1468 1469 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1470 Error(L, "unexpected token in directive"); 1471 return false; 1472 } 1473 PPCTargetStreamer &TStreamer = 1474 *static_cast<PPCTargetStreamer *>( 1475 getParser().getStreamer().getTargetStreamer()); 1476 TStreamer.emitMachine(CPU); 1477 1478 return false; 1479 } 1480 1481 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1482 /// ::= .machine cpu-identifier 1483 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1484 if (getLexer().isNot(AsmToken::Identifier) && 1485 getLexer().isNot(AsmToken::String)) { 1486 Error(L, "unexpected token in directive"); 1487 return false; 1488 } 1489 1490 StringRef CPU = Parser.getTok().getIdentifier(); 1491 Parser.Lex(); 1492 1493 // FIXME: this is only the 'default' set of cpu variants. 1494 // However we don't act on this information at present, this is simply 1495 // allowing parsing to proceed with minimal sanity checking. 1496 if (CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64") { 1497 Error(L, "unrecognized cpu type"); 1498 return false; 1499 } 1500 1501 if (isPPC64() && (CPU == "ppc7400" || CPU == "ppc")) { 1502 Error(L, "wrong cpu type specified for 64bit"); 1503 return false; 1504 } 1505 if (!isPPC64() && CPU == "ppc64") { 1506 Error(L, "wrong cpu type specified for 32bit"); 1507 return false; 1508 } 1509 1510 if (getLexer().isNot(AsmToken::EndOfStatement)) { 1511 Error(L, "unexpected token in directive"); 1512 return false; 1513 } 1514 1515 return false; 1516 } 1517 1518 /// Force static initialization. 1519 extern "C" void LLVMInitializePowerPCAsmParser() { 1520 RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target); 1521 RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target); 1522 RegisterMCAsmParser<PPCAsmParser> C(ThePPC64LETarget); 1523 } 1524 1525 #define GET_REGISTER_MATCHER 1526 #define GET_MATCHER_IMPLEMENTATION 1527 #include "PPCGenAsmMatcher.inc" 1528 1529 // Define this matcher function after the auto-generated include so we 1530 // have the match class enum definitions. 1531 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand *AsmOp, 1532 unsigned Kind) { 1533 // If the kind is a token for a literal immediate, check if our asm 1534 // operand matches. This is for InstAliases which have a fixed-value 1535 // immediate in the syntax. 1536 int64_t ImmVal; 1537 switch (Kind) { 1538 case MCK_0: ImmVal = 0; break; 1539 case MCK_1: ImmVal = 1; break; 1540 case MCK_2: ImmVal = 2; break; 1541 case MCK_3: ImmVal = 3; break; 1542 default: return Match_InvalidOperand; 1543 } 1544 1545 PPCOperand *Op = static_cast<PPCOperand*>(AsmOp); 1546 if (Op->isImm() && Op->getImm() == ImmVal) 1547 return Match_Success; 1548 1549 return Match_InvalidOperand; 1550 } 1551 1552 const MCExpr * 1553 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1554 MCSymbolRefExpr::VariantKind Variant, 1555 MCContext &Ctx) { 1556 switch (Variant) { 1557 case MCSymbolRefExpr::VK_PPC_LO: 1558 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_LO, E, false, Ctx); 1559 case MCSymbolRefExpr::VK_PPC_HI: 1560 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HI, E, false, Ctx); 1561 case MCSymbolRefExpr::VK_PPC_HA: 1562 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HA, E, false, Ctx); 1563 case MCSymbolRefExpr::VK_PPC_HIGHER: 1564 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHER, E, false, Ctx); 1565 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1566 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHERA, E, false, Ctx); 1567 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1568 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHEST, E, false, Ctx); 1569 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1570 return PPCMCExpr::Create(PPCMCExpr::VK_PPC_HIGHESTA, E, false, Ctx); 1571 default: 1572 return 0; 1573 } 1574 } 1575