1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions -------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 9 #include "MCTargetDesc/PPCMCExpr.h" 10 #include "MCTargetDesc/PPCMCTargetDesc.h" 11 #include "PPCTargetStreamer.h" 12 #include "TargetInfo/PowerPCTargetInfo.h" 13 #include "llvm/ADT/STLExtras.h" 14 #include "llvm/ADT/StringSwitch.h" 15 #include "llvm/ADT/Twine.h" 16 #include "llvm/MC/MCContext.h" 17 #include "llvm/MC/MCExpr.h" 18 #include "llvm/MC/MCInst.h" 19 #include "llvm/MC/MCInstrInfo.h" 20 #include "llvm/MC/MCParser/MCAsmLexer.h" 21 #include "llvm/MC/MCParser/MCAsmParser.h" 22 #include "llvm/MC/MCParser/MCParsedAsmOperand.h" 23 #include "llvm/MC/MCParser/MCTargetAsmParser.h" 24 #include "llvm/MC/MCStreamer.h" 25 #include "llvm/MC/MCSubtargetInfo.h" 26 #include "llvm/MC/MCSymbolELF.h" 27 #include "llvm/Support/SourceMgr.h" 28 #include "llvm/Support/TargetRegistry.h" 29 #include "llvm/Support/raw_ostream.h" 30 31 using namespace llvm; 32 33 DEFINE_PPC_REGCLASSES; 34 35 // Evaluate an expression containing condition register 36 // or condition register field symbols. Returns positive 37 // value on success, or -1 on error. 38 static int64_t 39 EvaluateCRExpr(const MCExpr *E) { 40 switch (E->getKind()) { 41 case MCExpr::Target: 42 return -1; 43 44 case MCExpr::Constant: { 45 int64_t Res = cast<MCConstantExpr>(E)->getValue(); 46 return Res < 0 ? -1 : Res; 47 } 48 49 case MCExpr::SymbolRef: { 50 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 51 StringRef Name = SRE->getSymbol().getName(); 52 53 if (Name == "lt") return 0; 54 if (Name == "gt") return 1; 55 if (Name == "eq") return 2; 56 if (Name == "so") return 3; 57 if (Name == "un") return 3; 58 59 if (Name == "cr0") return 0; 60 if (Name == "cr1") return 1; 61 if (Name == "cr2") return 2; 62 if (Name == "cr3") return 3; 63 if (Name == "cr4") return 4; 64 if (Name == "cr5") return 5; 65 if (Name == "cr6") return 6; 66 if (Name == "cr7") return 7; 67 68 return -1; 69 } 70 71 case MCExpr::Unary: 72 return -1; 73 74 case MCExpr::Binary: { 75 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 76 int64_t LHSVal = EvaluateCRExpr(BE->getLHS()); 77 int64_t RHSVal = EvaluateCRExpr(BE->getRHS()); 78 int64_t Res; 79 80 if (LHSVal < 0 || RHSVal < 0) 81 return -1; 82 83 switch (BE->getOpcode()) { 84 default: return -1; 85 case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break; 86 case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break; 87 } 88 89 return Res < 0 ? -1 : Res; 90 } 91 } 92 93 llvm_unreachable("Invalid expression kind!"); 94 } 95 96 namespace { 97 98 struct PPCOperand; 99 100 class PPCAsmParser : public MCTargetAsmParser { 101 bool IsPPC64; 102 bool IsDarwin; 103 104 void Warning(SMLoc L, const Twine &Msg) { getParser().Warning(L, Msg); } 105 106 bool isPPC64() const { return IsPPC64; } 107 bool isDarwin() const { return IsDarwin; } 108 109 bool MatchRegisterName(unsigned &RegNo, int64_t &IntVal); 110 111 bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) override; 112 OperandMatchResultTy tryParseRegister(unsigned &RegNo, SMLoc &StartLoc, 113 SMLoc &EndLoc) override; 114 115 const MCExpr *ExtractModifierFromExpr(const MCExpr *E, 116 PPCMCExpr::VariantKind &Variant); 117 const MCExpr *FixupVariantKind(const MCExpr *E); 118 bool ParseExpression(const MCExpr *&EVal); 119 bool ParseDarwinExpression(const MCExpr *&EVal); 120 121 bool ParseOperand(OperandVector &Operands); 122 123 bool ParseDirectiveWord(unsigned Size, AsmToken ID); 124 bool ParseDirectiveTC(unsigned Size, AsmToken ID); 125 bool ParseDirectiveMachine(SMLoc L); 126 bool ParseDarwinDirectiveMachine(SMLoc L); 127 bool ParseDirectiveAbiVersion(SMLoc L); 128 bool ParseDirectiveLocalEntry(SMLoc L); 129 130 bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 131 OperandVector &Operands, MCStreamer &Out, 132 uint64_t &ErrorInfo, 133 bool MatchingInlineAsm) override; 134 135 void ProcessInstruction(MCInst &Inst, const OperandVector &Ops); 136 137 /// @name Auto-generated Match Functions 138 /// { 139 140 #define GET_ASSEMBLER_HEADER 141 #include "PPCGenAsmMatcher.inc" 142 143 /// } 144 145 146 public: 147 PPCAsmParser(const MCSubtargetInfo &STI, MCAsmParser &, 148 const MCInstrInfo &MII, const MCTargetOptions &Options) 149 : MCTargetAsmParser(Options, STI, MII) { 150 // Check for 64-bit vs. 32-bit pointer mode. 151 const Triple &TheTriple = STI.getTargetTriple(); 152 IsPPC64 = TheTriple.isPPC64(); 153 IsDarwin = TheTriple.isMacOSX(); 154 // Initialize the set of available features. 155 setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits())); 156 } 157 158 bool ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 159 SMLoc NameLoc, OperandVector &Operands) override; 160 161 bool ParseDirective(AsmToken DirectiveID) override; 162 163 unsigned validateTargetOperandClass(MCParsedAsmOperand &Op, 164 unsigned Kind) override; 165 166 const MCExpr *applyModifierToExpr(const MCExpr *E, 167 MCSymbolRefExpr::VariantKind, 168 MCContext &Ctx) override; 169 }; 170 171 /// PPCOperand - Instances of this class represent a parsed PowerPC machine 172 /// instruction. 173 struct PPCOperand : public MCParsedAsmOperand { 174 enum KindTy { 175 Token, 176 Immediate, 177 ContextImmediate, 178 Expression, 179 TLSRegister 180 } Kind; 181 182 SMLoc StartLoc, EndLoc; 183 bool IsPPC64; 184 185 struct TokOp { 186 const char *Data; 187 unsigned Length; 188 }; 189 190 struct ImmOp { 191 int64_t Val; 192 }; 193 194 struct ExprOp { 195 const MCExpr *Val; 196 int64_t CRVal; // Cached result of EvaluateCRExpr(Val) 197 }; 198 199 struct TLSRegOp { 200 const MCSymbolRefExpr *Sym; 201 }; 202 203 union { 204 struct TokOp Tok; 205 struct ImmOp Imm; 206 struct ExprOp Expr; 207 struct TLSRegOp TLSReg; 208 }; 209 210 PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {} 211 public: 212 PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() { 213 Kind = o.Kind; 214 StartLoc = o.StartLoc; 215 EndLoc = o.EndLoc; 216 IsPPC64 = o.IsPPC64; 217 switch (Kind) { 218 case Token: 219 Tok = o.Tok; 220 break; 221 case Immediate: 222 case ContextImmediate: 223 Imm = o.Imm; 224 break; 225 case Expression: 226 Expr = o.Expr; 227 break; 228 case TLSRegister: 229 TLSReg = o.TLSReg; 230 break; 231 } 232 } 233 234 // Disable use of sized deallocation due to overallocation of PPCOperand 235 // objects in CreateTokenWithStringCopy. 236 void operator delete(void *p) { ::operator delete(p); } 237 238 /// getStartLoc - Get the location of the first token of this operand. 239 SMLoc getStartLoc() const override { return StartLoc; } 240 241 /// getEndLoc - Get the location of the last token of this operand. 242 SMLoc getEndLoc() const override { return EndLoc; } 243 244 /// getLocRange - Get the range between the first and last token of this 245 /// operand. 246 SMRange getLocRange() const { return SMRange(StartLoc, EndLoc); } 247 248 /// isPPC64 - True if this operand is for an instruction in 64-bit mode. 249 bool isPPC64() const { return IsPPC64; } 250 251 int64_t getImm() const { 252 assert(Kind == Immediate && "Invalid access!"); 253 return Imm.Val; 254 } 255 int64_t getImmS16Context() const { 256 assert((Kind == Immediate || Kind == ContextImmediate) && 257 "Invalid access!"); 258 if (Kind == Immediate) 259 return Imm.Val; 260 return static_cast<int16_t>(Imm.Val); 261 } 262 int64_t getImmU16Context() const { 263 assert((Kind == Immediate || Kind == ContextImmediate) && 264 "Invalid access!"); 265 return Imm.Val; 266 } 267 268 const MCExpr *getExpr() const { 269 assert(Kind == Expression && "Invalid access!"); 270 return Expr.Val; 271 } 272 273 int64_t getExprCRVal() const { 274 assert(Kind == Expression && "Invalid access!"); 275 return Expr.CRVal; 276 } 277 278 const MCExpr *getTLSReg() const { 279 assert(Kind == TLSRegister && "Invalid access!"); 280 return TLSReg.Sym; 281 } 282 283 unsigned getReg() const override { 284 assert(isRegNumber() && "Invalid access!"); 285 return (unsigned) Imm.Val; 286 } 287 288 unsigned getVSReg() const { 289 assert(isVSRegNumber() && "Invalid access!"); 290 return (unsigned) Imm.Val; 291 } 292 293 unsigned getACCReg() const { 294 assert(isACCRegNumber() && "Invalid access!"); 295 return (unsigned) Imm.Val; 296 } 297 298 unsigned getVSRpEvenReg() const { 299 assert(isVSRpEvenRegNumber() && "Invalid access!"); 300 return (unsigned) Imm.Val >> 1; 301 } 302 303 unsigned getCCReg() const { 304 assert(isCCRegNumber() && "Invalid access!"); 305 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 306 } 307 308 unsigned getCRBit() const { 309 assert(isCRBitNumber() && "Invalid access!"); 310 return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal); 311 } 312 313 unsigned getCRBitMask() const { 314 assert(isCRBitMask() && "Invalid access!"); 315 return 7 - countTrailingZeros<uint64_t>(Imm.Val); 316 } 317 318 bool isToken() const override { return Kind == Token; } 319 bool isImm() const override { 320 return Kind == Immediate || Kind == Expression; 321 } 322 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } 323 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } 324 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } 325 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } 326 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } 327 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } 328 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } 329 bool isU6ImmX2() const { return Kind == Immediate && 330 isUInt<6>(getImm()) && 331 (getImm() & 1) == 0; } 332 bool isU7Imm() const { return Kind == Immediate && isUInt<7>(getImm()); } 333 bool isU7ImmX4() const { return Kind == Immediate && 334 isUInt<7>(getImm()) && 335 (getImm() & 3) == 0; } 336 bool isU8Imm() const { return Kind == Immediate && isUInt<8>(getImm()); } 337 bool isU8ImmX8() const { return Kind == Immediate && 338 isUInt<8>(getImm()) && 339 (getImm() & 7) == 0; } 340 341 bool isU10Imm() const { return Kind == Immediate && isUInt<10>(getImm()); } 342 bool isU12Imm() const { return Kind == Immediate && isUInt<12>(getImm()); } 343 bool isU16Imm() const { 344 switch (Kind) { 345 case Expression: 346 return true; 347 case Immediate: 348 case ContextImmediate: 349 return isUInt<16>(getImmU16Context()); 350 default: 351 return false; 352 } 353 } 354 bool isS16Imm() const { 355 switch (Kind) { 356 case Expression: 357 return true; 358 case Immediate: 359 case ContextImmediate: 360 return isInt<16>(getImmS16Context()); 361 default: 362 return false; 363 } 364 } 365 bool isS16ImmX4() const { return Kind == Expression || 366 (Kind == Immediate && isInt<16>(getImm()) && 367 (getImm() & 3) == 0); } 368 bool isS16ImmX16() const { return Kind == Expression || 369 (Kind == Immediate && isInt<16>(getImm()) && 370 (getImm() & 15) == 0); } 371 bool isS34ImmX16() const { 372 return Kind == Expression || 373 (Kind == Immediate && isInt<34>(getImm()) && (getImm() & 15) == 0); 374 } 375 bool isS34Imm() const { 376 // Once the PC-Rel ABI is finalized, evaluate whether a 34-bit 377 // ContextImmediate is needed. 378 return Kind == Expression || (Kind == Immediate && isInt<34>(getImm())); 379 } 380 381 bool isS17Imm() const { 382 switch (Kind) { 383 case Expression: 384 return true; 385 case Immediate: 386 case ContextImmediate: 387 return isInt<17>(getImmS16Context()); 388 default: 389 return false; 390 } 391 } 392 bool isTLSReg() const { return Kind == TLSRegister; } 393 bool isDirectBr() const { 394 if (Kind == Expression) 395 return true; 396 if (Kind != Immediate) 397 return false; 398 // Operand must be 64-bit aligned, signed 27-bit immediate. 399 if ((getImm() & 3) != 0) 400 return false; 401 if (isInt<26>(getImm())) 402 return true; 403 if (!IsPPC64) { 404 // In 32-bit mode, large 32-bit quantities wrap around. 405 if (isUInt<32>(getImm()) && isInt<26>(static_cast<int32_t>(getImm()))) 406 return true; 407 } 408 return false; 409 } 410 bool isCondBr() const { return Kind == Expression || 411 (Kind == Immediate && isInt<16>(getImm()) && 412 (getImm() & 3) == 0); } 413 bool isImmZero() const { return Kind == Immediate && getImm() == 0; } 414 bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); } 415 bool isACCRegNumber() const { 416 return Kind == Immediate && isUInt<3>(getImm()); 417 } 418 bool isVSRpEvenRegNumber() const { 419 return Kind == Immediate && isUInt<6>(getImm()) && ((getImm() & 1) == 0); 420 } 421 bool isVSRegNumber() const { 422 return Kind == Immediate && isUInt<6>(getImm()); 423 } 424 bool isCCRegNumber() const { return (Kind == Expression 425 && isUInt<3>(getExprCRVal())) || 426 (Kind == Immediate 427 && isUInt<3>(getImm())); } 428 bool isCRBitNumber() const { return (Kind == Expression 429 && isUInt<5>(getExprCRVal())) || 430 (Kind == Immediate 431 && isUInt<5>(getImm())); } 432 bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) && 433 isPowerOf2_32(getImm()); } 434 bool isATBitsAsHint() const { return false; } 435 bool isMem() const override { return false; } 436 bool isReg() const override { return false; } 437 438 void addRegOperands(MCInst &Inst, unsigned N) const { 439 llvm_unreachable("addRegOperands"); 440 } 441 442 void addRegGPRCOperands(MCInst &Inst, unsigned N) const { 443 assert(N == 1 && "Invalid number of operands!"); 444 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 445 } 446 447 void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const { 448 assert(N == 1 && "Invalid number of operands!"); 449 Inst.addOperand(MCOperand::createReg(RRegsNoR0[getReg()])); 450 } 451 452 void addRegG8RCOperands(MCInst &Inst, unsigned N) const { 453 assert(N == 1 && "Invalid number of operands!"); 454 Inst.addOperand(MCOperand::createReg(XRegs[getReg()])); 455 } 456 457 void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const { 458 assert(N == 1 && "Invalid number of operands!"); 459 Inst.addOperand(MCOperand::createReg(XRegsNoX0[getReg()])); 460 } 461 462 void addRegGxRCOperands(MCInst &Inst, unsigned N) const { 463 if (isPPC64()) 464 addRegG8RCOperands(Inst, N); 465 else 466 addRegGPRCOperands(Inst, N); 467 } 468 469 void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const { 470 if (isPPC64()) 471 addRegG8RCNoX0Operands(Inst, N); 472 else 473 addRegGPRCNoR0Operands(Inst, N); 474 } 475 476 void addRegF4RCOperands(MCInst &Inst, unsigned N) const { 477 assert(N == 1 && "Invalid number of operands!"); 478 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 479 } 480 481 void addRegF8RCOperands(MCInst &Inst, unsigned N) const { 482 assert(N == 1 && "Invalid number of operands!"); 483 Inst.addOperand(MCOperand::createReg(FRegs[getReg()])); 484 } 485 486 void addRegVFRCOperands(MCInst &Inst, unsigned N) const { 487 assert(N == 1 && "Invalid number of operands!"); 488 Inst.addOperand(MCOperand::createReg(VFRegs[getReg()])); 489 } 490 491 void addRegVRRCOperands(MCInst &Inst, unsigned N) const { 492 assert(N == 1 && "Invalid number of operands!"); 493 Inst.addOperand(MCOperand::createReg(VRegs[getReg()])); 494 } 495 496 void addRegVSRCOperands(MCInst &Inst, unsigned N) const { 497 assert(N == 1 && "Invalid number of operands!"); 498 Inst.addOperand(MCOperand::createReg(VSRegs[getVSReg()])); 499 } 500 501 void addRegVSFRCOperands(MCInst &Inst, unsigned N) const { 502 assert(N == 1 && "Invalid number of operands!"); 503 Inst.addOperand(MCOperand::createReg(VSFRegs[getVSReg()])); 504 } 505 506 void addRegVSSRCOperands(MCInst &Inst, unsigned N) const { 507 assert(N == 1 && "Invalid number of operands!"); 508 Inst.addOperand(MCOperand::createReg(VSSRegs[getVSReg()])); 509 } 510 511 void addRegSPE4RCOperands(MCInst &Inst, unsigned N) const { 512 assert(N == 1 && "Invalid number of operands!"); 513 Inst.addOperand(MCOperand::createReg(RRegs[getReg()])); 514 } 515 516 void addRegSPERCOperands(MCInst &Inst, unsigned N) const { 517 assert(N == 1 && "Invalid number of operands!"); 518 Inst.addOperand(MCOperand::createReg(SPERegs[getReg()])); 519 } 520 521 void addRegACCRCOperands(MCInst &Inst, unsigned N) const { 522 assert(N == 1 && "Invalid number of operands!"); 523 Inst.addOperand(MCOperand::createReg(ACCRegs[getACCReg()])); 524 } 525 526 void addRegVSRpRCOperands(MCInst &Inst, unsigned N) const { 527 assert(N == 1 && "Invalid number of operands!"); 528 Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); 529 } 530 531 void addRegVSRpEvenRCOperands(MCInst &Inst, unsigned N) const { 532 assert(N == 1 && "Invalid number of operands!"); 533 Inst.addOperand(MCOperand::createReg(VSRpRegs[getVSRpEvenReg()])); 534 } 535 536 void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const { 537 assert(N == 1 && "Invalid number of operands!"); 538 Inst.addOperand(MCOperand::createReg(CRBITRegs[getCRBit()])); 539 } 540 541 void addRegCRRCOperands(MCInst &Inst, unsigned N) const { 542 assert(N == 1 && "Invalid number of operands!"); 543 Inst.addOperand(MCOperand::createReg(CRRegs[getCCReg()])); 544 } 545 546 void addCRBitMaskOperands(MCInst &Inst, unsigned N) const { 547 assert(N == 1 && "Invalid number of operands!"); 548 Inst.addOperand(MCOperand::createReg(CRRegs[getCRBitMask()])); 549 } 550 551 void addImmOperands(MCInst &Inst, unsigned N) const { 552 assert(N == 1 && "Invalid number of operands!"); 553 if (Kind == Immediate) 554 Inst.addOperand(MCOperand::createImm(getImm())); 555 else 556 Inst.addOperand(MCOperand::createExpr(getExpr())); 557 } 558 559 void addS16ImmOperands(MCInst &Inst, unsigned N) const { 560 assert(N == 1 && "Invalid number of operands!"); 561 switch (Kind) { 562 case Immediate: 563 Inst.addOperand(MCOperand::createImm(getImm())); 564 break; 565 case ContextImmediate: 566 Inst.addOperand(MCOperand::createImm(getImmS16Context())); 567 break; 568 default: 569 Inst.addOperand(MCOperand::createExpr(getExpr())); 570 break; 571 } 572 } 573 574 void addU16ImmOperands(MCInst &Inst, unsigned N) const { 575 assert(N == 1 && "Invalid number of operands!"); 576 switch (Kind) { 577 case Immediate: 578 Inst.addOperand(MCOperand::createImm(getImm())); 579 break; 580 case ContextImmediate: 581 Inst.addOperand(MCOperand::createImm(getImmU16Context())); 582 break; 583 default: 584 Inst.addOperand(MCOperand::createExpr(getExpr())); 585 break; 586 } 587 } 588 589 void addBranchTargetOperands(MCInst &Inst, unsigned N) const { 590 assert(N == 1 && "Invalid number of operands!"); 591 if (Kind == Immediate) 592 Inst.addOperand(MCOperand::createImm(getImm() / 4)); 593 else 594 Inst.addOperand(MCOperand::createExpr(getExpr())); 595 } 596 597 void addTLSRegOperands(MCInst &Inst, unsigned N) const { 598 assert(N == 1 && "Invalid number of operands!"); 599 Inst.addOperand(MCOperand::createExpr(getTLSReg())); 600 } 601 602 StringRef getToken() const { 603 assert(Kind == Token && "Invalid access!"); 604 return StringRef(Tok.Data, Tok.Length); 605 } 606 607 void print(raw_ostream &OS) const override; 608 609 static std::unique_ptr<PPCOperand> CreateToken(StringRef Str, SMLoc S, 610 bool IsPPC64) { 611 auto Op = std::make_unique<PPCOperand>(Token); 612 Op->Tok.Data = Str.data(); 613 Op->Tok.Length = Str.size(); 614 Op->StartLoc = S; 615 Op->EndLoc = S; 616 Op->IsPPC64 = IsPPC64; 617 return Op; 618 } 619 620 static std::unique_ptr<PPCOperand> 621 CreateTokenWithStringCopy(StringRef Str, SMLoc S, bool IsPPC64) { 622 // Allocate extra memory for the string and copy it. 623 // FIXME: This is incorrect, Operands are owned by unique_ptr with a default 624 // deleter which will destroy them by simply using "delete", not correctly 625 // calling operator delete on this extra memory after calling the dtor 626 // explicitly. 627 void *Mem = ::operator new(sizeof(PPCOperand) + Str.size()); 628 std::unique_ptr<PPCOperand> Op(new (Mem) PPCOperand(Token)); 629 Op->Tok.Data = reinterpret_cast<const char *>(Op.get() + 1); 630 Op->Tok.Length = Str.size(); 631 std::memcpy(const_cast<char *>(Op->Tok.Data), Str.data(), Str.size()); 632 Op->StartLoc = S; 633 Op->EndLoc = S; 634 Op->IsPPC64 = IsPPC64; 635 return Op; 636 } 637 638 static std::unique_ptr<PPCOperand> CreateImm(int64_t Val, SMLoc S, SMLoc E, 639 bool IsPPC64) { 640 auto Op = std::make_unique<PPCOperand>(Immediate); 641 Op->Imm.Val = Val; 642 Op->StartLoc = S; 643 Op->EndLoc = E; 644 Op->IsPPC64 = IsPPC64; 645 return Op; 646 } 647 648 static std::unique_ptr<PPCOperand> CreateExpr(const MCExpr *Val, SMLoc S, 649 SMLoc E, bool IsPPC64) { 650 auto Op = std::make_unique<PPCOperand>(Expression); 651 Op->Expr.Val = Val; 652 Op->Expr.CRVal = EvaluateCRExpr(Val); 653 Op->StartLoc = S; 654 Op->EndLoc = E; 655 Op->IsPPC64 = IsPPC64; 656 return Op; 657 } 658 659 static std::unique_ptr<PPCOperand> 660 CreateTLSReg(const MCSymbolRefExpr *Sym, SMLoc S, SMLoc E, bool IsPPC64) { 661 auto Op = std::make_unique<PPCOperand>(TLSRegister); 662 Op->TLSReg.Sym = Sym; 663 Op->StartLoc = S; 664 Op->EndLoc = E; 665 Op->IsPPC64 = IsPPC64; 666 return Op; 667 } 668 669 static std::unique_ptr<PPCOperand> 670 CreateContextImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) { 671 auto Op = std::make_unique<PPCOperand>(ContextImmediate); 672 Op->Imm.Val = Val; 673 Op->StartLoc = S; 674 Op->EndLoc = E; 675 Op->IsPPC64 = IsPPC64; 676 return Op; 677 } 678 679 static std::unique_ptr<PPCOperand> 680 CreateFromMCExpr(const MCExpr *Val, SMLoc S, SMLoc E, bool IsPPC64) { 681 if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val)) 682 return CreateImm(CE->getValue(), S, E, IsPPC64); 683 684 if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val)) 685 if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS || 686 SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS_PCREL) 687 return CreateTLSReg(SRE, S, E, IsPPC64); 688 689 if (const PPCMCExpr *TE = dyn_cast<PPCMCExpr>(Val)) { 690 int64_t Res; 691 if (TE->evaluateAsConstant(Res)) 692 return CreateContextImm(Res, S, E, IsPPC64); 693 } 694 695 return CreateExpr(Val, S, E, IsPPC64); 696 } 697 }; 698 699 } // end anonymous namespace. 700 701 void PPCOperand::print(raw_ostream &OS) const { 702 switch (Kind) { 703 case Token: 704 OS << "'" << getToken() << "'"; 705 break; 706 case Immediate: 707 case ContextImmediate: 708 OS << getImm(); 709 break; 710 case Expression: 711 OS << *getExpr(); 712 break; 713 case TLSRegister: 714 OS << *getTLSReg(); 715 break; 716 } 717 } 718 719 static void 720 addNegOperand(MCInst &Inst, MCOperand &Op, MCContext &Ctx) { 721 if (Op.isImm()) { 722 Inst.addOperand(MCOperand::createImm(-Op.getImm())); 723 return; 724 } 725 const MCExpr *Expr = Op.getExpr(); 726 if (const MCUnaryExpr *UnExpr = dyn_cast<MCUnaryExpr>(Expr)) { 727 if (UnExpr->getOpcode() == MCUnaryExpr::Minus) { 728 Inst.addOperand(MCOperand::createExpr(UnExpr->getSubExpr())); 729 return; 730 } 731 } else if (const MCBinaryExpr *BinExpr = dyn_cast<MCBinaryExpr>(Expr)) { 732 if (BinExpr->getOpcode() == MCBinaryExpr::Sub) { 733 const MCExpr *NE = MCBinaryExpr::createSub(BinExpr->getRHS(), 734 BinExpr->getLHS(), Ctx); 735 Inst.addOperand(MCOperand::createExpr(NE)); 736 return; 737 } 738 } 739 Inst.addOperand(MCOperand::createExpr(MCUnaryExpr::createMinus(Expr, Ctx))); 740 } 741 742 void PPCAsmParser::ProcessInstruction(MCInst &Inst, 743 const OperandVector &Operands) { 744 int Opcode = Inst.getOpcode(); 745 switch (Opcode) { 746 case PPC::DCBTx: 747 case PPC::DCBTT: 748 case PPC::DCBTSTx: 749 case PPC::DCBTSTT: { 750 MCInst TmpInst; 751 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ? 752 PPC::DCBT : PPC::DCBTST); 753 TmpInst.addOperand(MCOperand::createImm( 754 (Opcode == PPC::DCBTx || Opcode == PPC::DCBTSTx) ? 0 : 16)); 755 TmpInst.addOperand(Inst.getOperand(0)); 756 TmpInst.addOperand(Inst.getOperand(1)); 757 Inst = TmpInst; 758 break; 759 } 760 case PPC::DCBTCT: 761 case PPC::DCBTDS: { 762 MCInst TmpInst; 763 TmpInst.setOpcode(PPC::DCBT); 764 TmpInst.addOperand(Inst.getOperand(2)); 765 TmpInst.addOperand(Inst.getOperand(0)); 766 TmpInst.addOperand(Inst.getOperand(1)); 767 Inst = TmpInst; 768 break; 769 } 770 case PPC::DCBTSTCT: 771 case PPC::DCBTSTDS: { 772 MCInst TmpInst; 773 TmpInst.setOpcode(PPC::DCBTST); 774 TmpInst.addOperand(Inst.getOperand(2)); 775 TmpInst.addOperand(Inst.getOperand(0)); 776 TmpInst.addOperand(Inst.getOperand(1)); 777 Inst = TmpInst; 778 break; 779 } 780 case PPC::DCBFx: 781 case PPC::DCBFL: 782 case PPC::DCBFLP: { 783 int L = 0; 784 if (Opcode == PPC::DCBFL) 785 L = 1; 786 else if (Opcode == PPC::DCBFLP) 787 L = 3; 788 789 MCInst TmpInst; 790 TmpInst.setOpcode(PPC::DCBF); 791 TmpInst.addOperand(MCOperand::createImm(L)); 792 TmpInst.addOperand(Inst.getOperand(0)); 793 TmpInst.addOperand(Inst.getOperand(1)); 794 Inst = TmpInst; 795 break; 796 } 797 case PPC::LAx: { 798 MCInst TmpInst; 799 TmpInst.setOpcode(PPC::LA); 800 TmpInst.addOperand(Inst.getOperand(0)); 801 TmpInst.addOperand(Inst.getOperand(2)); 802 TmpInst.addOperand(Inst.getOperand(1)); 803 Inst = TmpInst; 804 break; 805 } 806 case PPC::SUBI: { 807 MCInst TmpInst; 808 TmpInst.setOpcode(PPC::ADDI); 809 TmpInst.addOperand(Inst.getOperand(0)); 810 TmpInst.addOperand(Inst.getOperand(1)); 811 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 812 Inst = TmpInst; 813 break; 814 } 815 case PPC::SUBIS: { 816 MCInst TmpInst; 817 TmpInst.setOpcode(PPC::ADDIS); 818 TmpInst.addOperand(Inst.getOperand(0)); 819 TmpInst.addOperand(Inst.getOperand(1)); 820 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 821 Inst = TmpInst; 822 break; 823 } 824 case PPC::SUBIC: { 825 MCInst TmpInst; 826 TmpInst.setOpcode(PPC::ADDIC); 827 TmpInst.addOperand(Inst.getOperand(0)); 828 TmpInst.addOperand(Inst.getOperand(1)); 829 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 830 Inst = TmpInst; 831 break; 832 } 833 case PPC::SUBIC_rec: { 834 MCInst TmpInst; 835 TmpInst.setOpcode(PPC::ADDIC_rec); 836 TmpInst.addOperand(Inst.getOperand(0)); 837 TmpInst.addOperand(Inst.getOperand(1)); 838 addNegOperand(TmpInst, Inst.getOperand(2), getContext()); 839 Inst = TmpInst; 840 break; 841 } 842 case PPC::EXTLWI: 843 case PPC::EXTLWI_rec: { 844 MCInst TmpInst; 845 int64_t N = Inst.getOperand(2).getImm(); 846 int64_t B = Inst.getOperand(3).getImm(); 847 TmpInst.setOpcode(Opcode == PPC::EXTLWI ? PPC::RLWINM : PPC::RLWINM_rec); 848 TmpInst.addOperand(Inst.getOperand(0)); 849 TmpInst.addOperand(Inst.getOperand(1)); 850 TmpInst.addOperand(MCOperand::createImm(B)); 851 TmpInst.addOperand(MCOperand::createImm(0)); 852 TmpInst.addOperand(MCOperand::createImm(N - 1)); 853 Inst = TmpInst; 854 break; 855 } 856 case PPC::EXTRWI: 857 case PPC::EXTRWI_rec: { 858 MCInst TmpInst; 859 int64_t N = Inst.getOperand(2).getImm(); 860 int64_t B = Inst.getOperand(3).getImm(); 861 TmpInst.setOpcode(Opcode == PPC::EXTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 862 TmpInst.addOperand(Inst.getOperand(0)); 863 TmpInst.addOperand(Inst.getOperand(1)); 864 TmpInst.addOperand(MCOperand::createImm(B + N)); 865 TmpInst.addOperand(MCOperand::createImm(32 - N)); 866 TmpInst.addOperand(MCOperand::createImm(31)); 867 Inst = TmpInst; 868 break; 869 } 870 case PPC::INSLWI: 871 case PPC::INSLWI_rec: { 872 MCInst TmpInst; 873 int64_t N = Inst.getOperand(2).getImm(); 874 int64_t B = Inst.getOperand(3).getImm(); 875 TmpInst.setOpcode(Opcode == PPC::INSLWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 876 TmpInst.addOperand(Inst.getOperand(0)); 877 TmpInst.addOperand(Inst.getOperand(0)); 878 TmpInst.addOperand(Inst.getOperand(1)); 879 TmpInst.addOperand(MCOperand::createImm(32 - B)); 880 TmpInst.addOperand(MCOperand::createImm(B)); 881 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 882 Inst = TmpInst; 883 break; 884 } 885 case PPC::INSRWI: 886 case PPC::INSRWI_rec: { 887 MCInst TmpInst; 888 int64_t N = Inst.getOperand(2).getImm(); 889 int64_t B = Inst.getOperand(3).getImm(); 890 TmpInst.setOpcode(Opcode == PPC::INSRWI ? PPC::RLWIMI : PPC::RLWIMI_rec); 891 TmpInst.addOperand(Inst.getOperand(0)); 892 TmpInst.addOperand(Inst.getOperand(0)); 893 TmpInst.addOperand(Inst.getOperand(1)); 894 TmpInst.addOperand(MCOperand::createImm(32 - (B + N))); 895 TmpInst.addOperand(MCOperand::createImm(B)); 896 TmpInst.addOperand(MCOperand::createImm((B + N) - 1)); 897 Inst = TmpInst; 898 break; 899 } 900 case PPC::ROTRWI: 901 case PPC::ROTRWI_rec: { 902 MCInst TmpInst; 903 int64_t N = Inst.getOperand(2).getImm(); 904 TmpInst.setOpcode(Opcode == PPC::ROTRWI ? PPC::RLWINM : PPC::RLWINM_rec); 905 TmpInst.addOperand(Inst.getOperand(0)); 906 TmpInst.addOperand(Inst.getOperand(1)); 907 TmpInst.addOperand(MCOperand::createImm(32 - N)); 908 TmpInst.addOperand(MCOperand::createImm(0)); 909 TmpInst.addOperand(MCOperand::createImm(31)); 910 Inst = TmpInst; 911 break; 912 } 913 case PPC::SLWI: 914 case PPC::SLWI_rec: { 915 MCInst TmpInst; 916 int64_t N = Inst.getOperand(2).getImm(); 917 TmpInst.setOpcode(Opcode == PPC::SLWI ? PPC::RLWINM : PPC::RLWINM_rec); 918 TmpInst.addOperand(Inst.getOperand(0)); 919 TmpInst.addOperand(Inst.getOperand(1)); 920 TmpInst.addOperand(MCOperand::createImm(N)); 921 TmpInst.addOperand(MCOperand::createImm(0)); 922 TmpInst.addOperand(MCOperand::createImm(31 - N)); 923 Inst = TmpInst; 924 break; 925 } 926 case PPC::SRWI: 927 case PPC::SRWI_rec: { 928 MCInst TmpInst; 929 int64_t N = Inst.getOperand(2).getImm(); 930 TmpInst.setOpcode(Opcode == PPC::SRWI ? PPC::RLWINM : PPC::RLWINM_rec); 931 TmpInst.addOperand(Inst.getOperand(0)); 932 TmpInst.addOperand(Inst.getOperand(1)); 933 TmpInst.addOperand(MCOperand::createImm(32 - N)); 934 TmpInst.addOperand(MCOperand::createImm(N)); 935 TmpInst.addOperand(MCOperand::createImm(31)); 936 Inst = TmpInst; 937 break; 938 } 939 case PPC::CLRRWI: 940 case PPC::CLRRWI_rec: { 941 MCInst TmpInst; 942 int64_t N = Inst.getOperand(2).getImm(); 943 TmpInst.setOpcode(Opcode == PPC::CLRRWI ? PPC::RLWINM : PPC::RLWINM_rec); 944 TmpInst.addOperand(Inst.getOperand(0)); 945 TmpInst.addOperand(Inst.getOperand(1)); 946 TmpInst.addOperand(MCOperand::createImm(0)); 947 TmpInst.addOperand(MCOperand::createImm(0)); 948 TmpInst.addOperand(MCOperand::createImm(31 - N)); 949 Inst = TmpInst; 950 break; 951 } 952 case PPC::CLRLSLWI: 953 case PPC::CLRLSLWI_rec: { 954 MCInst TmpInst; 955 int64_t B = Inst.getOperand(2).getImm(); 956 int64_t N = Inst.getOperand(3).getImm(); 957 TmpInst.setOpcode(Opcode == PPC::CLRLSLWI ? PPC::RLWINM : PPC::RLWINM_rec); 958 TmpInst.addOperand(Inst.getOperand(0)); 959 TmpInst.addOperand(Inst.getOperand(1)); 960 TmpInst.addOperand(MCOperand::createImm(N)); 961 TmpInst.addOperand(MCOperand::createImm(B - N)); 962 TmpInst.addOperand(MCOperand::createImm(31 - N)); 963 Inst = TmpInst; 964 break; 965 } 966 case PPC::EXTLDI: 967 case PPC::EXTLDI_rec: { 968 MCInst TmpInst; 969 int64_t N = Inst.getOperand(2).getImm(); 970 int64_t B = Inst.getOperand(3).getImm(); 971 TmpInst.setOpcode(Opcode == PPC::EXTLDI ? PPC::RLDICR : PPC::RLDICR_rec); 972 TmpInst.addOperand(Inst.getOperand(0)); 973 TmpInst.addOperand(Inst.getOperand(1)); 974 TmpInst.addOperand(MCOperand::createImm(B)); 975 TmpInst.addOperand(MCOperand::createImm(N - 1)); 976 Inst = TmpInst; 977 break; 978 } 979 case PPC::EXTRDI: 980 case PPC::EXTRDI_rec: { 981 MCInst TmpInst; 982 int64_t N = Inst.getOperand(2).getImm(); 983 int64_t B = Inst.getOperand(3).getImm(); 984 TmpInst.setOpcode(Opcode == PPC::EXTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 985 TmpInst.addOperand(Inst.getOperand(0)); 986 TmpInst.addOperand(Inst.getOperand(1)); 987 TmpInst.addOperand(MCOperand::createImm(B + N)); 988 TmpInst.addOperand(MCOperand::createImm(64 - N)); 989 Inst = TmpInst; 990 break; 991 } 992 case PPC::INSRDI: 993 case PPC::INSRDI_rec: { 994 MCInst TmpInst; 995 int64_t N = Inst.getOperand(2).getImm(); 996 int64_t B = Inst.getOperand(3).getImm(); 997 TmpInst.setOpcode(Opcode == PPC::INSRDI ? PPC::RLDIMI : PPC::RLDIMI_rec); 998 TmpInst.addOperand(Inst.getOperand(0)); 999 TmpInst.addOperand(Inst.getOperand(0)); 1000 TmpInst.addOperand(Inst.getOperand(1)); 1001 TmpInst.addOperand(MCOperand::createImm(64 - (B + N))); 1002 TmpInst.addOperand(MCOperand::createImm(B)); 1003 Inst = TmpInst; 1004 break; 1005 } 1006 case PPC::ROTRDI: 1007 case PPC::ROTRDI_rec: { 1008 MCInst TmpInst; 1009 int64_t N = Inst.getOperand(2).getImm(); 1010 TmpInst.setOpcode(Opcode == PPC::ROTRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1011 TmpInst.addOperand(Inst.getOperand(0)); 1012 TmpInst.addOperand(Inst.getOperand(1)); 1013 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1014 TmpInst.addOperand(MCOperand::createImm(0)); 1015 Inst = TmpInst; 1016 break; 1017 } 1018 case PPC::SLDI: 1019 case PPC::SLDI_rec: { 1020 MCInst TmpInst; 1021 int64_t N = Inst.getOperand(2).getImm(); 1022 TmpInst.setOpcode(Opcode == PPC::SLDI ? PPC::RLDICR : PPC::RLDICR_rec); 1023 TmpInst.addOperand(Inst.getOperand(0)); 1024 TmpInst.addOperand(Inst.getOperand(1)); 1025 TmpInst.addOperand(MCOperand::createImm(N)); 1026 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1027 Inst = TmpInst; 1028 break; 1029 } 1030 case PPC::SUBPCIS: { 1031 MCInst TmpInst; 1032 int64_t N = Inst.getOperand(1).getImm(); 1033 TmpInst.setOpcode(PPC::ADDPCIS); 1034 TmpInst.addOperand(Inst.getOperand(0)); 1035 TmpInst.addOperand(MCOperand::createImm(-N)); 1036 Inst = TmpInst; 1037 break; 1038 } 1039 case PPC::SRDI: 1040 case PPC::SRDI_rec: { 1041 MCInst TmpInst; 1042 int64_t N = Inst.getOperand(2).getImm(); 1043 TmpInst.setOpcode(Opcode == PPC::SRDI ? PPC::RLDICL : PPC::RLDICL_rec); 1044 TmpInst.addOperand(Inst.getOperand(0)); 1045 TmpInst.addOperand(Inst.getOperand(1)); 1046 TmpInst.addOperand(MCOperand::createImm(64 - N)); 1047 TmpInst.addOperand(MCOperand::createImm(N)); 1048 Inst = TmpInst; 1049 break; 1050 } 1051 case PPC::CLRRDI: 1052 case PPC::CLRRDI_rec: { 1053 MCInst TmpInst; 1054 int64_t N = Inst.getOperand(2).getImm(); 1055 TmpInst.setOpcode(Opcode == PPC::CLRRDI ? PPC::RLDICR : PPC::RLDICR_rec); 1056 TmpInst.addOperand(Inst.getOperand(0)); 1057 TmpInst.addOperand(Inst.getOperand(1)); 1058 TmpInst.addOperand(MCOperand::createImm(0)); 1059 TmpInst.addOperand(MCOperand::createImm(63 - N)); 1060 Inst = TmpInst; 1061 break; 1062 } 1063 case PPC::CLRLSLDI: 1064 case PPC::CLRLSLDI_rec: { 1065 MCInst TmpInst; 1066 int64_t B = Inst.getOperand(2).getImm(); 1067 int64_t N = Inst.getOperand(3).getImm(); 1068 TmpInst.setOpcode(Opcode == PPC::CLRLSLDI ? PPC::RLDIC : PPC::RLDIC_rec); 1069 TmpInst.addOperand(Inst.getOperand(0)); 1070 TmpInst.addOperand(Inst.getOperand(1)); 1071 TmpInst.addOperand(MCOperand::createImm(N)); 1072 TmpInst.addOperand(MCOperand::createImm(B - N)); 1073 Inst = TmpInst; 1074 break; 1075 } 1076 case PPC::RLWINMbm: 1077 case PPC::RLWINMbm_rec: { 1078 unsigned MB, ME; 1079 int64_t BM = Inst.getOperand(3).getImm(); 1080 if (!isRunOfOnes(BM, MB, ME)) 1081 break; 1082 1083 MCInst TmpInst; 1084 TmpInst.setOpcode(Opcode == PPC::RLWINMbm ? PPC::RLWINM : PPC::RLWINM_rec); 1085 TmpInst.addOperand(Inst.getOperand(0)); 1086 TmpInst.addOperand(Inst.getOperand(1)); 1087 TmpInst.addOperand(Inst.getOperand(2)); 1088 TmpInst.addOperand(MCOperand::createImm(MB)); 1089 TmpInst.addOperand(MCOperand::createImm(ME)); 1090 Inst = TmpInst; 1091 break; 1092 } 1093 case PPC::RLWIMIbm: 1094 case PPC::RLWIMIbm_rec: { 1095 unsigned MB, ME; 1096 int64_t BM = Inst.getOperand(3).getImm(); 1097 if (!isRunOfOnes(BM, MB, ME)) 1098 break; 1099 1100 MCInst TmpInst; 1101 TmpInst.setOpcode(Opcode == PPC::RLWIMIbm ? PPC::RLWIMI : PPC::RLWIMI_rec); 1102 TmpInst.addOperand(Inst.getOperand(0)); 1103 TmpInst.addOperand(Inst.getOperand(0)); // The tied operand. 1104 TmpInst.addOperand(Inst.getOperand(1)); 1105 TmpInst.addOperand(Inst.getOperand(2)); 1106 TmpInst.addOperand(MCOperand::createImm(MB)); 1107 TmpInst.addOperand(MCOperand::createImm(ME)); 1108 Inst = TmpInst; 1109 break; 1110 } 1111 case PPC::RLWNMbm: 1112 case PPC::RLWNMbm_rec: { 1113 unsigned MB, ME; 1114 int64_t BM = Inst.getOperand(3).getImm(); 1115 if (!isRunOfOnes(BM, MB, ME)) 1116 break; 1117 1118 MCInst TmpInst; 1119 TmpInst.setOpcode(Opcode == PPC::RLWNMbm ? PPC::RLWNM : PPC::RLWNM_rec); 1120 TmpInst.addOperand(Inst.getOperand(0)); 1121 TmpInst.addOperand(Inst.getOperand(1)); 1122 TmpInst.addOperand(Inst.getOperand(2)); 1123 TmpInst.addOperand(MCOperand::createImm(MB)); 1124 TmpInst.addOperand(MCOperand::createImm(ME)); 1125 Inst = TmpInst; 1126 break; 1127 } 1128 case PPC::MFTB: { 1129 if (getSTI().getFeatureBits()[PPC::FeatureMFTB]) { 1130 assert(Inst.getNumOperands() == 2 && "Expecting two operands"); 1131 Inst.setOpcode(PPC::MFSPR); 1132 } 1133 break; 1134 } 1135 case PPC::CP_COPYx: 1136 case PPC::CP_COPY_FIRST: { 1137 MCInst TmpInst; 1138 TmpInst.setOpcode(PPC::CP_COPY); 1139 TmpInst.addOperand(Inst.getOperand(0)); 1140 TmpInst.addOperand(Inst.getOperand(1)); 1141 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_COPYx ? 0 : 1)); 1142 1143 Inst = TmpInst; 1144 break; 1145 } 1146 case PPC::CP_PASTEx : 1147 case PPC::CP_PASTE_LAST: { 1148 MCInst TmpInst; 1149 TmpInst.setOpcode(Opcode == PPC::CP_PASTEx ? PPC::CP_PASTE 1150 : PPC::CP_PASTE_rec); 1151 TmpInst.addOperand(Inst.getOperand(0)); 1152 TmpInst.addOperand(Inst.getOperand(1)); 1153 TmpInst.addOperand(MCOperand::createImm(Opcode == PPC::CP_PASTEx ? 0 : 1)); 1154 1155 Inst = TmpInst; 1156 break; 1157 } 1158 } 1159 } 1160 1161 static std::string PPCMnemonicSpellCheck(StringRef S, const FeatureBitset &FBS, 1162 unsigned VariantID = 0); 1163 1164 bool PPCAsmParser::MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode, 1165 OperandVector &Operands, 1166 MCStreamer &Out, uint64_t &ErrorInfo, 1167 bool MatchingInlineAsm) { 1168 MCInst Inst; 1169 1170 switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) { 1171 case Match_Success: 1172 // Post-process instructions (typically extended mnemonics) 1173 ProcessInstruction(Inst, Operands); 1174 Inst.setLoc(IDLoc); 1175 Out.emitInstruction(Inst, getSTI()); 1176 return false; 1177 case Match_MissingFeature: 1178 return Error(IDLoc, "instruction use requires an option to be enabled"); 1179 case Match_MnemonicFail: { 1180 FeatureBitset FBS = ComputeAvailableFeatures(getSTI().getFeatureBits()); 1181 std::string Suggestion = PPCMnemonicSpellCheck( 1182 ((PPCOperand &)*Operands[0]).getToken(), FBS); 1183 return Error(IDLoc, "invalid instruction" + Suggestion, 1184 ((PPCOperand &)*Operands[0]).getLocRange()); 1185 } 1186 case Match_InvalidOperand: { 1187 SMLoc ErrorLoc = IDLoc; 1188 if (ErrorInfo != ~0ULL) { 1189 if (ErrorInfo >= Operands.size()) 1190 return Error(IDLoc, "too few operands for instruction"); 1191 1192 ErrorLoc = ((PPCOperand &)*Operands[ErrorInfo]).getStartLoc(); 1193 if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc; 1194 } 1195 1196 return Error(ErrorLoc, "invalid operand for instruction"); 1197 } 1198 } 1199 1200 llvm_unreachable("Implement any new match types added!"); 1201 } 1202 1203 bool PPCAsmParser::MatchRegisterName(unsigned &RegNo, int64_t &IntVal) { 1204 if (getParser().getTok().is(AsmToken::Percent)) 1205 getParser().Lex(); // Eat the '%'. 1206 1207 if (!getParser().getTok().is(AsmToken::Identifier)) 1208 return true; 1209 1210 StringRef Name = getParser().getTok().getString(); 1211 if (Name.equals_lower("lr")) { 1212 RegNo = isPPC64() ? PPC::LR8 : PPC::LR; 1213 IntVal = 8; 1214 } else if (Name.equals_lower("ctr")) { 1215 RegNo = isPPC64() ? PPC::CTR8 : PPC::CTR; 1216 IntVal = 9; 1217 } else if (Name.equals_lower("vrsave")) { 1218 RegNo = PPC::VRSAVE; 1219 IntVal = 256; 1220 } else if (Name.startswith_lower("r") && 1221 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1222 RegNo = isPPC64() ? XRegs[IntVal] : RRegs[IntVal]; 1223 } else if (Name.startswith_lower("f") && 1224 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1225 RegNo = FRegs[IntVal]; 1226 } else if (Name.startswith_lower("vs") && 1227 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 64) { 1228 RegNo = VSRegs[IntVal]; 1229 } else if (Name.startswith_lower("v") && 1230 !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) { 1231 RegNo = VRegs[IntVal]; 1232 } else if (Name.startswith_lower("cr") && 1233 !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) { 1234 RegNo = CRRegs[IntVal]; 1235 } else 1236 return true; 1237 getParser().Lex(); 1238 return false; 1239 } 1240 1241 bool PPCAsmParser:: 1242 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) { 1243 if (tryParseRegister(RegNo, StartLoc, EndLoc) != MatchOperand_Success) 1244 return TokError("invalid register name"); 1245 return false; 1246 } 1247 1248 OperandMatchResultTy PPCAsmParser::tryParseRegister(unsigned &RegNo, 1249 SMLoc &StartLoc, 1250 SMLoc &EndLoc) { 1251 const AsmToken &Tok = getParser().getTok(); 1252 StartLoc = Tok.getLoc(); 1253 EndLoc = Tok.getEndLoc(); 1254 RegNo = 0; 1255 int64_t IntVal; 1256 if (MatchRegisterName(RegNo, IntVal)) 1257 return MatchOperand_NoMatch; 1258 return MatchOperand_Success; 1259 } 1260 1261 /// Extract \code @l/@ha \endcode modifier from expression. Recursively scan 1262 /// the expression and check for VK_PPC_LO/HI/HA 1263 /// symbol variants. If all symbols with modifier use the same 1264 /// variant, return the corresponding PPCMCExpr::VariantKind, 1265 /// and a modified expression using the default symbol variant. 1266 /// Otherwise, return NULL. 1267 const MCExpr *PPCAsmParser:: 1268 ExtractModifierFromExpr(const MCExpr *E, 1269 PPCMCExpr::VariantKind &Variant) { 1270 MCContext &Context = getParser().getContext(); 1271 Variant = PPCMCExpr::VK_PPC_None; 1272 1273 switch (E->getKind()) { 1274 case MCExpr::Target: 1275 case MCExpr::Constant: 1276 return nullptr; 1277 1278 case MCExpr::SymbolRef: { 1279 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1280 1281 switch (SRE->getKind()) { 1282 case MCSymbolRefExpr::VK_PPC_LO: 1283 Variant = PPCMCExpr::VK_PPC_LO; 1284 break; 1285 case MCSymbolRefExpr::VK_PPC_HI: 1286 Variant = PPCMCExpr::VK_PPC_HI; 1287 break; 1288 case MCSymbolRefExpr::VK_PPC_HA: 1289 Variant = PPCMCExpr::VK_PPC_HA; 1290 break; 1291 case MCSymbolRefExpr::VK_PPC_HIGH: 1292 Variant = PPCMCExpr::VK_PPC_HIGH; 1293 break; 1294 case MCSymbolRefExpr::VK_PPC_HIGHA: 1295 Variant = PPCMCExpr::VK_PPC_HIGHA; 1296 break; 1297 case MCSymbolRefExpr::VK_PPC_HIGHER: 1298 Variant = PPCMCExpr::VK_PPC_HIGHER; 1299 break; 1300 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1301 Variant = PPCMCExpr::VK_PPC_HIGHERA; 1302 break; 1303 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1304 Variant = PPCMCExpr::VK_PPC_HIGHEST; 1305 break; 1306 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1307 Variant = PPCMCExpr::VK_PPC_HIGHESTA; 1308 break; 1309 default: 1310 return nullptr; 1311 } 1312 1313 return MCSymbolRefExpr::create(&SRE->getSymbol(), Context); 1314 } 1315 1316 case MCExpr::Unary: { 1317 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1318 const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant); 1319 if (!Sub) 1320 return nullptr; 1321 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1322 } 1323 1324 case MCExpr::Binary: { 1325 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1326 PPCMCExpr::VariantKind LHSVariant, RHSVariant; 1327 const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant); 1328 const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant); 1329 1330 if (!LHS && !RHS) 1331 return nullptr; 1332 1333 if (!LHS) LHS = BE->getLHS(); 1334 if (!RHS) RHS = BE->getRHS(); 1335 1336 if (LHSVariant == PPCMCExpr::VK_PPC_None) 1337 Variant = RHSVariant; 1338 else if (RHSVariant == PPCMCExpr::VK_PPC_None) 1339 Variant = LHSVariant; 1340 else if (LHSVariant == RHSVariant) 1341 Variant = LHSVariant; 1342 else 1343 return nullptr; 1344 1345 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1346 } 1347 } 1348 1349 llvm_unreachable("Invalid expression kind!"); 1350 } 1351 1352 /// Find all VK_TLSGD/VK_TLSLD symbol references in expression and replace 1353 /// them by VK_PPC_TLSGD/VK_PPC_TLSLD. This is necessary to avoid having 1354 /// _GLOBAL_OFFSET_TABLE_ created via ELFObjectWriter::RelocNeedsGOT. 1355 /// FIXME: This is a hack. 1356 const MCExpr *PPCAsmParser:: 1357 FixupVariantKind(const MCExpr *E) { 1358 MCContext &Context = getParser().getContext(); 1359 1360 switch (E->getKind()) { 1361 case MCExpr::Target: 1362 case MCExpr::Constant: 1363 return E; 1364 1365 case MCExpr::SymbolRef: { 1366 const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E); 1367 MCSymbolRefExpr::VariantKind Variant = MCSymbolRefExpr::VK_None; 1368 1369 switch (SRE->getKind()) { 1370 case MCSymbolRefExpr::VK_TLSGD: 1371 Variant = MCSymbolRefExpr::VK_PPC_TLSGD; 1372 break; 1373 case MCSymbolRefExpr::VK_TLSLD: 1374 Variant = MCSymbolRefExpr::VK_PPC_TLSLD; 1375 break; 1376 default: 1377 return E; 1378 } 1379 return MCSymbolRefExpr::create(&SRE->getSymbol(), Variant, Context); 1380 } 1381 1382 case MCExpr::Unary: { 1383 const MCUnaryExpr *UE = cast<MCUnaryExpr>(E); 1384 const MCExpr *Sub = FixupVariantKind(UE->getSubExpr()); 1385 if (Sub == UE->getSubExpr()) 1386 return E; 1387 return MCUnaryExpr::create(UE->getOpcode(), Sub, Context); 1388 } 1389 1390 case MCExpr::Binary: { 1391 const MCBinaryExpr *BE = cast<MCBinaryExpr>(E); 1392 const MCExpr *LHS = FixupVariantKind(BE->getLHS()); 1393 const MCExpr *RHS = FixupVariantKind(BE->getRHS()); 1394 if (LHS == BE->getLHS() && RHS == BE->getRHS()) 1395 return E; 1396 return MCBinaryExpr::create(BE->getOpcode(), LHS, RHS, Context); 1397 } 1398 } 1399 1400 llvm_unreachable("Invalid expression kind!"); 1401 } 1402 1403 /// ParseExpression. This differs from the default "parseExpression" in that 1404 /// it handles modifiers. 1405 bool PPCAsmParser:: 1406 ParseExpression(const MCExpr *&EVal) { 1407 1408 if (isDarwin()) 1409 return ParseDarwinExpression(EVal); 1410 1411 // (ELF Platforms) 1412 // Handle \code @l/@ha \endcode 1413 if (getParser().parseExpression(EVal)) 1414 return true; 1415 1416 EVal = FixupVariantKind(EVal); 1417 1418 PPCMCExpr::VariantKind Variant; 1419 const MCExpr *E = ExtractModifierFromExpr(EVal, Variant); 1420 if (E) 1421 EVal = PPCMCExpr::create(Variant, E, getParser().getContext()); 1422 1423 return false; 1424 } 1425 1426 /// ParseDarwinExpression. (MachO Platforms) 1427 /// This differs from the default "parseExpression" in that it handles detection 1428 /// of the \code hi16(), ha16() and lo16() \endcode modifiers. At present, 1429 /// parseExpression() doesn't recognise the modifiers when in the Darwin/MachO 1430 /// syntax form so it is done here. TODO: Determine if there is merit in 1431 /// arranging for this to be done at a higher level. 1432 bool PPCAsmParser:: 1433 ParseDarwinExpression(const MCExpr *&EVal) { 1434 MCAsmParser &Parser = getParser(); 1435 PPCMCExpr::VariantKind Variant = PPCMCExpr::VK_PPC_None; 1436 switch (getLexer().getKind()) { 1437 default: 1438 break; 1439 case AsmToken::Identifier: 1440 // Compiler-generated Darwin identifiers begin with L,l,_ or "; thus 1441 // something starting with any other char should be part of the 1442 // asm syntax. If handwritten asm includes an identifier like lo16, 1443 // then all bets are off - but no-one would do that, right? 1444 StringRef poss = Parser.getTok().getString(); 1445 if (poss.equals_lower("lo16")) { 1446 Variant = PPCMCExpr::VK_PPC_LO; 1447 } else if (poss.equals_lower("hi16")) { 1448 Variant = PPCMCExpr::VK_PPC_HI; 1449 } else if (poss.equals_lower("ha16")) { 1450 Variant = PPCMCExpr::VK_PPC_HA; 1451 } 1452 if (Variant != PPCMCExpr::VK_PPC_None) { 1453 Parser.Lex(); // Eat the xx16 1454 if (getLexer().isNot(AsmToken::LParen)) 1455 return Error(Parser.getTok().getLoc(), "expected '('"); 1456 Parser.Lex(); // Eat the '(' 1457 } 1458 break; 1459 } 1460 1461 if (getParser().parseExpression(EVal)) 1462 return true; 1463 1464 if (Variant != PPCMCExpr::VK_PPC_None) { 1465 if (getLexer().isNot(AsmToken::RParen)) 1466 return Error(Parser.getTok().getLoc(), "expected ')'"); 1467 Parser.Lex(); // Eat the ')' 1468 EVal = PPCMCExpr::create(Variant, EVal, getParser().getContext()); 1469 } 1470 return false; 1471 } 1472 1473 /// ParseOperand 1474 /// This handles registers in the form 'NN', '%rNN' for ELF platforms and 1475 /// rNN for MachO. 1476 bool PPCAsmParser::ParseOperand(OperandVector &Operands) { 1477 MCAsmParser &Parser = getParser(); 1478 SMLoc S = Parser.getTok().getLoc(); 1479 SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1); 1480 const MCExpr *EVal; 1481 1482 // Attempt to parse the next token as an immediate 1483 switch (getLexer().getKind()) { 1484 // Special handling for register names. These are interpreted 1485 // as immediates corresponding to the register number. 1486 case AsmToken::Percent: { 1487 unsigned RegNo; 1488 int64_t IntVal; 1489 if (MatchRegisterName(RegNo, IntVal)) 1490 return Error(S, "invalid register name"); 1491 1492 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1493 return false; 1494 } 1495 case AsmToken::Identifier: 1496 case AsmToken::LParen: 1497 case AsmToken::Plus: 1498 case AsmToken::Minus: 1499 case AsmToken::Integer: 1500 case AsmToken::Dot: 1501 case AsmToken::Dollar: 1502 case AsmToken::Exclaim: 1503 case AsmToken::Tilde: 1504 // Note that non-register-name identifiers from the compiler will begin 1505 // with '_', 'L'/'l' or '"'. Of course, handwritten asm could include 1506 // identifiers like r31foo - so we fall through in the event that parsing 1507 // a register name fails. 1508 if (isDarwin()) { 1509 unsigned RegNo; 1510 int64_t IntVal; 1511 if (!MatchRegisterName(RegNo, IntVal)) { 1512 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1513 return false; 1514 } 1515 } 1516 // All other expressions 1517 1518 if (!ParseExpression(EVal)) 1519 break; 1520 // Fall-through 1521 LLVM_FALLTHROUGH; 1522 default: 1523 return Error(S, "unknown operand"); 1524 } 1525 1526 // Push the parsed operand into the list of operands 1527 Operands.push_back(PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64())); 1528 1529 // Check whether this is a TLS call expression 1530 bool TLSCall = false; 1531 if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal)) 1532 TLSCall = Ref->getSymbol().getName() == "__tls_get_addr"; 1533 1534 if (TLSCall && getLexer().is(AsmToken::LParen)) { 1535 const MCExpr *TLSSym; 1536 1537 Parser.Lex(); // Eat the '('. 1538 S = Parser.getTok().getLoc(); 1539 if (ParseExpression(TLSSym)) 1540 return Error(S, "invalid TLS call expression"); 1541 if (getLexer().isNot(AsmToken::RParen)) 1542 return Error(Parser.getTok().getLoc(), "missing ')'"); 1543 E = Parser.getTok().getLoc(); 1544 Parser.Lex(); // Eat the ')'. 1545 1546 Operands.push_back(PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64())); 1547 } 1548 1549 // Otherwise, check for D-form memory operands 1550 if (!TLSCall && getLexer().is(AsmToken::LParen)) { 1551 Parser.Lex(); // Eat the '('. 1552 S = Parser.getTok().getLoc(); 1553 1554 int64_t IntVal; 1555 switch (getLexer().getKind()) { 1556 case AsmToken::Percent: { 1557 unsigned RegNo; 1558 if (MatchRegisterName(RegNo, IntVal)) 1559 return Error(S, "invalid register name"); 1560 break; 1561 } 1562 case AsmToken::Integer: 1563 if (isDarwin()) 1564 return Error(S, "unexpected integer value"); 1565 else if (getParser().parseAbsoluteExpression(IntVal) || IntVal < 0 || 1566 IntVal > 31) 1567 return Error(S, "invalid register number"); 1568 break; 1569 case AsmToken::Identifier: 1570 if (isDarwin()) { 1571 unsigned RegNo; 1572 if (!MatchRegisterName(RegNo, IntVal)) { 1573 break; 1574 } 1575 } 1576 LLVM_FALLTHROUGH; 1577 1578 default: 1579 return Error(S, "invalid memory operand"); 1580 } 1581 1582 E = Parser.getTok().getLoc(); 1583 if (parseToken(AsmToken::RParen, "missing ')'")) 1584 return true; 1585 Operands.push_back(PPCOperand::CreateImm(IntVal, S, E, isPPC64())); 1586 } 1587 1588 return false; 1589 } 1590 1591 /// Parse an instruction mnemonic followed by its operands. 1592 bool PPCAsmParser::ParseInstruction(ParseInstructionInfo &Info, StringRef Name, 1593 SMLoc NameLoc, OperandVector &Operands) { 1594 // The first operand is the token for the instruction name. 1595 // If the next character is a '+' or '-', we need to add it to the 1596 // instruction name, to match what TableGen is doing. 1597 std::string NewOpcode; 1598 if (parseOptionalToken(AsmToken::Plus)) { 1599 NewOpcode = std::string(Name); 1600 NewOpcode += '+'; 1601 Name = NewOpcode; 1602 } 1603 if (parseOptionalToken(AsmToken::Minus)) { 1604 NewOpcode = std::string(Name); 1605 NewOpcode += '-'; 1606 Name = NewOpcode; 1607 } 1608 // If the instruction ends in a '.', we need to create a separate 1609 // token for it, to match what TableGen is doing. 1610 size_t Dot = Name.find('.'); 1611 StringRef Mnemonic = Name.slice(0, Dot); 1612 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1613 Operands.push_back( 1614 PPCOperand::CreateTokenWithStringCopy(Mnemonic, NameLoc, isPPC64())); 1615 else 1616 Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64())); 1617 if (Dot != StringRef::npos) { 1618 SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot); 1619 StringRef DotStr = Name.slice(Dot, StringRef::npos); 1620 if (!NewOpcode.empty()) // Underlying memory for Name is volatile. 1621 Operands.push_back( 1622 PPCOperand::CreateTokenWithStringCopy(DotStr, DotLoc, isPPC64())); 1623 else 1624 Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64())); 1625 } 1626 1627 // If there are no more operands then finish 1628 if (parseOptionalToken(AsmToken::EndOfStatement)) 1629 return false; 1630 1631 // Parse the first operand 1632 if (ParseOperand(Operands)) 1633 return true; 1634 1635 while (!parseOptionalToken(AsmToken::EndOfStatement)) { 1636 if (parseToken(AsmToken::Comma) || ParseOperand(Operands)) 1637 return true; 1638 } 1639 1640 // We'll now deal with an unfortunate special case: the syntax for the dcbt 1641 // and dcbtst instructions differs for server vs. embedded cores. 1642 // The syntax for dcbt is: 1643 // dcbt ra, rb, th [server] 1644 // dcbt th, ra, rb [embedded] 1645 // where th can be omitted when it is 0. dcbtst is the same. We take the 1646 // server form to be the default, so swap the operands if we're parsing for 1647 // an embedded core (they'll be swapped again upon printing). 1648 if (getSTI().getFeatureBits()[PPC::FeatureBookE] && 1649 Operands.size() == 4 && 1650 (Name == "dcbt" || Name == "dcbtst")) { 1651 std::swap(Operands[1], Operands[3]); 1652 std::swap(Operands[2], Operands[1]); 1653 } 1654 1655 return false; 1656 } 1657 1658 /// ParseDirective parses the PPC specific directives 1659 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) { 1660 StringRef IDVal = DirectiveID.getIdentifier(); 1661 if (isDarwin()) { 1662 if (IDVal == ".machine") 1663 ParseDarwinDirectiveMachine(DirectiveID.getLoc()); 1664 else 1665 return true; 1666 } else if (IDVal == ".word") 1667 ParseDirectiveWord(2, DirectiveID); 1668 else if (IDVal == ".llong") 1669 ParseDirectiveWord(8, DirectiveID); 1670 else if (IDVal == ".tc") 1671 ParseDirectiveTC(isPPC64() ? 8 : 4, DirectiveID); 1672 else if (IDVal == ".machine") 1673 ParseDirectiveMachine(DirectiveID.getLoc()); 1674 else if (IDVal == ".abiversion") 1675 ParseDirectiveAbiVersion(DirectiveID.getLoc()); 1676 else if (IDVal == ".localentry") 1677 ParseDirectiveLocalEntry(DirectiveID.getLoc()); 1678 else 1679 return true; 1680 return false; 1681 } 1682 1683 /// ParseDirectiveWord 1684 /// ::= .word [ expression (, expression)* ] 1685 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, AsmToken ID) { 1686 auto parseOp = [&]() -> bool { 1687 const MCExpr *Value; 1688 SMLoc ExprLoc = getParser().getTok().getLoc(); 1689 if (getParser().parseExpression(Value)) 1690 return true; 1691 if (const auto *MCE = dyn_cast<MCConstantExpr>(Value)) { 1692 assert(Size <= 8 && "Invalid size"); 1693 uint64_t IntValue = MCE->getValue(); 1694 if (!isUIntN(8 * Size, IntValue) && !isIntN(8 * Size, IntValue)) 1695 return Error(ExprLoc, "literal value out of range for '" + 1696 ID.getIdentifier() + "' directive"); 1697 getStreamer().emitIntValue(IntValue, Size); 1698 } else 1699 getStreamer().emitValue(Value, Size, ExprLoc); 1700 return false; 1701 }; 1702 1703 if (parseMany(parseOp)) 1704 return addErrorSuffix(" in '" + ID.getIdentifier() + "' directive"); 1705 return false; 1706 } 1707 1708 /// ParseDirectiveTC 1709 /// ::= .tc [ symbol (, expression)* ] 1710 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, AsmToken ID) { 1711 MCAsmParser &Parser = getParser(); 1712 // Skip TC symbol, which is only used with XCOFF. 1713 while (getLexer().isNot(AsmToken::EndOfStatement) 1714 && getLexer().isNot(AsmToken::Comma)) 1715 Parser.Lex(); 1716 if (parseToken(AsmToken::Comma)) 1717 return addErrorSuffix(" in '.tc' directive"); 1718 1719 // Align to word size. 1720 getParser().getStreamer().emitValueToAlignment(Size); 1721 1722 // Emit expressions. 1723 return ParseDirectiveWord(Size, ID); 1724 } 1725 1726 /// ParseDirectiveMachine (ELF platforms) 1727 /// ::= .machine [ cpu | "push" | "pop" ] 1728 bool PPCAsmParser::ParseDirectiveMachine(SMLoc L) { 1729 MCAsmParser &Parser = getParser(); 1730 if (Parser.getTok().isNot(AsmToken::Identifier) && 1731 Parser.getTok().isNot(AsmToken::String)) 1732 return Error(L, "unexpected token in '.machine' directive"); 1733 1734 StringRef CPU = Parser.getTok().getIdentifier(); 1735 1736 // FIXME: Right now, the parser always allows any available 1737 // instruction, so the .machine directive is not useful. 1738 // Implement ".machine any" (by doing nothing) for the benefit 1739 // of existing assembler code. Likewise, we can then implement 1740 // ".machine push" and ".machine pop" as no-op. 1741 if (CPU != "any" && CPU != "push" && CPU != "pop" && CPU != "ppc64") 1742 return TokError("unrecognized machine type"); 1743 1744 Parser.Lex(); 1745 1746 if (parseToken(AsmToken::EndOfStatement)) 1747 return addErrorSuffix(" in '.machine' directive"); 1748 1749 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1750 getParser().getStreamer().getTargetStreamer()); 1751 if (TStreamer != nullptr) 1752 TStreamer->emitMachine(CPU); 1753 1754 return false; 1755 } 1756 1757 /// ParseDarwinDirectiveMachine (Mach-o platforms) 1758 /// ::= .machine cpu-identifier 1759 bool PPCAsmParser::ParseDarwinDirectiveMachine(SMLoc L) { 1760 MCAsmParser &Parser = getParser(); 1761 if (Parser.getTok().isNot(AsmToken::Identifier) && 1762 Parser.getTok().isNot(AsmToken::String)) 1763 return Error(L, "unexpected token in directive"); 1764 1765 StringRef CPU = Parser.getTok().getIdentifier(); 1766 Parser.Lex(); 1767 1768 // FIXME: this is only the 'default' set of cpu variants. 1769 // However we don't act on this information at present, this is simply 1770 // allowing parsing to proceed with minimal sanity checking. 1771 if (check(CPU != "ppc7400" && CPU != "ppc" && CPU != "ppc64", L, 1772 "unrecognized cpu type") || 1773 check(isPPC64() && (CPU == "ppc7400" || CPU == "ppc"), L, 1774 "wrong cpu type specified for 64bit") || 1775 check(!isPPC64() && CPU == "ppc64", L, 1776 "wrong cpu type specified for 32bit") || 1777 parseToken(AsmToken::EndOfStatement)) 1778 return addErrorSuffix(" in '.machine' directive"); 1779 return false; 1780 } 1781 1782 /// ParseDirectiveAbiVersion 1783 /// ::= .abiversion constant-expression 1784 bool PPCAsmParser::ParseDirectiveAbiVersion(SMLoc L) { 1785 int64_t AbiVersion; 1786 if (check(getParser().parseAbsoluteExpression(AbiVersion), L, 1787 "expected constant expression") || 1788 parseToken(AsmToken::EndOfStatement)) 1789 return addErrorSuffix(" in '.abiversion' directive"); 1790 1791 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1792 getParser().getStreamer().getTargetStreamer()); 1793 if (TStreamer != nullptr) 1794 TStreamer->emitAbiVersion(AbiVersion); 1795 1796 return false; 1797 } 1798 1799 /// ParseDirectiveLocalEntry 1800 /// ::= .localentry symbol, expression 1801 bool PPCAsmParser::ParseDirectiveLocalEntry(SMLoc L) { 1802 StringRef Name; 1803 if (getParser().parseIdentifier(Name)) 1804 return Error(L, "expected identifier in '.localentry' directive"); 1805 1806 MCSymbolELF *Sym = cast<MCSymbolELF>(getContext().getOrCreateSymbol(Name)); 1807 const MCExpr *Expr; 1808 1809 if (parseToken(AsmToken::Comma) || 1810 check(getParser().parseExpression(Expr), L, "expected expression") || 1811 parseToken(AsmToken::EndOfStatement)) 1812 return addErrorSuffix(" in '.localentry' directive"); 1813 1814 PPCTargetStreamer *TStreamer = static_cast<PPCTargetStreamer *>( 1815 getParser().getStreamer().getTargetStreamer()); 1816 if (TStreamer != nullptr) 1817 TStreamer->emitLocalEntry(Sym, Expr); 1818 1819 return false; 1820 } 1821 1822 1823 1824 /// Force static initialization. 1825 extern "C" LLVM_EXTERNAL_VISIBILITY void LLVMInitializePowerPCAsmParser() { 1826 RegisterMCAsmParser<PPCAsmParser> A(getThePPC32Target()); 1827 RegisterMCAsmParser<PPCAsmParser> B(getThePPC64Target()); 1828 RegisterMCAsmParser<PPCAsmParser> C(getThePPC64LETarget()); 1829 } 1830 1831 #define GET_REGISTER_MATCHER 1832 #define GET_MATCHER_IMPLEMENTATION 1833 #define GET_MNEMONIC_SPELL_CHECKER 1834 #include "PPCGenAsmMatcher.inc" 1835 1836 // Define this matcher function after the auto-generated include so we 1837 // have the match class enum definitions. 1838 unsigned PPCAsmParser::validateTargetOperandClass(MCParsedAsmOperand &AsmOp, 1839 unsigned Kind) { 1840 // If the kind is a token for a literal immediate, check if our asm 1841 // operand matches. This is for InstAliases which have a fixed-value 1842 // immediate in the syntax. 1843 int64_t ImmVal; 1844 switch (Kind) { 1845 case MCK_0: ImmVal = 0; break; 1846 case MCK_1: ImmVal = 1; break; 1847 case MCK_2: ImmVal = 2; break; 1848 case MCK_3: ImmVal = 3; break; 1849 case MCK_4: ImmVal = 4; break; 1850 case MCK_5: ImmVal = 5; break; 1851 case MCK_6: ImmVal = 6; break; 1852 case MCK_7: ImmVal = 7; break; 1853 default: return Match_InvalidOperand; 1854 } 1855 1856 PPCOperand &Op = static_cast<PPCOperand &>(AsmOp); 1857 if (Op.isImm() && Op.getImm() == ImmVal) 1858 return Match_Success; 1859 1860 return Match_InvalidOperand; 1861 } 1862 1863 const MCExpr * 1864 PPCAsmParser::applyModifierToExpr(const MCExpr *E, 1865 MCSymbolRefExpr::VariantKind Variant, 1866 MCContext &Ctx) { 1867 switch (Variant) { 1868 case MCSymbolRefExpr::VK_PPC_LO: 1869 return PPCMCExpr::create(PPCMCExpr::VK_PPC_LO, E, Ctx); 1870 case MCSymbolRefExpr::VK_PPC_HI: 1871 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HI, E, Ctx); 1872 case MCSymbolRefExpr::VK_PPC_HA: 1873 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HA, E, Ctx); 1874 case MCSymbolRefExpr::VK_PPC_HIGH: 1875 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGH, E, Ctx); 1876 case MCSymbolRefExpr::VK_PPC_HIGHA: 1877 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHA, E, Ctx); 1878 case MCSymbolRefExpr::VK_PPC_HIGHER: 1879 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHER, E, Ctx); 1880 case MCSymbolRefExpr::VK_PPC_HIGHERA: 1881 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHERA, E, Ctx); 1882 case MCSymbolRefExpr::VK_PPC_HIGHEST: 1883 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHEST, E, Ctx); 1884 case MCSymbolRefExpr::VK_PPC_HIGHESTA: 1885 return PPCMCExpr::create(PPCMCExpr::VK_PPC_HIGHESTA, E, Ctx); 1886 default: 1887 return nullptr; 1888 } 1889 } 1890