1 //===-- PPCAsmParser.cpp - Parse PowerPC asm to MCInst instructions ---------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 
10 #include "MCTargetDesc/PPCMCTargetDesc.h"
11 #include "MCTargetDesc/PPCMCExpr.h"
12 #include "llvm/MC/MCTargetAsmParser.h"
13 #include "llvm/MC/MCStreamer.h"
14 #include "llvm/MC/MCExpr.h"
15 #include "llvm/MC/MCInst.h"
16 #include "llvm/MC/MCRegisterInfo.h"
17 #include "llvm/MC/MCSubtargetInfo.h"
18 #include "llvm/MC/MCParser/MCAsmLexer.h"
19 #include "llvm/MC/MCParser/MCAsmParser.h"
20 #include "llvm/MC/MCParser/MCParsedAsmOperand.h"
21 #include "llvm/ADT/SmallString.h"
22 #include "llvm/ADT/SmallVector.h"
23 #include "llvm/ADT/StringSwitch.h"
24 #include "llvm/ADT/Twine.h"
25 #include "llvm/Support/SourceMgr.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 using namespace llvm;
30 
31 namespace {
32 
33 static unsigned RRegs[32] = {
34   PPC::R0,  PPC::R1,  PPC::R2,  PPC::R3,
35   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
36   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
37   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
38   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
39   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
40   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
41   PPC::R28, PPC::R29, PPC::R30, PPC::R31
42 };
43 static unsigned RRegsNoR0[32] = {
44   PPC::ZERO,
45             PPC::R1,  PPC::R2,  PPC::R3,
46   PPC::R4,  PPC::R5,  PPC::R6,  PPC::R7,
47   PPC::R8,  PPC::R9,  PPC::R10, PPC::R11,
48   PPC::R12, PPC::R13, PPC::R14, PPC::R15,
49   PPC::R16, PPC::R17, PPC::R18, PPC::R19,
50   PPC::R20, PPC::R21, PPC::R22, PPC::R23,
51   PPC::R24, PPC::R25, PPC::R26, PPC::R27,
52   PPC::R28, PPC::R29, PPC::R30, PPC::R31
53 };
54 static unsigned XRegs[32] = {
55   PPC::X0,  PPC::X1,  PPC::X2,  PPC::X3,
56   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
57   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
58   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
59   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
60   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
61   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
62   PPC::X28, PPC::X29, PPC::X30, PPC::X31
63 };
64 static unsigned XRegsNoX0[32] = {
65   PPC::ZERO8,
66             PPC::X1,  PPC::X2,  PPC::X3,
67   PPC::X4,  PPC::X5,  PPC::X6,  PPC::X7,
68   PPC::X8,  PPC::X9,  PPC::X10, PPC::X11,
69   PPC::X12, PPC::X13, PPC::X14, PPC::X15,
70   PPC::X16, PPC::X17, PPC::X18, PPC::X19,
71   PPC::X20, PPC::X21, PPC::X22, PPC::X23,
72   PPC::X24, PPC::X25, PPC::X26, PPC::X27,
73   PPC::X28, PPC::X29, PPC::X30, PPC::X31
74 };
75 static unsigned FRegs[32] = {
76   PPC::F0,  PPC::F1,  PPC::F2,  PPC::F3,
77   PPC::F4,  PPC::F5,  PPC::F6,  PPC::F7,
78   PPC::F8,  PPC::F9,  PPC::F10, PPC::F11,
79   PPC::F12, PPC::F13, PPC::F14, PPC::F15,
80   PPC::F16, PPC::F17, PPC::F18, PPC::F19,
81   PPC::F20, PPC::F21, PPC::F22, PPC::F23,
82   PPC::F24, PPC::F25, PPC::F26, PPC::F27,
83   PPC::F28, PPC::F29, PPC::F30, PPC::F31
84 };
85 static unsigned VRegs[32] = {
86   PPC::V0,  PPC::V1,  PPC::V2,  PPC::V3,
87   PPC::V4,  PPC::V5,  PPC::V6,  PPC::V7,
88   PPC::V8,  PPC::V9,  PPC::V10, PPC::V11,
89   PPC::V12, PPC::V13, PPC::V14, PPC::V15,
90   PPC::V16, PPC::V17, PPC::V18, PPC::V19,
91   PPC::V20, PPC::V21, PPC::V22, PPC::V23,
92   PPC::V24, PPC::V25, PPC::V26, PPC::V27,
93   PPC::V28, PPC::V29, PPC::V30, PPC::V31
94 };
95 static unsigned CRBITRegs[32] = {
96   PPC::CR0LT, PPC::CR0GT, PPC::CR0EQ, PPC::CR0UN,
97   PPC::CR1LT, PPC::CR1GT, PPC::CR1EQ, PPC::CR1UN,
98   PPC::CR2LT, PPC::CR2GT, PPC::CR2EQ, PPC::CR2UN,
99   PPC::CR3LT, PPC::CR3GT, PPC::CR3EQ, PPC::CR3UN,
100   PPC::CR4LT, PPC::CR4GT, PPC::CR4EQ, PPC::CR4UN,
101   PPC::CR5LT, PPC::CR5GT, PPC::CR5EQ, PPC::CR5UN,
102   PPC::CR6LT, PPC::CR6GT, PPC::CR6EQ, PPC::CR6UN,
103   PPC::CR7LT, PPC::CR7GT, PPC::CR7EQ, PPC::CR7UN
104 };
105 static unsigned CRRegs[8] = {
106   PPC::CR0, PPC::CR1, PPC::CR2, PPC::CR3,
107   PPC::CR4, PPC::CR5, PPC::CR6, PPC::CR7
108 };
109 
110 // Evaluate an expression containing condition register
111 // or condition register field symbols.  Returns positive
112 // value on success, or -1 on error.
113 static int64_t
114 EvaluateCRExpr(const MCExpr *E) {
115   switch (E->getKind()) {
116   case MCExpr::Target:
117     return -1;
118 
119   case MCExpr::Constant: {
120     int64_t Res = cast<MCConstantExpr>(E)->getValue();
121     return Res < 0 ? -1 : Res;
122   }
123 
124   case MCExpr::SymbolRef: {
125     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
126     StringRef Name = SRE->getSymbol().getName();
127 
128     if (Name == "lt") return 0;
129     if (Name == "gt") return 1;
130     if (Name == "eq") return 2;
131     if (Name == "so") return 3;
132     if (Name == "un") return 3;
133 
134     if (Name == "cr0") return 0;
135     if (Name == "cr1") return 1;
136     if (Name == "cr2") return 2;
137     if (Name == "cr3") return 3;
138     if (Name == "cr4") return 4;
139     if (Name == "cr5") return 5;
140     if (Name == "cr6") return 6;
141     if (Name == "cr7") return 7;
142 
143     return -1;
144   }
145 
146   case MCExpr::Unary:
147     return -1;
148 
149   case MCExpr::Binary: {
150     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
151     int64_t LHSVal = EvaluateCRExpr(BE->getLHS());
152     int64_t RHSVal = EvaluateCRExpr(BE->getRHS());
153     int64_t Res;
154 
155     if (LHSVal < 0 || RHSVal < 0)
156       return -1;
157 
158     switch (BE->getOpcode()) {
159     default: return -1;
160     case MCBinaryExpr::Add: Res = LHSVal + RHSVal; break;
161     case MCBinaryExpr::Mul: Res = LHSVal * RHSVal; break;
162     }
163 
164     return Res < 0 ? -1 : Res;
165   }
166   }
167 
168   llvm_unreachable("Invalid expression kind!");
169 }
170 
171 struct PPCOperand;
172 
173 class PPCAsmParser : public MCTargetAsmParser {
174   MCSubtargetInfo &STI;
175   MCAsmParser &Parser;
176   bool IsPPC64;
177 
178   MCAsmParser &getParser() const { return Parser; }
179   MCAsmLexer &getLexer() const { return Parser.getLexer(); }
180 
181   void Warning(SMLoc L, const Twine &Msg) { Parser.Warning(L, Msg); }
182   bool Error(SMLoc L, const Twine &Msg) { return Parser.Error(L, Msg); }
183 
184   bool isPPC64() const { return IsPPC64; }
185 
186   bool MatchRegisterName(const AsmToken &Tok,
187                          unsigned &RegNo, int64_t &IntVal);
188 
189   virtual bool ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc);
190 
191   const MCExpr *ExtractModifierFromExpr(const MCExpr *E,
192                                         PPCMCExpr::VariantKind &Variant);
193   bool ParseExpression(const MCExpr *&EVal);
194 
195   bool ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands);
196 
197   bool ParseDirectiveWord(unsigned Size, SMLoc L);
198   bool ParseDirectiveTC(unsigned Size, SMLoc L);
199 
200   bool MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
201                                SmallVectorImpl<MCParsedAsmOperand*> &Operands,
202                                MCStreamer &Out, unsigned &ErrorInfo,
203                                bool MatchingInlineAsm);
204 
205   void ProcessInstruction(MCInst &Inst,
206                           const SmallVectorImpl<MCParsedAsmOperand*> &Ops);
207 
208   /// @name Auto-generated Match Functions
209   /// {
210 
211 #define GET_ASSEMBLER_HEADER
212 #include "PPCGenAsmMatcher.inc"
213 
214   /// }
215 
216 
217 public:
218   PPCAsmParser(MCSubtargetInfo &_STI, MCAsmParser &_Parser)
219     : MCTargetAsmParser(), STI(_STI), Parser(_Parser) {
220     // Check for 64-bit vs. 32-bit pointer mode.
221     Triple TheTriple(STI.getTargetTriple());
222     IsPPC64 = TheTriple.getArch() == Triple::ppc64;
223     // Initialize the set of available features.
224     setAvailableFeatures(ComputeAvailableFeatures(STI.getFeatureBits()));
225   }
226 
227   virtual bool ParseInstruction(ParseInstructionInfo &Info,
228                                 StringRef Name, SMLoc NameLoc,
229                                 SmallVectorImpl<MCParsedAsmOperand*> &Operands);
230 
231   virtual bool ParseDirective(AsmToken DirectiveID);
232 };
233 
234 /// PPCOperand - Instances of this class represent a parsed PowerPC machine
235 /// instruction.
236 struct PPCOperand : public MCParsedAsmOperand {
237   enum KindTy {
238     Token,
239     Immediate,
240     Expression,
241     TLSRegister
242   } Kind;
243 
244   SMLoc StartLoc, EndLoc;
245   bool IsPPC64;
246 
247   struct TokOp {
248     const char *Data;
249     unsigned Length;
250   };
251 
252   struct ImmOp {
253     int64_t Val;
254   };
255 
256   struct ExprOp {
257     const MCExpr *Val;
258     int64_t CRVal;     // Cached result of EvaluateCRExpr(Val)
259   };
260 
261   struct TLSRegOp {
262     const MCSymbolRefExpr *Sym;
263   };
264 
265   union {
266     struct TokOp Tok;
267     struct ImmOp Imm;
268     struct ExprOp Expr;
269     struct TLSRegOp TLSReg;
270   };
271 
272   PPCOperand(KindTy K) : MCParsedAsmOperand(), Kind(K) {}
273 public:
274   PPCOperand(const PPCOperand &o) : MCParsedAsmOperand() {
275     Kind = o.Kind;
276     StartLoc = o.StartLoc;
277     EndLoc = o.EndLoc;
278     IsPPC64 = o.IsPPC64;
279     switch (Kind) {
280     case Token:
281       Tok = o.Tok;
282       break;
283     case Immediate:
284       Imm = o.Imm;
285       break;
286     case Expression:
287       Expr = o.Expr;
288       break;
289     case TLSRegister:
290       TLSReg = o.TLSReg;
291       break;
292     }
293   }
294 
295   /// getStartLoc - Get the location of the first token of this operand.
296   SMLoc getStartLoc() const { return StartLoc; }
297 
298   /// getEndLoc - Get the location of the last token of this operand.
299   SMLoc getEndLoc() const { return EndLoc; }
300 
301   /// isPPC64 - True if this operand is for an instruction in 64-bit mode.
302   bool isPPC64() const { return IsPPC64; }
303 
304   int64_t getImm() const {
305     assert(Kind == Immediate && "Invalid access!");
306     return Imm.Val;
307   }
308 
309   const MCExpr *getExpr() const {
310     assert(Kind == Expression && "Invalid access!");
311     return Expr.Val;
312   }
313 
314   int64_t getExprCRVal() const {
315     assert(Kind == Expression && "Invalid access!");
316     return Expr.CRVal;
317   }
318 
319   const MCExpr *getTLSReg() const {
320     assert(Kind == TLSRegister && "Invalid access!");
321     return TLSReg.Sym;
322   }
323 
324   unsigned getReg() const {
325     assert(isRegNumber() && "Invalid access!");
326     return (unsigned) Imm.Val;
327   }
328 
329   unsigned getCCReg() const {
330     assert(isCCRegNumber() && "Invalid access!");
331     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
332   }
333 
334   unsigned getCRBit() const {
335     assert(isCRBitNumber() && "Invalid access!");
336     return (unsigned) (Kind == Immediate ? Imm.Val : Expr.CRVal);
337   }
338 
339   unsigned getCRBitMask() const {
340     assert(isCRBitMask() && "Invalid access!");
341     return 7 - countTrailingZeros<uint64_t>(Imm.Val);
342   }
343 
344   bool isToken() const { return Kind == Token; }
345   bool isImm() const { return Kind == Immediate || Kind == Expression; }
346   bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); }
347   bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); }
348   bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); }
349   bool isU16Imm() const { return Kind == Expression ||
350                                  (Kind == Immediate && isUInt<16>(getImm())); }
351   bool isS16Imm() const { return Kind == Expression ||
352                                  (Kind == Immediate && isInt<16>(getImm())); }
353   bool isS16ImmX4() const { return Kind == Expression ||
354                                    (Kind == Immediate && isInt<16>(getImm()) &&
355                                     (getImm() & 3) == 0); }
356   bool isS17Imm() const { return Kind == Expression ||
357                                  (Kind == Immediate && isInt<17>(getImm())); }
358   bool isTLSReg() const { return Kind == TLSRegister; }
359   bool isDirectBr() const { return Kind == Expression ||
360                                    (Kind == Immediate && isInt<26>(getImm()) &&
361                                     (getImm() & 3) == 0); }
362   bool isCondBr() const { return Kind == Expression ||
363                                  (Kind == Immediate && isInt<16>(getImm()) &&
364                                   (getImm() & 3) == 0); }
365   bool isRegNumber() const { return Kind == Immediate && isUInt<5>(getImm()); }
366   bool isCCRegNumber() const { return (Kind == Expression
367                                        && isUInt<3>(getExprCRVal())) ||
368                                       (Kind == Immediate
369                                        && isUInt<3>(getImm())); }
370   bool isCRBitNumber() const { return (Kind == Expression
371                                        && isUInt<5>(getExprCRVal())) ||
372                                       (Kind == Immediate
373                                        && isUInt<5>(getImm())); }
374   bool isCRBitMask() const { return Kind == Immediate && isUInt<8>(getImm()) &&
375                                     isPowerOf2_32(getImm()); }
376   bool isMem() const { return false; }
377   bool isReg() const { return false; }
378 
379   void addRegOperands(MCInst &Inst, unsigned N) const {
380     llvm_unreachable("addRegOperands");
381   }
382 
383   void addRegGPRCOperands(MCInst &Inst, unsigned N) const {
384     assert(N == 1 && "Invalid number of operands!");
385     Inst.addOperand(MCOperand::CreateReg(RRegs[getReg()]));
386   }
387 
388   void addRegGPRCNoR0Operands(MCInst &Inst, unsigned N) const {
389     assert(N == 1 && "Invalid number of operands!");
390     Inst.addOperand(MCOperand::CreateReg(RRegsNoR0[getReg()]));
391   }
392 
393   void addRegG8RCOperands(MCInst &Inst, unsigned N) const {
394     assert(N == 1 && "Invalid number of operands!");
395     Inst.addOperand(MCOperand::CreateReg(XRegs[getReg()]));
396   }
397 
398   void addRegG8RCNoX0Operands(MCInst &Inst, unsigned N) const {
399     assert(N == 1 && "Invalid number of operands!");
400     Inst.addOperand(MCOperand::CreateReg(XRegsNoX0[getReg()]));
401   }
402 
403   void addRegGxRCOperands(MCInst &Inst, unsigned N) const {
404     if (isPPC64())
405       addRegG8RCOperands(Inst, N);
406     else
407       addRegGPRCOperands(Inst, N);
408   }
409 
410   void addRegGxRCNoR0Operands(MCInst &Inst, unsigned N) const {
411     if (isPPC64())
412       addRegG8RCNoX0Operands(Inst, N);
413     else
414       addRegGPRCNoR0Operands(Inst, N);
415   }
416 
417   void addRegF4RCOperands(MCInst &Inst, unsigned N) const {
418     assert(N == 1 && "Invalid number of operands!");
419     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
420   }
421 
422   void addRegF8RCOperands(MCInst &Inst, unsigned N) const {
423     assert(N == 1 && "Invalid number of operands!");
424     Inst.addOperand(MCOperand::CreateReg(FRegs[getReg()]));
425   }
426 
427   void addRegVRRCOperands(MCInst &Inst, unsigned N) const {
428     assert(N == 1 && "Invalid number of operands!");
429     Inst.addOperand(MCOperand::CreateReg(VRegs[getReg()]));
430   }
431 
432   void addRegCRBITRCOperands(MCInst &Inst, unsigned N) const {
433     assert(N == 1 && "Invalid number of operands!");
434     Inst.addOperand(MCOperand::CreateReg(CRBITRegs[getCRBit()]));
435   }
436 
437   void addRegCRRCOperands(MCInst &Inst, unsigned N) const {
438     assert(N == 1 && "Invalid number of operands!");
439     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCCReg()]));
440   }
441 
442   void addCRBitMaskOperands(MCInst &Inst, unsigned N) const {
443     assert(N == 1 && "Invalid number of operands!");
444     Inst.addOperand(MCOperand::CreateReg(CRRegs[getCRBitMask()]));
445   }
446 
447   void addImmOperands(MCInst &Inst, unsigned N) const {
448     assert(N == 1 && "Invalid number of operands!");
449     if (Kind == Immediate)
450       Inst.addOperand(MCOperand::CreateImm(getImm()));
451     else
452       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
453   }
454 
455   void addBranchTargetOperands(MCInst &Inst, unsigned N) const {
456     assert(N == 1 && "Invalid number of operands!");
457     if (Kind == Immediate)
458       Inst.addOperand(MCOperand::CreateImm(getImm() / 4));
459     else
460       Inst.addOperand(MCOperand::CreateExpr(getExpr()));
461   }
462 
463   void addTLSRegOperands(MCInst &Inst, unsigned N) const {
464     assert(N == 1 && "Invalid number of operands!");
465     Inst.addOperand(MCOperand::CreateExpr(getTLSReg()));
466   }
467 
468   StringRef getToken() const {
469     assert(Kind == Token && "Invalid access!");
470     return StringRef(Tok.Data, Tok.Length);
471   }
472 
473   virtual void print(raw_ostream &OS) const;
474 
475   static PPCOperand *CreateToken(StringRef Str, SMLoc S, bool IsPPC64) {
476     PPCOperand *Op = new PPCOperand(Token);
477     Op->Tok.Data = Str.data();
478     Op->Tok.Length = Str.size();
479     Op->StartLoc = S;
480     Op->EndLoc = S;
481     Op->IsPPC64 = IsPPC64;
482     return Op;
483   }
484 
485   static PPCOperand *CreateImm(int64_t Val, SMLoc S, SMLoc E, bool IsPPC64) {
486     PPCOperand *Op = new PPCOperand(Immediate);
487     Op->Imm.Val = Val;
488     Op->StartLoc = S;
489     Op->EndLoc = E;
490     Op->IsPPC64 = IsPPC64;
491     return Op;
492   }
493 
494   static PPCOperand *CreateExpr(const MCExpr *Val,
495                                 SMLoc S, SMLoc E, bool IsPPC64) {
496     PPCOperand *Op = new PPCOperand(Expression);
497     Op->Expr.Val = Val;
498     Op->Expr.CRVal = EvaluateCRExpr(Val);
499     Op->StartLoc = S;
500     Op->EndLoc = E;
501     Op->IsPPC64 = IsPPC64;
502     return Op;
503   }
504 
505   static PPCOperand *CreateTLSReg(const MCSymbolRefExpr *Sym,
506                                   SMLoc S, SMLoc E, bool IsPPC64) {
507     PPCOperand *Op = new PPCOperand(TLSRegister);
508     Op->TLSReg.Sym = Sym;
509     Op->StartLoc = S;
510     Op->EndLoc = E;
511     Op->IsPPC64 = IsPPC64;
512     return Op;
513   }
514 
515   static PPCOperand *CreateFromMCExpr(const MCExpr *Val,
516                                       SMLoc S, SMLoc E, bool IsPPC64) {
517     if (const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(Val))
518       return CreateImm(CE->getValue(), S, E, IsPPC64);
519 
520     if (const MCSymbolRefExpr *SRE = dyn_cast<MCSymbolRefExpr>(Val))
521       if (SRE->getKind() == MCSymbolRefExpr::VK_PPC_TLS)
522         return CreateTLSReg(SRE, S, E, IsPPC64);
523 
524     return CreateExpr(Val, S, E, IsPPC64);
525   }
526 };
527 
528 } // end anonymous namespace.
529 
530 void PPCOperand::print(raw_ostream &OS) const {
531   switch (Kind) {
532   case Token:
533     OS << "'" << getToken() << "'";
534     break;
535   case Immediate:
536     OS << getImm();
537     break;
538   case Expression:
539     getExpr()->print(OS);
540     break;
541   case TLSRegister:
542     getTLSReg()->print(OS);
543     break;
544   }
545 }
546 
547 
548 void PPCAsmParser::
549 ProcessInstruction(MCInst &Inst,
550                    const SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
551   int Opcode = Inst.getOpcode();
552   switch (Opcode) {
553   case PPC::LAx: {
554     MCInst TmpInst;
555     TmpInst.setOpcode(PPC::LA);
556     TmpInst.addOperand(Inst.getOperand(0));
557     TmpInst.addOperand(Inst.getOperand(2));
558     TmpInst.addOperand(Inst.getOperand(1));
559     Inst = TmpInst;
560     break;
561   }
562   case PPC::SUBI: {
563     MCInst TmpInst;
564     int64_t N = Inst.getOperand(2).getImm();
565     TmpInst.setOpcode(PPC::ADDI);
566     TmpInst.addOperand(Inst.getOperand(0));
567     TmpInst.addOperand(Inst.getOperand(1));
568     TmpInst.addOperand(MCOperand::CreateImm(-N));
569     Inst = TmpInst;
570     break;
571   }
572   case PPC::SUBIS: {
573     MCInst TmpInst;
574     int64_t N = Inst.getOperand(2).getImm();
575     TmpInst.setOpcode(PPC::ADDIS);
576     TmpInst.addOperand(Inst.getOperand(0));
577     TmpInst.addOperand(Inst.getOperand(1));
578     TmpInst.addOperand(MCOperand::CreateImm(-N));
579     Inst = TmpInst;
580     break;
581   }
582   case PPC::SUBIC: {
583     MCInst TmpInst;
584     int64_t N = Inst.getOperand(2).getImm();
585     TmpInst.setOpcode(PPC::ADDIC);
586     TmpInst.addOperand(Inst.getOperand(0));
587     TmpInst.addOperand(Inst.getOperand(1));
588     TmpInst.addOperand(MCOperand::CreateImm(-N));
589     Inst = TmpInst;
590     break;
591   }
592   case PPC::SUBICo: {
593     MCInst TmpInst;
594     int64_t N = Inst.getOperand(2).getImm();
595     TmpInst.setOpcode(PPC::ADDICo);
596     TmpInst.addOperand(Inst.getOperand(0));
597     TmpInst.addOperand(Inst.getOperand(1));
598     TmpInst.addOperand(MCOperand::CreateImm(-N));
599     Inst = TmpInst;
600     break;
601   }
602   case PPC::EXTLWI:
603   case PPC::EXTLWIo: {
604     MCInst TmpInst;
605     int64_t N = Inst.getOperand(2).getImm();
606     int64_t B = Inst.getOperand(3).getImm();
607     TmpInst.setOpcode(Opcode == PPC::EXTLWI? PPC::RLWINM : PPC::RLWINMo);
608     TmpInst.addOperand(Inst.getOperand(0));
609     TmpInst.addOperand(Inst.getOperand(1));
610     TmpInst.addOperand(MCOperand::CreateImm(B));
611     TmpInst.addOperand(MCOperand::CreateImm(0));
612     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
613     Inst = TmpInst;
614     break;
615   }
616   case PPC::EXTRWI:
617   case PPC::EXTRWIo: {
618     MCInst TmpInst;
619     int64_t N = Inst.getOperand(2).getImm();
620     int64_t B = Inst.getOperand(3).getImm();
621     TmpInst.setOpcode(Opcode == PPC::EXTRWI? PPC::RLWINM : PPC::RLWINMo);
622     TmpInst.addOperand(Inst.getOperand(0));
623     TmpInst.addOperand(Inst.getOperand(1));
624     TmpInst.addOperand(MCOperand::CreateImm(B + N));
625     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
626     TmpInst.addOperand(MCOperand::CreateImm(31));
627     Inst = TmpInst;
628     break;
629   }
630   case PPC::INSLWI:
631   case PPC::INSLWIo: {
632     MCInst TmpInst;
633     int64_t N = Inst.getOperand(2).getImm();
634     int64_t B = Inst.getOperand(3).getImm();
635     TmpInst.setOpcode(Opcode == PPC::INSLWI? PPC::RLWIMI : PPC::RLWIMIo);
636     TmpInst.addOperand(Inst.getOperand(0));
637     TmpInst.addOperand(Inst.getOperand(0));
638     TmpInst.addOperand(Inst.getOperand(1));
639     TmpInst.addOperand(MCOperand::CreateImm(32 - B));
640     TmpInst.addOperand(MCOperand::CreateImm(B));
641     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
642     Inst = TmpInst;
643     break;
644   }
645   case PPC::INSRWI:
646   case PPC::INSRWIo: {
647     MCInst TmpInst;
648     int64_t N = Inst.getOperand(2).getImm();
649     int64_t B = Inst.getOperand(3).getImm();
650     TmpInst.setOpcode(Opcode == PPC::INSRWI? PPC::RLWIMI : PPC::RLWIMIo);
651     TmpInst.addOperand(Inst.getOperand(0));
652     TmpInst.addOperand(Inst.getOperand(0));
653     TmpInst.addOperand(Inst.getOperand(1));
654     TmpInst.addOperand(MCOperand::CreateImm(32 - (B + N)));
655     TmpInst.addOperand(MCOperand::CreateImm(B));
656     TmpInst.addOperand(MCOperand::CreateImm((B + N) - 1));
657     Inst = TmpInst;
658     break;
659   }
660   case PPC::ROTRWI:
661   case PPC::ROTRWIo: {
662     MCInst TmpInst;
663     int64_t N = Inst.getOperand(2).getImm();
664     TmpInst.setOpcode(Opcode == PPC::ROTRWI? PPC::RLWINM : PPC::RLWINMo);
665     TmpInst.addOperand(Inst.getOperand(0));
666     TmpInst.addOperand(Inst.getOperand(1));
667     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
668     TmpInst.addOperand(MCOperand::CreateImm(0));
669     TmpInst.addOperand(MCOperand::CreateImm(31));
670     Inst = TmpInst;
671     break;
672   }
673   case PPC::SLWI:
674   case PPC::SLWIo: {
675     MCInst TmpInst;
676     int64_t N = Inst.getOperand(2).getImm();
677     TmpInst.setOpcode(Opcode == PPC::SLWI? PPC::RLWINM : PPC::RLWINMo);
678     TmpInst.addOperand(Inst.getOperand(0));
679     TmpInst.addOperand(Inst.getOperand(1));
680     TmpInst.addOperand(MCOperand::CreateImm(N));
681     TmpInst.addOperand(MCOperand::CreateImm(0));
682     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
683     Inst = TmpInst;
684     break;
685   }
686   case PPC::SRWI:
687   case PPC::SRWIo: {
688     MCInst TmpInst;
689     int64_t N = Inst.getOperand(2).getImm();
690     TmpInst.setOpcode(Opcode == PPC::SRWI? PPC::RLWINM : PPC::RLWINMo);
691     TmpInst.addOperand(Inst.getOperand(0));
692     TmpInst.addOperand(Inst.getOperand(1));
693     TmpInst.addOperand(MCOperand::CreateImm(32 - N));
694     TmpInst.addOperand(MCOperand::CreateImm(N));
695     TmpInst.addOperand(MCOperand::CreateImm(31));
696     Inst = TmpInst;
697     break;
698   }
699   case PPC::CLRRWI:
700   case PPC::CLRRWIo: {
701     MCInst TmpInst;
702     int64_t N = Inst.getOperand(2).getImm();
703     TmpInst.setOpcode(Opcode == PPC::CLRRWI? PPC::RLWINM : PPC::RLWINMo);
704     TmpInst.addOperand(Inst.getOperand(0));
705     TmpInst.addOperand(Inst.getOperand(1));
706     TmpInst.addOperand(MCOperand::CreateImm(0));
707     TmpInst.addOperand(MCOperand::CreateImm(0));
708     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
709     Inst = TmpInst;
710     break;
711   }
712   case PPC::CLRLSLWI:
713   case PPC::CLRLSLWIo: {
714     MCInst TmpInst;
715     int64_t B = Inst.getOperand(2).getImm();
716     int64_t N = Inst.getOperand(3).getImm();
717     TmpInst.setOpcode(Opcode == PPC::CLRLSLWI? PPC::RLWINM : PPC::RLWINMo);
718     TmpInst.addOperand(Inst.getOperand(0));
719     TmpInst.addOperand(Inst.getOperand(1));
720     TmpInst.addOperand(MCOperand::CreateImm(N));
721     TmpInst.addOperand(MCOperand::CreateImm(B - N));
722     TmpInst.addOperand(MCOperand::CreateImm(31 - N));
723     Inst = TmpInst;
724     break;
725   }
726   case PPC::EXTLDI:
727   case PPC::EXTLDIo: {
728     MCInst TmpInst;
729     int64_t N = Inst.getOperand(2).getImm();
730     int64_t B = Inst.getOperand(3).getImm();
731     TmpInst.setOpcode(Opcode == PPC::EXTLDI? PPC::RLDICR : PPC::RLDICRo);
732     TmpInst.addOperand(Inst.getOperand(0));
733     TmpInst.addOperand(Inst.getOperand(1));
734     TmpInst.addOperand(MCOperand::CreateImm(B));
735     TmpInst.addOperand(MCOperand::CreateImm(N - 1));
736     Inst = TmpInst;
737     break;
738   }
739   case PPC::EXTRDI:
740   case PPC::EXTRDIo: {
741     MCInst TmpInst;
742     int64_t N = Inst.getOperand(2).getImm();
743     int64_t B = Inst.getOperand(3).getImm();
744     TmpInst.setOpcode(Opcode == PPC::EXTRDI? PPC::RLDICL : PPC::RLDICLo);
745     TmpInst.addOperand(Inst.getOperand(0));
746     TmpInst.addOperand(Inst.getOperand(1));
747     TmpInst.addOperand(MCOperand::CreateImm(B + N));
748     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
749     Inst = TmpInst;
750     break;
751   }
752   case PPC::INSRDI:
753   case PPC::INSRDIo: {
754     MCInst TmpInst;
755     int64_t N = Inst.getOperand(2).getImm();
756     int64_t B = Inst.getOperand(3).getImm();
757     TmpInst.setOpcode(Opcode == PPC::INSRDI? PPC::RLDIMI : PPC::RLDIMIo);
758     TmpInst.addOperand(Inst.getOperand(0));
759     TmpInst.addOperand(Inst.getOperand(0));
760     TmpInst.addOperand(Inst.getOperand(1));
761     TmpInst.addOperand(MCOperand::CreateImm(64 - (B + N)));
762     TmpInst.addOperand(MCOperand::CreateImm(B));
763     Inst = TmpInst;
764     break;
765   }
766   case PPC::ROTRDI:
767   case PPC::ROTRDIo: {
768     MCInst TmpInst;
769     int64_t N = Inst.getOperand(2).getImm();
770     TmpInst.setOpcode(Opcode == PPC::ROTRDI? PPC::RLDICL : PPC::RLDICLo);
771     TmpInst.addOperand(Inst.getOperand(0));
772     TmpInst.addOperand(Inst.getOperand(1));
773     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
774     TmpInst.addOperand(MCOperand::CreateImm(0));
775     Inst = TmpInst;
776     break;
777   }
778   case PPC::SLDI:
779   case PPC::SLDIo: {
780     MCInst TmpInst;
781     int64_t N = Inst.getOperand(2).getImm();
782     TmpInst.setOpcode(Opcode == PPC::SLDI? PPC::RLDICR : PPC::RLDICRo);
783     TmpInst.addOperand(Inst.getOperand(0));
784     TmpInst.addOperand(Inst.getOperand(1));
785     TmpInst.addOperand(MCOperand::CreateImm(N));
786     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
787     Inst = TmpInst;
788     break;
789   }
790   case PPC::SRDI:
791   case PPC::SRDIo: {
792     MCInst TmpInst;
793     int64_t N = Inst.getOperand(2).getImm();
794     TmpInst.setOpcode(Opcode == PPC::SRDI? PPC::RLDICL : PPC::RLDICLo);
795     TmpInst.addOperand(Inst.getOperand(0));
796     TmpInst.addOperand(Inst.getOperand(1));
797     TmpInst.addOperand(MCOperand::CreateImm(64 - N));
798     TmpInst.addOperand(MCOperand::CreateImm(N));
799     Inst = TmpInst;
800     break;
801   }
802   case PPC::CLRRDI:
803   case PPC::CLRRDIo: {
804     MCInst TmpInst;
805     int64_t N = Inst.getOperand(2).getImm();
806     TmpInst.setOpcode(Opcode == PPC::CLRRDI? PPC::RLDICR : PPC::RLDICRo);
807     TmpInst.addOperand(Inst.getOperand(0));
808     TmpInst.addOperand(Inst.getOperand(1));
809     TmpInst.addOperand(MCOperand::CreateImm(0));
810     TmpInst.addOperand(MCOperand::CreateImm(63 - N));
811     Inst = TmpInst;
812     break;
813   }
814   case PPC::CLRLSLDI:
815   case PPC::CLRLSLDIo: {
816     MCInst TmpInst;
817     int64_t B = Inst.getOperand(2).getImm();
818     int64_t N = Inst.getOperand(3).getImm();
819     TmpInst.setOpcode(Opcode == PPC::CLRLSLDI? PPC::RLDIC : PPC::RLDICo);
820     TmpInst.addOperand(Inst.getOperand(0));
821     TmpInst.addOperand(Inst.getOperand(1));
822     TmpInst.addOperand(MCOperand::CreateImm(N));
823     TmpInst.addOperand(MCOperand::CreateImm(B - N));
824     Inst = TmpInst;
825     break;
826   }
827   }
828 }
829 
830 bool PPCAsmParser::
831 MatchAndEmitInstruction(SMLoc IDLoc, unsigned &Opcode,
832                         SmallVectorImpl<MCParsedAsmOperand*> &Operands,
833                         MCStreamer &Out, unsigned &ErrorInfo,
834                         bool MatchingInlineAsm) {
835   MCInst Inst;
836 
837   switch (MatchInstructionImpl(Operands, Inst, ErrorInfo, MatchingInlineAsm)) {
838   default: break;
839   case Match_Success:
840     // Post-process instructions (typically extended mnemonics)
841     ProcessInstruction(Inst, Operands);
842     Inst.setLoc(IDLoc);
843     Out.EmitInstruction(Inst);
844     return false;
845   case Match_MissingFeature:
846     return Error(IDLoc, "instruction use requires an option to be enabled");
847   case Match_MnemonicFail:
848       return Error(IDLoc, "unrecognized instruction mnemonic");
849   case Match_InvalidOperand: {
850     SMLoc ErrorLoc = IDLoc;
851     if (ErrorInfo != ~0U) {
852       if (ErrorInfo >= Operands.size())
853         return Error(IDLoc, "too few operands for instruction");
854 
855       ErrorLoc = ((PPCOperand*)Operands[ErrorInfo])->getStartLoc();
856       if (ErrorLoc == SMLoc()) ErrorLoc = IDLoc;
857     }
858 
859     return Error(ErrorLoc, "invalid operand for instruction");
860   }
861   }
862 
863   llvm_unreachable("Implement any new match types added!");
864 }
865 
866 bool PPCAsmParser::
867 MatchRegisterName(const AsmToken &Tok, unsigned &RegNo, int64_t &IntVal) {
868   if (Tok.is(AsmToken::Identifier)) {
869     StringRef Name = Tok.getString();
870 
871     if (Name.equals_lower("lr")) {
872       RegNo = isPPC64()? PPC::LR8 : PPC::LR;
873       IntVal = 8;
874       return false;
875     } else if (Name.equals_lower("ctr")) {
876       RegNo = isPPC64()? PPC::CTR8 : PPC::CTR;
877       IntVal = 9;
878       return false;
879     } else if (Name.equals_lower("vrsave")) {
880       RegNo = PPC::VRSAVE;
881       IntVal = 256;
882       return false;
883     } else if (Name.substr(0, 1).equals_lower("r") &&
884                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
885       RegNo = isPPC64()? XRegs[IntVal] : RRegs[IntVal];
886       return false;
887     } else if (Name.substr(0, 1).equals_lower("f") &&
888                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
889       RegNo = FRegs[IntVal];
890       return false;
891     } else if (Name.substr(0, 1).equals_lower("v") &&
892                !Name.substr(1).getAsInteger(10, IntVal) && IntVal < 32) {
893       RegNo = VRegs[IntVal];
894       return false;
895     } else if (Name.substr(0, 2).equals_lower("cr") &&
896                !Name.substr(2).getAsInteger(10, IntVal) && IntVal < 8) {
897       RegNo = CRRegs[IntVal];
898       return false;
899     }
900   }
901 
902   return true;
903 }
904 
905 bool PPCAsmParser::
906 ParseRegister(unsigned &RegNo, SMLoc &StartLoc, SMLoc &EndLoc) {
907   const AsmToken &Tok = Parser.getTok();
908   StartLoc = Tok.getLoc();
909   EndLoc = Tok.getEndLoc();
910   RegNo = 0;
911   int64_t IntVal;
912 
913   if (!MatchRegisterName(Tok, RegNo, IntVal)) {
914     Parser.Lex(); // Eat identifier token.
915     return false;
916   }
917 
918   return Error(StartLoc, "invalid register name");
919 }
920 
921 /// Extract \code @l/@ha \endcode modifier from expression.  Recursively scan
922 /// the expression and check for VK_PPC_LO/HI/HA
923 /// symbol variants.  If all symbols with modifier use the same
924 /// variant, return the corresponding PPCMCExpr::VariantKind,
925 /// and a modified expression using the default symbol variant.
926 /// Otherwise, return NULL.
927 const MCExpr *PPCAsmParser::
928 ExtractModifierFromExpr(const MCExpr *E,
929                         PPCMCExpr::VariantKind &Variant) {
930   MCContext &Context = getParser().getContext();
931   Variant = PPCMCExpr::VK_PPC_None;
932 
933   switch (E->getKind()) {
934   case MCExpr::Target:
935   case MCExpr::Constant:
936     return 0;
937 
938   case MCExpr::SymbolRef: {
939     const MCSymbolRefExpr *SRE = cast<MCSymbolRefExpr>(E);
940 
941     switch (SRE->getKind()) {
942     case MCSymbolRefExpr::VK_PPC_LO:
943       Variant = PPCMCExpr::VK_PPC_LO;
944       break;
945     case MCSymbolRefExpr::VK_PPC_HI:
946       Variant = PPCMCExpr::VK_PPC_HI;
947       break;
948     case MCSymbolRefExpr::VK_PPC_HA:
949       Variant = PPCMCExpr::VK_PPC_HA;
950       break;
951     case MCSymbolRefExpr::VK_PPC_HIGHER:
952       Variant = PPCMCExpr::VK_PPC_HIGHER;
953       break;
954     case MCSymbolRefExpr::VK_PPC_HIGHERA:
955       Variant = PPCMCExpr::VK_PPC_HIGHERA;
956       break;
957     case MCSymbolRefExpr::VK_PPC_HIGHEST:
958       Variant = PPCMCExpr::VK_PPC_HIGHEST;
959       break;
960     case MCSymbolRefExpr::VK_PPC_HIGHESTA:
961       Variant = PPCMCExpr::VK_PPC_HIGHESTA;
962       break;
963     default:
964       return 0;
965     }
966 
967     return MCSymbolRefExpr::Create(&SRE->getSymbol(), Context);
968   }
969 
970   case MCExpr::Unary: {
971     const MCUnaryExpr *UE = cast<MCUnaryExpr>(E);
972     const MCExpr *Sub = ExtractModifierFromExpr(UE->getSubExpr(), Variant);
973     if (!Sub)
974       return 0;
975     return MCUnaryExpr::Create(UE->getOpcode(), Sub, Context);
976   }
977 
978   case MCExpr::Binary: {
979     const MCBinaryExpr *BE = cast<MCBinaryExpr>(E);
980     PPCMCExpr::VariantKind LHSVariant, RHSVariant;
981     const MCExpr *LHS = ExtractModifierFromExpr(BE->getLHS(), LHSVariant);
982     const MCExpr *RHS = ExtractModifierFromExpr(BE->getRHS(), RHSVariant);
983 
984     if (!LHS && !RHS)
985       return 0;
986 
987     if (!LHS) LHS = BE->getLHS();
988     if (!RHS) RHS = BE->getRHS();
989 
990     if (LHSVariant == PPCMCExpr::VK_PPC_None)
991       Variant = RHSVariant;
992     else if (RHSVariant == PPCMCExpr::VK_PPC_None)
993       Variant = LHSVariant;
994     else if (LHSVariant == RHSVariant)
995       Variant = LHSVariant;
996     else
997       return 0;
998 
999     return MCBinaryExpr::Create(BE->getOpcode(), LHS, RHS, Context);
1000   }
1001   }
1002 
1003   llvm_unreachable("Invalid expression kind!");
1004 }
1005 
1006 /// Parse an expression.  This differs from the default "parseExpression"
1007 /// in that it handles complex \code @l/@ha \endcode modifiers.
1008 bool PPCAsmParser::
1009 ParseExpression(const MCExpr *&EVal) {
1010   if (getParser().parseExpression(EVal))
1011     return true;
1012 
1013   PPCMCExpr::VariantKind Variant;
1014   const MCExpr *E = ExtractModifierFromExpr(EVal, Variant);
1015   if (E)
1016     EVal = PPCMCExpr::Create(Variant, E, getParser().getContext());
1017 
1018   return false;
1019 }
1020 
1021 bool PPCAsmParser::
1022 ParseOperand(SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1023   SMLoc S = Parser.getTok().getLoc();
1024   SMLoc E = SMLoc::getFromPointer(Parser.getTok().getLoc().getPointer() - 1);
1025   const MCExpr *EVal;
1026   PPCOperand *Op;
1027 
1028   // Attempt to parse the next token as an immediate
1029   switch (getLexer().getKind()) {
1030   // Special handling for register names.  These are interpreted
1031   // as immediates corresponding to the register number.
1032   case AsmToken::Percent:
1033     Parser.Lex(); // Eat the '%'.
1034     unsigned RegNo;
1035     int64_t IntVal;
1036     if (!MatchRegisterName(Parser.getTok(), RegNo, IntVal)) {
1037       Parser.Lex(); // Eat the identifier token.
1038       Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1039       Operands.push_back(Op);
1040       return false;
1041     }
1042     return Error(S, "invalid register name");
1043 
1044   // All other expressions
1045   case AsmToken::LParen:
1046   case AsmToken::Plus:
1047   case AsmToken::Minus:
1048   case AsmToken::Integer:
1049   case AsmToken::Identifier:
1050   case AsmToken::Dot:
1051   case AsmToken::Dollar:
1052     if (!ParseExpression(EVal))
1053       break;
1054     /* fall through */
1055   default:
1056     return Error(S, "unknown operand");
1057   }
1058 
1059   // Push the parsed operand into the list of operands
1060   Op = PPCOperand::CreateFromMCExpr(EVal, S, E, isPPC64());
1061   Operands.push_back(Op);
1062 
1063   // Check whether this is a TLS call expression
1064   bool TLSCall = false;
1065   if (const MCSymbolRefExpr *Ref = dyn_cast<MCSymbolRefExpr>(EVal))
1066     TLSCall = Ref->getSymbol().getName() == "__tls_get_addr";
1067 
1068   if (TLSCall && getLexer().is(AsmToken::LParen)) {
1069     const MCExpr *TLSSym;
1070 
1071     Parser.Lex(); // Eat the '('.
1072     S = Parser.getTok().getLoc();
1073     if (ParseExpression(TLSSym))
1074       return Error(S, "invalid TLS call expression");
1075     if (getLexer().isNot(AsmToken::RParen))
1076       return Error(Parser.getTok().getLoc(), "missing ')'");
1077     E = Parser.getTok().getLoc();
1078     Parser.Lex(); // Eat the ')'.
1079 
1080     Op = PPCOperand::CreateFromMCExpr(TLSSym, S, E, isPPC64());
1081     Operands.push_back(Op);
1082   }
1083 
1084   // Otherwise, check for D-form memory operands
1085   if (!TLSCall && getLexer().is(AsmToken::LParen)) {
1086     Parser.Lex(); // Eat the '('.
1087     S = Parser.getTok().getLoc();
1088 
1089     int64_t IntVal;
1090     switch (getLexer().getKind()) {
1091     case AsmToken::Percent:
1092       Parser.Lex(); // Eat the '%'.
1093       unsigned RegNo;
1094       if (MatchRegisterName(Parser.getTok(), RegNo, IntVal))
1095         return Error(S, "invalid register name");
1096       Parser.Lex(); // Eat the identifier token.
1097       break;
1098 
1099     case AsmToken::Integer:
1100       if (getParser().parseAbsoluteExpression(IntVal) ||
1101           IntVal < 0 || IntVal > 31)
1102         return Error(S, "invalid register number");
1103       break;
1104 
1105     default:
1106       return Error(S, "invalid memory operand");
1107     }
1108 
1109     if (getLexer().isNot(AsmToken::RParen))
1110       return Error(Parser.getTok().getLoc(), "missing ')'");
1111     E = Parser.getTok().getLoc();
1112     Parser.Lex(); // Eat the ')'.
1113 
1114     Op = PPCOperand::CreateImm(IntVal, S, E, isPPC64());
1115     Operands.push_back(Op);
1116   }
1117 
1118   return false;
1119 }
1120 
1121 /// Parse an instruction mnemonic followed by its operands.
1122 bool PPCAsmParser::
1123 ParseInstruction(ParseInstructionInfo &Info, StringRef Name, SMLoc NameLoc,
1124                  SmallVectorImpl<MCParsedAsmOperand*> &Operands) {
1125   // The first operand is the token for the instruction name.
1126   // If the next character is a '+' or '-', we need to add it to the
1127   // instruction name, to match what TableGen is doing.
1128   if (getLexer().is(AsmToken::Plus)) {
1129     getLexer().Lex();
1130     char *NewOpcode = new char[Name.size() + 1];
1131     memcpy(NewOpcode, Name.data(), Name.size());
1132     NewOpcode[Name.size()] = '+';
1133     Name = StringRef(NewOpcode, Name.size() + 1);
1134   }
1135   if (getLexer().is(AsmToken::Minus)) {
1136     getLexer().Lex();
1137     char *NewOpcode = new char[Name.size() + 1];
1138     memcpy(NewOpcode, Name.data(), Name.size());
1139     NewOpcode[Name.size()] = '-';
1140     Name = StringRef(NewOpcode, Name.size() + 1);
1141   }
1142   // If the instruction ends in a '.', we need to create a separate
1143   // token for it, to match what TableGen is doing.
1144   size_t Dot = Name.find('.');
1145   StringRef Mnemonic = Name.slice(0, Dot);
1146   Operands.push_back(PPCOperand::CreateToken(Mnemonic, NameLoc, isPPC64()));
1147   if (Dot != StringRef::npos) {
1148     SMLoc DotLoc = SMLoc::getFromPointer(NameLoc.getPointer() + Dot);
1149     StringRef DotStr = Name.slice(Dot, StringRef::npos);
1150     Operands.push_back(PPCOperand::CreateToken(DotStr, DotLoc, isPPC64()));
1151   }
1152 
1153   // If there are no more operands then finish
1154   if (getLexer().is(AsmToken::EndOfStatement))
1155     return false;
1156 
1157   // Parse the first operand
1158   if (ParseOperand(Operands))
1159     return true;
1160 
1161   while (getLexer().isNot(AsmToken::EndOfStatement) &&
1162          getLexer().is(AsmToken::Comma)) {
1163     // Consume the comma token
1164     getLexer().Lex();
1165 
1166     // Parse the next operand
1167     if (ParseOperand(Operands))
1168       return true;
1169   }
1170 
1171   return false;
1172 }
1173 
1174 /// ParseDirective parses the PPC specific directives
1175 bool PPCAsmParser::ParseDirective(AsmToken DirectiveID) {
1176   StringRef IDVal = DirectiveID.getIdentifier();
1177   if (IDVal == ".word")
1178     return ParseDirectiveWord(4, DirectiveID.getLoc());
1179   if (IDVal == ".tc")
1180     return ParseDirectiveTC(isPPC64()? 8 : 4, DirectiveID.getLoc());
1181   return true;
1182 }
1183 
1184 /// ParseDirectiveWord
1185 ///  ::= .word [ expression (, expression)* ]
1186 bool PPCAsmParser::ParseDirectiveWord(unsigned Size, SMLoc L) {
1187   if (getLexer().isNot(AsmToken::EndOfStatement)) {
1188     for (;;) {
1189       const MCExpr *Value;
1190       if (getParser().parseExpression(Value))
1191         return true;
1192 
1193       getParser().getStreamer().EmitValue(Value, Size);
1194 
1195       if (getLexer().is(AsmToken::EndOfStatement))
1196         break;
1197 
1198       if (getLexer().isNot(AsmToken::Comma))
1199         return Error(L, "unexpected token in directive");
1200       Parser.Lex();
1201     }
1202   }
1203 
1204   Parser.Lex();
1205   return false;
1206 }
1207 
1208 /// ParseDirectiveTC
1209 ///  ::= .tc [ symbol (, expression)* ]
1210 bool PPCAsmParser::ParseDirectiveTC(unsigned Size, SMLoc L) {
1211   // Skip TC symbol, which is only used with XCOFF.
1212   while (getLexer().isNot(AsmToken::EndOfStatement)
1213          && getLexer().isNot(AsmToken::Comma))
1214     Parser.Lex();
1215   if (getLexer().isNot(AsmToken::Comma))
1216     return Error(L, "unexpected token in directive");
1217   Parser.Lex();
1218 
1219   // Align to word size.
1220   getParser().getStreamer().EmitValueToAlignment(Size);
1221 
1222   // Emit expressions.
1223   return ParseDirectiveWord(Size, L);
1224 }
1225 
1226 /// Force static initialization.
1227 extern "C" void LLVMInitializePowerPCAsmParser() {
1228   RegisterMCAsmParser<PPCAsmParser> A(ThePPC32Target);
1229   RegisterMCAsmParser<PPCAsmParser> B(ThePPC64Target);
1230 }
1231 
1232 #define GET_REGISTER_MATCHER
1233 #define GET_MATCHER_IMPLEMENTATION
1234 #include "PPCGenAsmMatcher.inc"
1235