1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
16 #include "NVPTX.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "NVPTXTargetTransformInfo.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSubtargetInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
47 #include "llvm/Transforms/Scalar/GVN.h"
48 
49 using namespace llvm;
50 
51 static cl::opt<bool> UseInferAddressSpaces(
52     "nvptx-use-infer-addrspace", cl::init(false), cl::Hidden,
53     cl::desc("Optimize address spaces using NVPTXInferAddressSpaces instead of "
54              "NVPTXFavorNonGenericAddrSpaces"));
55 
56 namespace llvm {
57 void initializeNVVMReflectPass(PassRegistry&);
58 void initializeGenericToNVVMPass(PassRegistry&);
59 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
60 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
61 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
62 void initializeNVPTXInferAddressSpacesPass(PassRegistry &);
63 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
64 void initializeNVPTXLowerKernelArgsPass(PassRegistry &);
65 void initializeNVPTXLowerAllocaPass(PassRegistry &);
66 }
67 
68 extern "C" void LLVMInitializeNVPTXTarget() {
69   // Register the target.
70   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
71   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
72 
73   // FIXME: This pass is really intended to be invoked during IR optimization,
74   // but it's very NVPTX-specific.
75   PassRegistry &PR = *PassRegistry::getPassRegistry();
76   initializeNVVMReflectPass(PR);
77   initializeGenericToNVVMPass(PR);
78   initializeNVPTXAllocaHoistingPass(PR);
79   initializeNVPTXAssignValidGlobalNamesPass(PR);
80   initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
81   initializeNVPTXInferAddressSpacesPass(PR);
82   initializeNVPTXLowerKernelArgsPass(PR);
83   initializeNVPTXLowerAllocaPass(PR);
84   initializeNVPTXLowerAggrCopiesPass(PR);
85 }
86 
87 static std::string computeDataLayout(bool is64Bit) {
88   std::string Ret = "e";
89 
90   if (!is64Bit)
91     Ret += "-p:32:32";
92 
93   Ret += "-i64:64-v16:16-v32:32-n16:32:64";
94 
95   return Ret;
96 }
97 
98 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
99                                        StringRef CPU, StringRef FS,
100                                        const TargetOptions &Options,
101                                        Reloc::Model RM, CodeModel::Model CM,
102                                        CodeGenOpt::Level OL, bool is64bit)
103     : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
104                         CM, OL),
105       is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
106       Subtarget(TT, CPU, FS, *this) {
107   if (TT.getOS() == Triple::NVCL)
108     drvInterface = NVPTX::NVCL;
109   else
110     drvInterface = NVPTX::CUDA;
111   initAsmInfo();
112 }
113 
114 NVPTXTargetMachine::~NVPTXTargetMachine() {}
115 
116 void NVPTXTargetMachine32::anchor() {}
117 
118 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
119                                            StringRef CPU, StringRef FS,
120                                            const TargetOptions &Options,
121                                            Reloc::Model RM, CodeModel::Model CM,
122                                            CodeGenOpt::Level OL)
123     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
124 
125 void NVPTXTargetMachine64::anchor() {}
126 
127 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
128                                            StringRef CPU, StringRef FS,
129                                            const TargetOptions &Options,
130                                            Reloc::Model RM, CodeModel::Model CM,
131                                            CodeGenOpt::Level OL)
132     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
133 
134 namespace {
135 class NVPTXPassConfig : public TargetPassConfig {
136 public:
137   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
138       : TargetPassConfig(TM, PM) {}
139 
140   NVPTXTargetMachine &getNVPTXTargetMachine() const {
141     return getTM<NVPTXTargetMachine>();
142   }
143 
144   void addIRPasses() override;
145   bool addInstSelector() override;
146   void addPostRegAlloc() override;
147   void addMachineSSAOptimization() override;
148 
149   FunctionPass *createTargetRegisterAllocator(bool) override;
150   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
151   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
152 
153 private:
154   // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
155   // function is only called in opt mode.
156   void addEarlyCSEOrGVNPass();
157 
158   // Add passes that propagate special memory spaces.
159   void addAddressSpaceInferencePasses();
160 
161   // Add passes that perform straight-line scalar optimizations.
162   void addStraightLineScalarOptimizationPasses();
163 };
164 } // end anonymous namespace
165 
166 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
167   return new NVPTXPassConfig(this, PM);
168 }
169 
170 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
171   return TargetIRAnalysis([this](const Function &F) {
172     return TargetTransformInfo(NVPTXTTIImpl(this, F));
173   });
174 }
175 
176 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
177   if (getOptLevel() == CodeGenOpt::Aggressive)
178     addPass(createGVNPass());
179   else
180     addPass(createEarlyCSEPass());
181 }
182 
183 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
184   addPass(createNVPTXLowerKernelArgsPass(&getNVPTXTargetMachine()));
185   // NVPTXLowerKernelArgs emits alloca for byval parameters which can often
186   // be eliminated by SROA.
187   addPass(createSROAPass());
188   addPass(createNVPTXLowerAllocaPass());
189   if (UseInferAddressSpaces) {
190     addPass(createNVPTXInferAddressSpacesPass());
191   } else {
192     addPass(createNVPTXFavorNonGenericAddrSpacesPass());
193     // FavorNonGenericAddrSpaces shortcuts unnecessary addrspacecasts, and leave
194     // them unused. We could remove dead code in an ad-hoc manner, but that
195     // requires manual work and might be error-prone.
196     addPass(createDeadCodeEliminationPass());
197   }
198 }
199 
200 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
201   addPass(createSeparateConstOffsetFromGEPPass());
202   addPass(createSpeculativeExecutionPass());
203   // ReassociateGEPs exposes more opportunites for SLSR. See
204   // the example in reassociate-geps-and-slsr.ll.
205   addPass(createStraightLineStrengthReducePass());
206   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
207   // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
208   // for some of our benchmarks.
209   addEarlyCSEOrGVNPass();
210   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
211   addPass(createNaryReassociatePass());
212   // NaryReassociate on GEPs creates redundant common expressions, so run
213   // EarlyCSE after it.
214   addPass(createEarlyCSEPass());
215 }
216 
217 void NVPTXPassConfig::addIRPasses() {
218   // The following passes are known to not play well with virtual regs hanging
219   // around after register allocation (which in our case, is *all* registers).
220   // We explicitly disable them here.  We do, however, need some functionality
221   // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
222   // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
223   disablePass(&PrologEpilogCodeInserterID);
224   disablePass(&MachineCopyPropagationID);
225   disablePass(&TailDuplicateID);
226 
227   addPass(createNVVMReflectPass());
228   if (getOptLevel() != CodeGenOpt::None)
229     addPass(createNVPTXImageOptimizerPass());
230   addPass(createNVPTXAssignValidGlobalNamesPass());
231   addPass(createGenericToNVVMPass());
232 
233   if (getOptLevel() != CodeGenOpt::None) {
234     addAddressSpaceInferencePasses();
235     addStraightLineScalarOptimizationPasses();
236   }
237 
238   // === LSR and other generic IR passes ===
239   TargetPassConfig::addIRPasses();
240   // EarlyCSE is not always strong enough to clean up what LSR produces. For
241   // example, GVN can combine
242   //
243   //   %0 = add %a, %b
244   //   %1 = add %b, %a
245   //
246   // and
247   //
248   //   %0 = shl nsw %a, 2
249   //   %1 = shl %a, 2
250   //
251   // but EarlyCSE can do neither of them.
252   if (getOptLevel() != CodeGenOpt::None)
253     addEarlyCSEOrGVNPass();
254 }
255 
256 bool NVPTXPassConfig::addInstSelector() {
257   const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
258 
259   addPass(createLowerAggrCopies());
260   addPass(createAllocaHoisting());
261   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
262 
263   if (!ST.hasImageHandles())
264     addPass(createNVPTXReplaceImageHandlesPass());
265 
266   return false;
267 }
268 
269 void NVPTXPassConfig::addPostRegAlloc() {
270   addPass(createNVPTXPrologEpilogPass(), false);
271   // NVPTXPrologEpilogPass calculates frame object offset and replace frame
272   // index with VRFrame register. NVPTXPeephole need to be run after that and
273   // will replace VRFrame with VRFrameLocal when possible.
274   addPass(createNVPTXPeephole());
275 }
276 
277 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
278   return nullptr; // No reg alloc
279 }
280 
281 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
282   assert(!RegAllocPass && "NVPTX uses no regalloc!");
283   addPass(&PHIEliminationID);
284   addPass(&TwoAddressInstructionPassID);
285 }
286 
287 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
288   assert(!RegAllocPass && "NVPTX uses no regalloc!");
289 
290   addPass(&ProcessImplicitDefsID);
291   addPass(&LiveVariablesID);
292   addPass(&MachineLoopInfoID);
293   addPass(&PHIEliminationID);
294 
295   addPass(&TwoAddressInstructionPassID);
296   addPass(&RegisterCoalescerID);
297 
298   // PreRA instruction scheduling.
299   if (addPass(&MachineSchedulerID))
300     printAndVerify("After Machine Scheduling");
301 
302 
303   addPass(&StackSlotColoringID);
304 
305   // FIXME: Needs physical registers
306   //addPass(&PostRAMachineLICMID);
307 
308   printAndVerify("After StackSlotColoring");
309 }
310 
311 void NVPTXPassConfig::addMachineSSAOptimization() {
312   // Pre-ra tail duplication.
313   if (addPass(&EarlyTailDuplicateID))
314     printAndVerify("After Pre-RegAlloc TailDuplicate");
315 
316   // Optimize PHIs before DCE: removing dead PHI cycles may make more
317   // instructions dead.
318   addPass(&OptimizePHIsID);
319 
320   // This pass merges large allocas. StackSlotColoring is a different pass
321   // which merges spill slots.
322   addPass(&StackColoringID);
323 
324   // If the target requests it, assign local variables to stack slots relative
325   // to one another and simplify frame index references where possible.
326   addPass(&LocalStackSlotAllocationID);
327 
328   // With optimization, dead code should already be eliminated. However
329   // there is one known exception: lowered code for arguments that are only
330   // used by tail calls, where the tail calls reuse the incoming stack
331   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
332   addPass(&DeadMachineInstructionElimID);
333   printAndVerify("After codegen DCE pass");
334 
335   // Allow targets to insert passes that improve instruction level parallelism,
336   // like if-conversion. Such passes will typically need dominator trees and
337   // loop info, just like LICM and CSE below.
338   if (addILPOpts())
339     printAndVerify("After ILP optimizations");
340 
341   addPass(&MachineLICMID);
342   addPass(&MachineCSEID);
343 
344   addPass(&MachineSinkingID);
345   printAndVerify("After Machine LICM, CSE and Sinking passes");
346 
347   addPass(&PeepholeOptimizerID);
348   printAndVerify("After codegen peephole optimization pass");
349 }
350