1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
16 #include "NVPTX.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "NVPTXTargetTransformInfo.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/CodeGen/TargetPassConfig.h"
27 #include "llvm/IR/DataLayout.h"
28 #include "llvm/IR/IRPrintingPasses.h"
29 #include "llvm/IR/LegacyPassManager.h"
30 #include "llvm/IR/Verifier.h"
31 #include "llvm/MC/MCAsmInfo.h"
32 #include "llvm/MC/MCInstrInfo.h"
33 #include "llvm/MC/MCStreamer.h"
34 #include "llvm/MC/MCSubtargetInfo.h"
35 #include "llvm/Support/CommandLine.h"
36 #include "llvm/Support/Debug.h"
37 #include "llvm/Support/FormattedStream.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetSubtargetInfo.h"
47 #include "llvm/Transforms/Scalar.h"
48 #include "llvm/Transforms/Scalar/GVN.h"
49 #include "llvm/Transforms/Vectorize.h"
50 
51 using namespace llvm;
52 
53 static cl::opt<bool> UseInferAddressSpaces(
54     "nvptx-use-infer-addrspace", cl::init(false), cl::Hidden,
55     cl::desc("Optimize address spaces using NVPTXInferAddressSpaces instead of "
56              "NVPTXFavorNonGenericAddrSpaces"));
57 
58 // LSV is still relatively new; this switch lets us turn it off in case we
59 // encounter (or suspect) a bug.
60 static cl::opt<bool>
61     DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
62                                cl::desc("Disable load/store vectorizer"),
63                                cl::init(false), cl::Hidden);
64 
65 namespace llvm {
66 void initializeNVVMIntrRangePass(PassRegistry&);
67 void initializeNVVMReflectPass(PassRegistry&);
68 void initializeGenericToNVVMPass(PassRegistry&);
69 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
70 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
71 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
72 void initializeNVPTXInferAddressSpacesPass(PassRegistry &);
73 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
74 void initializeNVPTXLowerArgsPass(PassRegistry &);
75 void initializeNVPTXLowerAllocaPass(PassRegistry &);
76 }
77 
78 extern "C" void LLVMInitializeNVPTXTarget() {
79   // Register the target.
80   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
81   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
82 
83   // FIXME: This pass is really intended to be invoked during IR optimization,
84   // but it's very NVPTX-specific.
85   PassRegistry &PR = *PassRegistry::getPassRegistry();
86   initializeNVVMReflectPass(PR);
87   initializeNVVMIntrRangePass(PR);
88   initializeGenericToNVVMPass(PR);
89   initializeNVPTXAllocaHoistingPass(PR);
90   initializeNVPTXAssignValidGlobalNamesPass(PR);
91   initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
92   initializeNVPTXInferAddressSpacesPass(PR);
93   initializeNVPTXLowerArgsPass(PR);
94   initializeNVPTXLowerAllocaPass(PR);
95   initializeNVPTXLowerAggrCopiesPass(PR);
96 }
97 
98 static std::string computeDataLayout(bool is64Bit) {
99   std::string Ret = "e";
100 
101   if (!is64Bit)
102     Ret += "-p:32:32";
103 
104   Ret += "-i64:64-v16:16-v32:32-n16:32:64";
105 
106   return Ret;
107 }
108 
109 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
110                                        StringRef CPU, StringRef FS,
111                                        const TargetOptions &Options,
112                                        Optional<Reloc::Model> RM,
113                                        CodeModel::Model CM,
114                                        CodeGenOpt::Level OL, bool is64bit)
115     // The pic relocation model is used regardless of what the client has
116     // specified, as it is the only relocation model currently supported.
117     : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
118                         Reloc::PIC_, CM, OL),
119       is64bit(is64bit),
120       TLOF(make_unique<NVPTXTargetObjectFile>()),
121       Subtarget(TT, CPU, FS, *this) {
122   if (TT.getOS() == Triple::NVCL)
123     drvInterface = NVPTX::NVCL;
124   else
125     drvInterface = NVPTX::CUDA;
126   initAsmInfo();
127 }
128 
129 NVPTXTargetMachine::~NVPTXTargetMachine() {}
130 
131 void NVPTXTargetMachine32::anchor() {}
132 
133 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
134                                            StringRef CPU, StringRef FS,
135                                            const TargetOptions &Options,
136                                            Optional<Reloc::Model> RM,
137                                            CodeModel::Model CM,
138                                            CodeGenOpt::Level OL)
139     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
140 
141 void NVPTXTargetMachine64::anchor() {}
142 
143 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
144                                            StringRef CPU, StringRef FS,
145                                            const TargetOptions &Options,
146                                            Optional<Reloc::Model> RM,
147                                            CodeModel::Model CM,
148                                            CodeGenOpt::Level OL)
149     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
150 
151 namespace {
152 class NVPTXPassConfig : public TargetPassConfig {
153 public:
154   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
155       : TargetPassConfig(TM, PM) {}
156 
157   NVPTXTargetMachine &getNVPTXTargetMachine() const {
158     return getTM<NVPTXTargetMachine>();
159   }
160 
161   void addIRPasses() override;
162   bool addInstSelector() override;
163   void addPostRegAlloc() override;
164   void addMachineSSAOptimization() override;
165 
166   FunctionPass *createTargetRegisterAllocator(bool) override;
167   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
168   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
169 
170 private:
171   // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
172   // function is only called in opt mode.
173   void addEarlyCSEOrGVNPass();
174 
175   // Add passes that propagate special memory spaces.
176   void addAddressSpaceInferencePasses();
177 
178   // Add passes that perform straight-line scalar optimizations.
179   void addStraightLineScalarOptimizationPasses();
180 };
181 } // end anonymous namespace
182 
183 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
184   return new NVPTXPassConfig(this, PM);
185 }
186 
187 void NVPTXTargetMachine::addEarlyAsPossiblePasses(PassManagerBase &PM) {
188   PM.add(createNVVMReflectPass());
189   PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
190 }
191 
192 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
193   return TargetIRAnalysis([this](const Function &F) {
194     return TargetTransformInfo(NVPTXTTIImpl(this, F));
195   });
196 }
197 
198 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
199   if (getOptLevel() == CodeGenOpt::Aggressive)
200     addPass(createGVNPass());
201   else
202     addPass(createEarlyCSEPass());
203 }
204 
205 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
206   // NVPTXLowerArgs emits alloca for byval parameters which can often
207   // be eliminated by SROA.
208   addPass(createSROAPass());
209   addPass(createNVPTXLowerAllocaPass());
210   if (UseInferAddressSpaces) {
211     addPass(createNVPTXInferAddressSpacesPass());
212   } else {
213     addPass(createNVPTXFavorNonGenericAddrSpacesPass());
214     // FavorNonGenericAddrSpaces shortcuts unnecessary addrspacecasts, and leave
215     // them unused. We could remove dead code in an ad-hoc manner, but that
216     // requires manual work and might be error-prone.
217     addPass(createDeadCodeEliminationPass());
218   }
219 }
220 
221 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
222   addPass(createSeparateConstOffsetFromGEPPass());
223   addPass(createSpeculativeExecutionPass());
224   // ReassociateGEPs exposes more opportunites for SLSR. See
225   // the example in reassociate-geps-and-slsr.ll.
226   addPass(createStraightLineStrengthReducePass());
227   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
228   // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
229   // for some of our benchmarks.
230   addEarlyCSEOrGVNPass();
231   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
232   addPass(createNaryReassociatePass());
233   // NaryReassociate on GEPs creates redundant common expressions, so run
234   // EarlyCSE after it.
235   addPass(createEarlyCSEPass());
236 }
237 
238 void NVPTXPassConfig::addIRPasses() {
239   // The following passes are known to not play well with virtual regs hanging
240   // around after register allocation (which in our case, is *all* registers).
241   // We explicitly disable them here.  We do, however, need some functionality
242   // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
243   // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
244   disablePass(&PrologEpilogCodeInserterID);
245   disablePass(&MachineCopyPropagationID);
246   disablePass(&TailDuplicateID);
247   disablePass(&StackMapLivenessID);
248   disablePass(&LiveDebugValuesID);
249   disablePass(&PostRASchedulerID);
250   disablePass(&FuncletLayoutID);
251   disablePass(&PatchableFunctionID);
252 
253   // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
254   // it here does nothing.  But since we need it for correctness when lowering
255   // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
256   // call addEarlyAsPossiblePasses.
257   addPass(createNVVMReflectPass());
258 
259   if (getOptLevel() != CodeGenOpt::None)
260     addPass(createNVPTXImageOptimizerPass());
261   addPass(createNVPTXAssignValidGlobalNamesPass());
262   addPass(createGenericToNVVMPass());
263 
264   // NVPTXLowerArgs is required for correctness and should be run right
265   // before the address space inference passes.
266   addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
267   if (getOptLevel() != CodeGenOpt::None) {
268     addAddressSpaceInferencePasses();
269     if (!DisableLoadStoreVectorizer)
270       addPass(createLoadStoreVectorizerPass());
271     addStraightLineScalarOptimizationPasses();
272   }
273 
274   // === LSR and other generic IR passes ===
275   TargetPassConfig::addIRPasses();
276   // EarlyCSE is not always strong enough to clean up what LSR produces. For
277   // example, GVN can combine
278   //
279   //   %0 = add %a, %b
280   //   %1 = add %b, %a
281   //
282   // and
283   //
284   //   %0 = shl nsw %a, 2
285   //   %1 = shl %a, 2
286   //
287   // but EarlyCSE can do neither of them.
288   if (getOptLevel() != CodeGenOpt::None)
289     addEarlyCSEOrGVNPass();
290 }
291 
292 bool NVPTXPassConfig::addInstSelector() {
293   const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
294 
295   addPass(createLowerAggrCopies());
296   addPass(createAllocaHoisting());
297   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
298 
299   if (!ST.hasImageHandles())
300     addPass(createNVPTXReplaceImageHandlesPass());
301 
302   return false;
303 }
304 
305 void NVPTXPassConfig::addPostRegAlloc() {
306   addPass(createNVPTXPrologEpilogPass(), false);
307   if (getOptLevel() != CodeGenOpt::None) {
308     // NVPTXPrologEpilogPass calculates frame object offset and replace frame
309     // index with VRFrame register. NVPTXPeephole need to be run after that and
310     // will replace VRFrame with VRFrameLocal when possible.
311     addPass(createNVPTXPeephole());
312   }
313 }
314 
315 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
316   return nullptr; // No reg alloc
317 }
318 
319 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
320   assert(!RegAllocPass && "NVPTX uses no regalloc!");
321   addPass(&PHIEliminationID);
322   addPass(&TwoAddressInstructionPassID);
323 }
324 
325 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
326   assert(!RegAllocPass && "NVPTX uses no regalloc!");
327 
328   addPass(&ProcessImplicitDefsID);
329   addPass(&LiveVariablesID);
330   addPass(&MachineLoopInfoID);
331   addPass(&PHIEliminationID);
332 
333   addPass(&TwoAddressInstructionPassID);
334   addPass(&RegisterCoalescerID);
335 
336   // PreRA instruction scheduling.
337   if (addPass(&MachineSchedulerID))
338     printAndVerify("After Machine Scheduling");
339 
340 
341   addPass(&StackSlotColoringID);
342 
343   // FIXME: Needs physical registers
344   //addPass(&PostRAMachineLICMID);
345 
346   printAndVerify("After StackSlotColoring");
347 }
348 
349 void NVPTXPassConfig::addMachineSSAOptimization() {
350   // Pre-ra tail duplication.
351   if (addPass(&EarlyTailDuplicateID))
352     printAndVerify("After Pre-RegAlloc TailDuplicate");
353 
354   // Optimize PHIs before DCE: removing dead PHI cycles may make more
355   // instructions dead.
356   addPass(&OptimizePHIsID);
357 
358   // This pass merges large allocas. StackSlotColoring is a different pass
359   // which merges spill slots.
360   addPass(&StackColoringID);
361 
362   // If the target requests it, assign local variables to stack slots relative
363   // to one another and simplify frame index references where possible.
364   addPass(&LocalStackSlotAllocationID);
365 
366   // With optimization, dead code should already be eliminated. However
367   // there is one known exception: lowered code for arguments that are only
368   // used by tail calls, where the tail calls reuse the incoming stack
369   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
370   addPass(&DeadMachineInstructionElimID);
371   printAndVerify("After codegen DCE pass");
372 
373   // Allow targets to insert passes that improve instruction level parallelism,
374   // like if-conversion. Such passes will typically need dominator trees and
375   // loop info, just like LICM and CSE below.
376   if (addILPOpts())
377     printAndVerify("After ILP optimizations");
378 
379   addPass(&MachineLICMID);
380   addPass(&MachineCSEID);
381 
382   addPass(&MachineSinkingID);
383   printAndVerify("After Machine LICM, CSE and Sinking passes");
384 
385   addPass(&PeepholeOptimizerID);
386   printAndVerify("After codegen peephole optimization pass");
387 }
388