1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
16 #include "NVPTX.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXSplitBBatBar.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/Verifier.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/PassManager.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
47 
48 using namespace llvm;
49 
50 namespace llvm {
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
53 }
54 
55 extern "C" void LLVMInitializeNVPTXTarget() {
56   // Register the target.
57   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
58   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
59 
60   // FIXME: This pass is really intended to be invoked during IR optimization,
61   // but it's very NVPTX-specific.
62   initializeNVVMReflectPass(*PassRegistry::getPassRegistry());
63   initializeGenericToNVVMPass(*PassRegistry::getPassRegistry());
64 }
65 
66 static std::string computeDataLayout(const NVPTXSubtarget &ST) {
67   std::string Ret = "e";
68 
69   if (!ST.is64Bit())
70     Ret += "-p:32:32";
71 
72   Ret += "-i64:64-v16:16-v32:32-n16:32:64";
73 
74   return Ret;
75 }
76 
77 NVPTXTargetMachine::NVPTXTargetMachine(
78     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
79     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
80     CodeGenOpt::Level OL, bool is64bit)
81     : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
82       Subtarget(TT, CPU, FS, is64bit), DL(computeDataLayout(Subtarget)),
83       InstrInfo(*this), TLInfo(*this), TSInfo(*this),
84       FrameLowering(
85           *this, is64bit) /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
86   initAsmInfo();
87 }
88 
89 void NVPTXTargetMachine32::anchor() {}
90 
91 NVPTXTargetMachine32::NVPTXTargetMachine32(
92     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
93     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
94     CodeGenOpt::Level OL)
95     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
96 
97 void NVPTXTargetMachine64::anchor() {}
98 
99 NVPTXTargetMachine64::NVPTXTargetMachine64(
100     const Target &T, StringRef TT, StringRef CPU, StringRef FS,
101     const TargetOptions &Options, Reloc::Model RM, CodeModel::Model CM,
102     CodeGenOpt::Level OL)
103     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
104 
105 namespace {
106 class NVPTXPassConfig : public TargetPassConfig {
107 public:
108   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
109       : TargetPassConfig(TM, PM) {}
110 
111   NVPTXTargetMachine &getNVPTXTargetMachine() const {
112     return getTM<NVPTXTargetMachine>();
113   }
114 
115   virtual void addIRPasses();
116   virtual bool addInstSelector();
117   virtual bool addPreRegAlloc();
118   virtual bool addPostRegAlloc();
119 
120   virtual FunctionPass *createTargetRegisterAllocator(bool) LLVM_OVERRIDE;
121   virtual void addFastRegAlloc(FunctionPass *RegAllocPass);
122   virtual void addOptimizedRegAlloc(FunctionPass *RegAllocPass);
123 };
124 } // end anonymous namespace
125 
126 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
127   NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
128   return PassConfig;
129 }
130 
131 void NVPTXPassConfig::addIRPasses() {
132   // The following passes are known to not play well with virtual regs hanging
133   // around after register allocation (which in our case, is *all* registers).
134   // We explicitly disable them here.  We do, however, need some functionality
135   // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
136   // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
137   disablePass(&PrologEpilogCodeInserterID);
138   disablePass(&MachineCopyPropagationID);
139   disablePass(&BranchFolderPassID);
140   disablePass(&TailDuplicateID);
141 
142   TargetPassConfig::addIRPasses();
143   addPass(createGenericToNVVMPass());
144 }
145 
146 bool NVPTXPassConfig::addInstSelector() {
147   addPass(createLowerAggrCopies());
148   addPass(createSplitBBatBarPass());
149   addPass(createAllocaHoisting());
150   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
151   return false;
152 }
153 
154 bool NVPTXPassConfig::addPreRegAlloc() { return false; }
155 bool NVPTXPassConfig::addPostRegAlloc() {
156   addPass(createNVPTXPrologEpilogPass());
157   return false;
158 }
159 
160 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
161   return 0; // No reg alloc
162 }
163 
164 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
165   assert(!RegAllocPass && "NVPTX uses no regalloc!");
166   addPass(&PHIEliminationID);
167   addPass(&TwoAddressInstructionPassID);
168 }
169 
170 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
171   assert(!RegAllocPass && "NVPTX uses no regalloc!");
172 
173   addPass(&ProcessImplicitDefsID);
174   addPass(&LiveVariablesID);
175   addPass(&MachineLoopInfoID);
176   addPass(&PHIEliminationID);
177 
178   addPass(&TwoAddressInstructionPassID);
179   addPass(&RegisterCoalescerID);
180 
181   // PreRA instruction scheduling.
182   if (addPass(&MachineSchedulerID))
183     printAndVerify("After Machine Scheduling");
184 
185 
186   addPass(&StackSlotColoringID);
187 
188   // FIXME: Needs physical registers
189   //addPass(&PostRAMachineLICMID);
190 
191   printAndVerify("After StackSlotColoring");
192 }
193