1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "NVPTX.h"
16 #include "NVPTXAllocaHoisting.h"
17 #include "NVPTXLowerAggrCopies.h"
18 #include "NVPTXTargetObjectFile.h"
19 #include "NVPTXTargetTransformInfo.h"
20 #include "llvm/ADT/STLExtras.h"
21 #include "llvm/ADT/Triple.h"
22 #include "llvm/Analysis/TargetTransformInfo.h"
23 #include "llvm/CodeGen/Passes.h"
24 #include "llvm/CodeGen/TargetPassConfig.h"
25 #include "llvm/IR/LegacyPassManager.h"
26 #include "llvm/Pass.h"
27 #include "llvm/Support/CommandLine.h"
28 #include "llvm/Support/TargetRegistry.h"
29 #include "llvm/Target/TargetMachine.h"
30 #include "llvm/Target/TargetOptions.h"
31 #include "llvm/Transforms/IPO/PassManagerBuilder.h"
32 #include "llvm/Transforms/Scalar.h"
33 #include "llvm/Transforms/Scalar/GVN.h"
34 #include "llvm/Transforms/Vectorize.h"
35 #include <cassert>
36 #include <string>
37 
38 using namespace llvm;
39 
40 // LSV is still relatively new; this switch lets us turn it off in case we
41 // encounter (or suspect) a bug.
42 static cl::opt<bool>
43     DisableLoadStoreVectorizer("disable-nvptx-load-store-vectorizer",
44                                cl::desc("Disable load/store vectorizer"),
45                                cl::init(false), cl::Hidden);
46 
47 namespace llvm {
48 
49 void initializeNVVMIntrRangePass(PassRegistry&);
50 void initializeNVVMReflectPass(PassRegistry&);
51 void initializeGenericToNVVMPass(PassRegistry&);
52 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
53 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
54 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
55 void initializeNVPTXLowerArgsPass(PassRegistry &);
56 void initializeNVPTXLowerAllocaPass(PassRegistry &);
57 
58 } // end namespace llvm
59 
60 extern "C" void LLVMInitializeNVPTXTarget() {
61   // Register the target.
62   RegisterTargetMachine<NVPTXTargetMachine32> X(getTheNVPTXTarget32());
63   RegisterTargetMachine<NVPTXTargetMachine64> Y(getTheNVPTXTarget64());
64 
65   // FIXME: This pass is really intended to be invoked during IR optimization,
66   // but it's very NVPTX-specific.
67   PassRegistry &PR = *PassRegistry::getPassRegistry();
68   initializeNVVMReflectPass(PR);
69   initializeNVVMIntrRangePass(PR);
70   initializeGenericToNVVMPass(PR);
71   initializeNVPTXAllocaHoistingPass(PR);
72   initializeNVPTXAssignValidGlobalNamesPass(PR);
73   initializeNVPTXLowerArgsPass(PR);
74   initializeNVPTXLowerAllocaPass(PR);
75   initializeNVPTXLowerAggrCopiesPass(PR);
76 }
77 
78 static std::string computeDataLayout(bool is64Bit) {
79   std::string Ret = "e";
80 
81   if (!is64Bit)
82     Ret += "-p:32:32";
83 
84   Ret += "-i64:64-i128:128-v16:16-v32:32-n16:32:64";
85 
86   return Ret;
87 }
88 
89 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) {
90   if (CM)
91     return *CM;
92   return CodeModel::Small;
93 }
94 
95 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
96                                        StringRef CPU, StringRef FS,
97                                        const TargetOptions &Options,
98                                        Optional<Reloc::Model> RM,
99                                        Optional<CodeModel::Model> CM,
100                                        CodeGenOpt::Level OL, bool is64bit)
101     // The pic relocation model is used regardless of what the client has
102     // specified, as it is the only relocation model currently supported.
103     : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options,
104                         Reloc::PIC_, getEffectiveCodeModel(CM), OL),
105       is64bit(is64bit), TLOF(llvm::make_unique<NVPTXTargetObjectFile>()),
106       Subtarget(TT, CPU, FS, *this) {
107   if (TT.getOS() == Triple::NVCL)
108     drvInterface = NVPTX::NVCL;
109   else
110     drvInterface = NVPTX::CUDA;
111   initAsmInfo();
112 }
113 
114 NVPTXTargetMachine::~NVPTXTargetMachine() = default;
115 
116 void NVPTXTargetMachine32::anchor() {}
117 
118 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
119                                            StringRef CPU, StringRef FS,
120                                            const TargetOptions &Options,
121                                            Optional<Reloc::Model> RM,
122                                            Optional<CodeModel::Model> CM,
123                                            CodeGenOpt::Level OL, bool JIT)
124     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
125 
126 void NVPTXTargetMachine64::anchor() {}
127 
128 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
129                                            StringRef CPU, StringRef FS,
130                                            const TargetOptions &Options,
131                                            Optional<Reloc::Model> RM,
132                                            Optional<CodeModel::Model> CM,
133                                            CodeGenOpt::Level OL, bool JIT)
134     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
135 
136 namespace {
137 
138 class NVPTXPassConfig : public TargetPassConfig {
139 public:
140   NVPTXPassConfig(NVPTXTargetMachine &TM, PassManagerBase &PM)
141       : TargetPassConfig(TM, PM) {}
142 
143   NVPTXTargetMachine &getNVPTXTargetMachine() const {
144     return getTM<NVPTXTargetMachine>();
145   }
146 
147   void addIRPasses() override;
148   bool addInstSelector() override;
149   void addPostRegAlloc() override;
150   void addMachineSSAOptimization() override;
151 
152   FunctionPass *createTargetRegisterAllocator(bool) override;
153   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
154   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
155 
156 private:
157   // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
158   // function is only called in opt mode.
159   void addEarlyCSEOrGVNPass();
160 
161   // Add passes that propagate special memory spaces.
162   void addAddressSpaceInferencePasses();
163 
164   // Add passes that perform straight-line scalar optimizations.
165   void addStraightLineScalarOptimizationPasses();
166 };
167 
168 } // end anonymous namespace
169 
170 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
171   return new NVPTXPassConfig(*this, PM);
172 }
173 
174 void NVPTXTargetMachine::adjustPassManager(PassManagerBuilder &Builder) {
175   Builder.addExtension(
176     PassManagerBuilder::EP_EarlyAsPossible,
177     [&](const PassManagerBuilder &, legacy::PassManagerBase &PM) {
178       PM.add(createNVVMReflectPass());
179       PM.add(createNVVMIntrRangePass(Subtarget.getSmVersion()));
180     });
181 }
182 
183 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
184   return TargetIRAnalysis([this](const Function &F) {
185     return TargetTransformInfo(NVPTXTTIImpl(this, F));
186   });
187 }
188 
189 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
190   if (getOptLevel() == CodeGenOpt::Aggressive)
191     addPass(createGVNPass());
192   else
193     addPass(createEarlyCSEPass());
194 }
195 
196 void NVPTXPassConfig::addAddressSpaceInferencePasses() {
197   // NVPTXLowerArgs emits alloca for byval parameters which can often
198   // be eliminated by SROA.
199   addPass(createSROAPass());
200   addPass(createNVPTXLowerAllocaPass());
201   addPass(createInferAddressSpacesPass());
202 }
203 
204 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
205   addPass(createSeparateConstOffsetFromGEPPass());
206   addPass(createSpeculativeExecutionPass());
207   // ReassociateGEPs exposes more opportunites for SLSR. See
208   // the example in reassociate-geps-and-slsr.ll.
209   addPass(createStraightLineStrengthReducePass());
210   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
211   // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
212   // for some of our benchmarks.
213   addEarlyCSEOrGVNPass();
214   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
215   addPass(createNaryReassociatePass());
216   // NaryReassociate on GEPs creates redundant common expressions, so run
217   // EarlyCSE after it.
218   addPass(createEarlyCSEPass());
219 }
220 
221 void NVPTXPassConfig::addIRPasses() {
222   // The following passes are known to not play well with virtual regs hanging
223   // around after register allocation (which in our case, is *all* registers).
224   // We explicitly disable them here.  We do, however, need some functionality
225   // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
226   // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
227   disablePass(&PrologEpilogCodeInserterID);
228   disablePass(&MachineCopyPropagationID);
229   disablePass(&TailDuplicateID);
230   disablePass(&StackMapLivenessID);
231   disablePass(&LiveDebugValuesID);
232   disablePass(&PostRASchedulerID);
233   disablePass(&FuncletLayoutID);
234   disablePass(&PatchableFunctionID);
235 
236   // NVVMReflectPass is added in addEarlyAsPossiblePasses, so hopefully running
237   // it here does nothing.  But since we need it for correctness when lowering
238   // to NVPTX, run it here too, in case whoever built our pass pipeline didn't
239   // call addEarlyAsPossiblePasses.
240   addPass(createNVVMReflectPass());
241 
242   if (getOptLevel() != CodeGenOpt::None)
243     addPass(createNVPTXImageOptimizerPass());
244   addPass(createNVPTXAssignValidGlobalNamesPass());
245   addPass(createGenericToNVVMPass());
246 
247   // NVPTXLowerArgs is required for correctness and should be run right
248   // before the address space inference passes.
249   addPass(createNVPTXLowerArgsPass(&getNVPTXTargetMachine()));
250   if (getOptLevel() != CodeGenOpt::None) {
251     addAddressSpaceInferencePasses();
252     if (!DisableLoadStoreVectorizer)
253       addPass(createLoadStoreVectorizerPass());
254     addStraightLineScalarOptimizationPasses();
255   }
256 
257   // === LSR and other generic IR passes ===
258   TargetPassConfig::addIRPasses();
259   // EarlyCSE is not always strong enough to clean up what LSR produces. For
260   // example, GVN can combine
261   //
262   //   %0 = add %a, %b
263   //   %1 = add %b, %a
264   //
265   // and
266   //
267   //   %0 = shl nsw %a, 2
268   //   %1 = shl %a, 2
269   //
270   // but EarlyCSE can do neither of them.
271   if (getOptLevel() != CodeGenOpt::None)
272     addEarlyCSEOrGVNPass();
273 }
274 
275 bool NVPTXPassConfig::addInstSelector() {
276   const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
277 
278   addPass(createLowerAggrCopies());
279   addPass(createAllocaHoisting());
280   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
281 
282   if (!ST.hasImageHandles())
283     addPass(createNVPTXReplaceImageHandlesPass());
284 
285   return false;
286 }
287 
288 void NVPTXPassConfig::addPostRegAlloc() {
289   addPass(createNVPTXPrologEpilogPass(), false);
290   if (getOptLevel() != CodeGenOpt::None) {
291     // NVPTXPrologEpilogPass calculates frame object offset and replace frame
292     // index with VRFrame register. NVPTXPeephole need to be run after that and
293     // will replace VRFrame with VRFrameLocal when possible.
294     addPass(createNVPTXPeephole());
295   }
296 }
297 
298 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
299   return nullptr; // No reg alloc
300 }
301 
302 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
303   assert(!RegAllocPass && "NVPTX uses no regalloc!");
304   addPass(&PHIEliminationID);
305   addPass(&TwoAddressInstructionPassID);
306 }
307 
308 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
309   assert(!RegAllocPass && "NVPTX uses no regalloc!");
310 
311   addPass(&ProcessImplicitDefsID);
312   addPass(&LiveVariablesID);
313   addPass(&MachineLoopInfoID);
314   addPass(&PHIEliminationID);
315 
316   addPass(&TwoAddressInstructionPassID);
317   addPass(&RegisterCoalescerID);
318 
319   // PreRA instruction scheduling.
320   if (addPass(&MachineSchedulerID))
321     printAndVerify("After Machine Scheduling");
322 
323 
324   addPass(&StackSlotColoringID);
325 
326   // FIXME: Needs physical registers
327   //addPass(&PostRAMachineLICMID);
328 
329   printAndVerify("After StackSlotColoring");
330 }
331 
332 void NVPTXPassConfig::addMachineSSAOptimization() {
333   // Pre-ra tail duplication.
334   if (addPass(&EarlyTailDuplicateID))
335     printAndVerify("After Pre-RegAlloc TailDuplicate");
336 
337   // Optimize PHIs before DCE: removing dead PHI cycles may make more
338   // instructions dead.
339   addPass(&OptimizePHIsID);
340 
341   // This pass merges large allocas. StackSlotColoring is a different pass
342   // which merges spill slots.
343   addPass(&StackColoringID);
344 
345   // If the target requests it, assign local variables to stack slots relative
346   // to one another and simplify frame index references where possible.
347   addPass(&LocalStackSlotAllocationID);
348 
349   // With optimization, dead code should already be eliminated. However
350   // there is one known exception: lowered code for arguments that are only
351   // used by tail calls, where the tail calls reuse the incoming stack
352   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
353   addPass(&DeadMachineInstructionElimID);
354   printAndVerify("After codegen DCE pass");
355 
356   // Allow targets to insert passes that improve instruction level parallelism,
357   // like if-conversion. Such passes will typically need dominator trees and
358   // loop info, just like LICM and CSE below.
359   if (addILPOpts())
360     printAndVerify("After ILP optimizations");
361 
362   addPass(&MachineLICMID);
363   addPass(&MachineCSEID);
364 
365   addPass(&MachineSinkingID);
366   printAndVerify("After Machine LICM, CSE and Sinking passes");
367 
368   addPass(&PeepholeOptimizerID);
369   printAndVerify("After codegen peephole optimization pass");
370 }
371