1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
16 #include "NVPTX.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXSplitBBatBar.h"
20 #include "llvm/ADT/OwningPtr.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/Analysis/Verifier.h"
23 #include "llvm/Assembly/PrintModulePass.h"
24 #include "llvm/CodeGen/AsmPrinter.h"
25 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
26 #include "llvm/CodeGen/MachineModuleInfo.h"
27 #include "llvm/CodeGen/Passes.h"
28 #include "llvm/DataLayout.h"
29 #include "llvm/MC/MCAsmInfo.h"
30 #include "llvm/MC/MCInstrInfo.h"
31 #include "llvm/MC/MCStreamer.h"
32 #include "llvm/MC/MCSubtargetInfo.h"
33 #include "llvm/PassManager.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/TargetRegistry.h"
39 #include "llvm/Support/raw_ostream.h"
40 #include "llvm/Target/TargetInstrInfo.h"
41 #include "llvm/Target/TargetLowering.h"
42 #include "llvm/Target/TargetLoweringObjectFile.h"
43 #include "llvm/Target/TargetMachine.h"
44 #include "llvm/Target/TargetOptions.h"
45 #include "llvm/Target/TargetRegisterInfo.h"
46 #include "llvm/Target/TargetSubtargetInfo.h"
47 #include "llvm/Transforms/Scalar.h"
48 
49 
50 using namespace llvm;
51 
52 
53 extern "C" void LLVMInitializeNVPTXTarget() {
54   // Register the target.
55   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
56   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
57 
58   RegisterMCAsmInfo<NVPTXMCAsmInfo> A(TheNVPTXTarget32);
59   RegisterMCAsmInfo<NVPTXMCAsmInfo> B(TheNVPTXTarget64);
60 
61 }
62 
63 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T,
64                                        StringRef TT,
65                                        StringRef CPU,
66                                        StringRef FS,
67                                        const TargetOptions& Options,
68                                        Reloc::Model RM,
69                                        CodeModel::Model CM,
70                                        CodeGenOpt::Level OL,
71                                        bool is64bit)
72 : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
73   Subtarget(TT, CPU, FS, is64bit),
74   DL(Subtarget.getDataLayout()),
75   InstrInfo(*this), TLInfo(*this), TSInfo(*this), FrameLowering(*this,is64bit),
76   STTI(&TLInfo), VTTI(&TLInfo)
77 /*FrameInfo(TargetFrameInfo::StackGrowsUp, 8, 0)*/ {
78 }
79 
80 
81 
82 void NVPTXTargetMachine32::anchor() {}
83 
84 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, StringRef TT,
85                                            StringRef CPU, StringRef FS,
86                                            const TargetOptions &Options,
87                                            Reloc::Model RM, CodeModel::Model CM,
88                                            CodeGenOpt::Level OL)
89 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {
90 }
91 
92 void NVPTXTargetMachine64::anchor() {}
93 
94 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, StringRef TT,
95                                            StringRef CPU, StringRef FS,
96                                            const TargetOptions &Options,
97                                            Reloc::Model RM, CodeModel::Model CM,
98                                            CodeGenOpt::Level OL)
99 : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {
100 }
101 
102 
103 namespace llvm {
104 class NVPTXPassConfig : public TargetPassConfig {
105 public:
106   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
107   : TargetPassConfig(TM, PM) {}
108 
109   NVPTXTargetMachine &getNVPTXTargetMachine() const {
110     return getTM<NVPTXTargetMachine>();
111   }
112 
113   virtual bool addInstSelector();
114   virtual bool addPreRegAlloc();
115 };
116 }
117 
118 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
119   NVPTXPassConfig *PassConfig = new NVPTXPassConfig(this, PM);
120   return PassConfig;
121 }
122 
123 bool NVPTXPassConfig::addInstSelector() {
124   addPass(createLowerAggrCopies());
125   addPass(createSplitBBatBarPass());
126   addPass(createAllocaHoisting());
127   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
128   addPass(createVectorElementizePass(getNVPTXTargetMachine()));
129   return false;
130 }
131 
132 bool NVPTXPassConfig::addPreRegAlloc() {
133   return false;
134 }
135