1 //===-- NVPTXTargetMachine.cpp - Define TargetMachine for NVPTX -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Top-level implementation for the NVPTX target.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXTargetMachine.h"
15 #include "MCTargetDesc/NVPTXMCAsmInfo.h"
16 #include "NVPTX.h"
17 #include "NVPTXAllocaHoisting.h"
18 #include "NVPTXLowerAggrCopies.h"
19 #include "NVPTXTargetObjectFile.h"
20 #include "NVPTXTargetTransformInfo.h"
21 #include "llvm/Analysis/Passes.h"
22 #include "llvm/CodeGen/AsmPrinter.h"
23 #include "llvm/CodeGen/MachineFunctionAnalysis.h"
24 #include "llvm/CodeGen/MachineModuleInfo.h"
25 #include "llvm/CodeGen/Passes.h"
26 #include "llvm/IR/DataLayout.h"
27 #include "llvm/IR/IRPrintingPasses.h"
28 #include "llvm/IR/LegacyPassManager.h"
29 #include "llvm/IR/Verifier.h"
30 #include "llvm/MC/MCAsmInfo.h"
31 #include "llvm/MC/MCInstrInfo.h"
32 #include "llvm/MC/MCStreamer.h"
33 #include "llvm/MC/MCSubtargetInfo.h"
34 #include "llvm/Support/CommandLine.h"
35 #include "llvm/Support/Debug.h"
36 #include "llvm/Support/FormattedStream.h"
37 #include "llvm/Support/TargetRegistry.h"
38 #include "llvm/Support/raw_ostream.h"
39 #include "llvm/Target/TargetInstrInfo.h"
40 #include "llvm/Target/TargetLowering.h"
41 #include "llvm/Target/TargetLoweringObjectFile.h"
42 #include "llvm/Target/TargetMachine.h"
43 #include "llvm/Target/TargetOptions.h"
44 #include "llvm/Target/TargetRegisterInfo.h"
45 #include "llvm/Target/TargetSubtargetInfo.h"
46 #include "llvm/Transforms/Scalar.h"
47 
48 using namespace llvm;
49 
50 namespace llvm {
51 void initializeNVVMReflectPass(PassRegistry&);
52 void initializeGenericToNVVMPass(PassRegistry&);
53 void initializeNVPTXAllocaHoistingPass(PassRegistry &);
54 void initializeNVPTXAssignValidGlobalNamesPass(PassRegistry&);
55 void initializeNVPTXFavorNonGenericAddrSpacesPass(PassRegistry &);
56 void initializeNVPTXLowerAggrCopiesPass(PassRegistry &);
57 void initializeNVPTXLowerKernelArgsPass(PassRegistry &);
58 void initializeNVPTXLowerAllocaPass(PassRegistry &);
59 }
60 
61 extern "C" void LLVMInitializeNVPTXTarget() {
62   // Register the target.
63   RegisterTargetMachine<NVPTXTargetMachine32> X(TheNVPTXTarget32);
64   RegisterTargetMachine<NVPTXTargetMachine64> Y(TheNVPTXTarget64);
65 
66   // FIXME: This pass is really intended to be invoked during IR optimization,
67   // but it's very NVPTX-specific.
68   PassRegistry &PR = *PassRegistry::getPassRegistry();
69   initializeNVVMReflectPass(PR);
70   initializeGenericToNVVMPass(PR);
71   initializeNVPTXAllocaHoistingPass(PR);
72   initializeNVPTXAssignValidGlobalNamesPass(PR);
73   initializeNVPTXFavorNonGenericAddrSpacesPass(PR);
74   initializeNVPTXLowerKernelArgsPass(PR);
75   initializeNVPTXLowerAllocaPass(PR);
76   initializeNVPTXLowerAggrCopiesPass(PR);
77 }
78 
79 static std::string computeDataLayout(bool is64Bit) {
80   std::string Ret = "e";
81 
82   if (!is64Bit)
83     Ret += "-p:32:32";
84 
85   Ret += "-i64:64-v16:16-v32:32-n16:32:64";
86 
87   return Ret;
88 }
89 
90 NVPTXTargetMachine::NVPTXTargetMachine(const Target &T, const Triple &TT,
91                                        StringRef CPU, StringRef FS,
92                                        const TargetOptions &Options,
93                                        Reloc::Model RM, CodeModel::Model CM,
94                                        CodeGenOpt::Level OL, bool is64bit)
95     : LLVMTargetMachine(T, computeDataLayout(is64bit), TT, CPU, FS, Options, RM,
96                         CM, OL),
97       is64bit(is64bit), TLOF(make_unique<NVPTXTargetObjectFile>()),
98       Subtarget(TT, CPU, FS, *this) {
99   if (TT.getOS() == Triple::NVCL)
100     drvInterface = NVPTX::NVCL;
101   else
102     drvInterface = NVPTX::CUDA;
103   initAsmInfo();
104 }
105 
106 NVPTXTargetMachine::~NVPTXTargetMachine() {}
107 
108 void NVPTXTargetMachine32::anchor() {}
109 
110 NVPTXTargetMachine32::NVPTXTargetMachine32(const Target &T, const Triple &TT,
111                                            StringRef CPU, StringRef FS,
112                                            const TargetOptions &Options,
113                                            Reloc::Model RM, CodeModel::Model CM,
114                                            CodeGenOpt::Level OL)
115     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
116 
117 void NVPTXTargetMachine64::anchor() {}
118 
119 NVPTXTargetMachine64::NVPTXTargetMachine64(const Target &T, const Triple &TT,
120                                            StringRef CPU, StringRef FS,
121                                            const TargetOptions &Options,
122                                            Reloc::Model RM, CodeModel::Model CM,
123                                            CodeGenOpt::Level OL)
124     : NVPTXTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
125 
126 namespace {
127 class NVPTXPassConfig : public TargetPassConfig {
128 public:
129   NVPTXPassConfig(NVPTXTargetMachine *TM, PassManagerBase &PM)
130       : TargetPassConfig(TM, PM) {}
131 
132   NVPTXTargetMachine &getNVPTXTargetMachine() const {
133     return getTM<NVPTXTargetMachine>();
134   }
135 
136   void addIRPasses() override;
137   bool addInstSelector() override;
138   void addPostRegAlloc() override;
139   void addMachineSSAOptimization() override;
140 
141   FunctionPass *createTargetRegisterAllocator(bool) override;
142   void addFastRegAlloc(FunctionPass *RegAllocPass) override;
143   void addOptimizedRegAlloc(FunctionPass *RegAllocPass) override;
144 
145 private:
146   // If the opt level is aggressive, add GVN; otherwise, add EarlyCSE. This
147   // function is only called in opt mode.
148   void addEarlyCSEOrGVNPass();
149 
150   // Add passes that propagate special memory spaces.
151   void addMemorySpaceInferencePasses();
152 
153   // Add passes that perform straight-line scalar optimizations.
154   void addStraightLineScalarOptimizationPasses();
155 };
156 } // end anonymous namespace
157 
158 TargetPassConfig *NVPTXTargetMachine::createPassConfig(PassManagerBase &PM) {
159   return new NVPTXPassConfig(this, PM);
160 }
161 
162 TargetIRAnalysis NVPTXTargetMachine::getTargetIRAnalysis() {
163   return TargetIRAnalysis([this](const Function &F) {
164     return TargetTransformInfo(NVPTXTTIImpl(this, F));
165   });
166 }
167 
168 void NVPTXPassConfig::addEarlyCSEOrGVNPass() {
169   if (getOptLevel() == CodeGenOpt::Aggressive)
170     addPass(createGVNPass());
171   else
172     addPass(createEarlyCSEPass());
173 }
174 
175 void NVPTXPassConfig::addMemorySpaceInferencePasses() {
176   addPass(createNVPTXLowerKernelArgsPass(&getNVPTXTargetMachine()));
177   // NVPTXLowerKernelArgs emits alloca for byval parameters which can often
178   // be eliminated by SROA.
179   addPass(createSROAPass());
180   addPass(createNVPTXLowerAllocaPass());
181   addPass(createNVPTXFavorNonGenericAddrSpacesPass());
182   // FavorNonGenericAddrSpaces shortcuts unnecessary addrspacecasts, and leave
183   // them unused. We could remove dead code in an ad-hoc manner, but that
184   // requires manual work and might be error-prone.
185   addPass(createDeadCodeEliminationPass());
186 }
187 
188 void NVPTXPassConfig::addStraightLineScalarOptimizationPasses() {
189   addPass(createSeparateConstOffsetFromGEPPass());
190   addPass(createSpeculativeExecutionPass());
191   // ReassociateGEPs exposes more opportunites for SLSR. See
192   // the example in reassociate-geps-and-slsr.ll.
193   addPass(createStraightLineStrengthReducePass());
194   // SeparateConstOffsetFromGEP and SLSR creates common expressions which GVN or
195   // EarlyCSE can reuse. GVN generates significantly better code than EarlyCSE
196   // for some of our benchmarks.
197   addEarlyCSEOrGVNPass();
198   // Run NaryReassociate after EarlyCSE/GVN to be more effective.
199   addPass(createNaryReassociatePass());
200   // NaryReassociate on GEPs creates redundant common expressions, so run
201   // EarlyCSE after it.
202   addPass(createEarlyCSEPass());
203 }
204 
205 void NVPTXPassConfig::addIRPasses() {
206   // The following passes are known to not play well with virtual regs hanging
207   // around after register allocation (which in our case, is *all* registers).
208   // We explicitly disable them here.  We do, however, need some functionality
209   // of the PrologEpilogCodeInserter pass, so we emulate that behavior in the
210   // NVPTXPrologEpilog pass (see NVPTXPrologEpilogPass.cpp).
211   disablePass(&PrologEpilogCodeInserterID);
212   disablePass(&MachineCopyPropagationID);
213   disablePass(&TailDuplicateID);
214 
215   addPass(createNVVMReflectPass());
216   if (getOptLevel() != CodeGenOpt::None)
217     addPass(createNVPTXImageOptimizerPass());
218   addPass(createNVPTXAssignValidGlobalNamesPass());
219   addPass(createGenericToNVVMPass());
220 
221   if (getOptLevel() != CodeGenOpt::None) {
222     addMemorySpaceInferencePasses();
223     addStraightLineScalarOptimizationPasses();
224   }
225 
226   // === LSR and other generic IR passes ===
227   TargetPassConfig::addIRPasses();
228   // EarlyCSE is not always strong enough to clean up what LSR produces. For
229   // example, GVN can combine
230   //
231   //   %0 = add %a, %b
232   //   %1 = add %b, %a
233   //
234   // and
235   //
236   //   %0 = shl nsw %a, 2
237   //   %1 = shl %a, 2
238   //
239   // but EarlyCSE can do neither of them.
240   if (getOptLevel() != CodeGenOpt::None)
241     addEarlyCSEOrGVNPass();
242 }
243 
244 bool NVPTXPassConfig::addInstSelector() {
245   const NVPTXSubtarget &ST = *getTM<NVPTXTargetMachine>().getSubtargetImpl();
246 
247   addPass(createLowerAggrCopies());
248   addPass(createAllocaHoisting());
249   addPass(createNVPTXISelDag(getNVPTXTargetMachine(), getOptLevel()));
250 
251   if (!ST.hasImageHandles())
252     addPass(createNVPTXReplaceImageHandlesPass());
253 
254   return false;
255 }
256 
257 void NVPTXPassConfig::addPostRegAlloc() {
258   addPass(createNVPTXPrologEpilogPass(), false);
259   // NVPTXPrologEpilogPass calculates frame object offset and replace frame
260   // index with VRFrame register. NVPTXPeephole need to be run after that and
261   // will replace VRFrame with VRFrameLocal when possible.
262   addPass(createNVPTXPeephole());
263 }
264 
265 FunctionPass *NVPTXPassConfig::createTargetRegisterAllocator(bool) {
266   return nullptr; // No reg alloc
267 }
268 
269 void NVPTXPassConfig::addFastRegAlloc(FunctionPass *RegAllocPass) {
270   assert(!RegAllocPass && "NVPTX uses no regalloc!");
271   addPass(&PHIEliminationID);
272   addPass(&TwoAddressInstructionPassID);
273 }
274 
275 void NVPTXPassConfig::addOptimizedRegAlloc(FunctionPass *RegAllocPass) {
276   assert(!RegAllocPass && "NVPTX uses no regalloc!");
277 
278   addPass(&ProcessImplicitDefsID);
279   addPass(&LiveVariablesID);
280   addPass(&MachineLoopInfoID);
281   addPass(&PHIEliminationID);
282 
283   addPass(&TwoAddressInstructionPassID);
284   addPass(&RegisterCoalescerID);
285 
286   // PreRA instruction scheduling.
287   if (addPass(&MachineSchedulerID))
288     printAndVerify("After Machine Scheduling");
289 
290 
291   addPass(&StackSlotColoringID);
292 
293   // FIXME: Needs physical registers
294   //addPass(&PostRAMachineLICMID);
295 
296   printAndVerify("After StackSlotColoring");
297 }
298 
299 void NVPTXPassConfig::addMachineSSAOptimization() {
300   // Pre-ra tail duplication.
301   if (addPass(&EarlyTailDuplicateID))
302     printAndVerify("After Pre-RegAlloc TailDuplicate");
303 
304   // Optimize PHIs before DCE: removing dead PHI cycles may make more
305   // instructions dead.
306   addPass(&OptimizePHIsID);
307 
308   // This pass merges large allocas. StackSlotColoring is a different pass
309   // which merges spill slots.
310   addPass(&StackColoringID);
311 
312   // If the target requests it, assign local variables to stack slots relative
313   // to one another and simplify frame index references where possible.
314   addPass(&LocalStackSlotAllocationID);
315 
316   // With optimization, dead code should already be eliminated. However
317   // there is one known exception: lowered code for arguments that are only
318   // used by tail calls, where the tail calls reuse the incoming stack
319   // arguments directly (see t11 in test/CodeGen/X86/sibcall.ll).
320   addPass(&DeadMachineInstructionElimID);
321   printAndVerify("After codegen DCE pass");
322 
323   // Allow targets to insert passes that improve instruction level parallelism,
324   // like if-conversion. Such passes will typically need dominator trees and
325   // loop info, just like LICM and CSE below.
326   if (addILPOpts())
327     printAndVerify("After ILP optimizations");
328 
329   addPass(&MachineLICMID);
330   addPass(&MachineCSEID);
331 
332   addPass(&MachineSinkingID);
333   printAndVerify("After Machine LICM, CSE and Sinking passes");
334 
335   addPass(&PeepholeOptimizerID);
336   printAndVerify("After codegen peephole optimization pass");
337 }
338