1 //===- NVPTXRegisterInfo.cpp - NVPTX Register Information -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of the TargetRegisterInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #define DEBUG_TYPE "nvptx-reg-info"
15 
16 #include "NVPTXRegisterInfo.h"
17 #include "NVPTX.h"
18 #include "NVPTXSubtarget.h"
19 #include "llvm/ADT/BitVector.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/MC/MachineLocation.h"
24 #include "llvm/Target/TargetInstrInfo.h"
25 
26 using namespace llvm;
27 
28 namespace llvm {
29 std::string getNVPTXRegClassName(TargetRegisterClass const *RC) {
30   if (RC == &NVPTX::Float32RegsRegClass) {
31     return ".f32";
32   }
33   if (RC == &NVPTX::Float64RegsRegClass) {
34     return ".f64";
35   } else if (RC == &NVPTX::Int64RegsRegClass) {
36     return ".s64";
37   } else if (RC == &NVPTX::Int32RegsRegClass) {
38     return ".s32";
39   } else if (RC == &NVPTX::Int16RegsRegClass) {
40     return ".s16";
41   }
42       // Int8Regs become 16-bit registers in PTX
43       else if (RC == &NVPTX::Int8RegsRegClass) {
44     return ".s16";
45   } else if (RC == &NVPTX::Int1RegsRegClass) {
46     return ".pred";
47   } else if (RC == &NVPTX::SpecialRegsRegClass) {
48     return "!Special!";
49   } else {
50     return "INTERNAL";
51   }
52   return "";
53 }
54 
55 std::string getNVPTXRegClassStr(TargetRegisterClass const *RC) {
56   if (RC == &NVPTX::Float32RegsRegClass) {
57     return "%f";
58   }
59   if (RC == &NVPTX::Float64RegsRegClass) {
60     return "%fd";
61   } else if (RC == &NVPTX::Int64RegsRegClass) {
62     return "%rd";
63   } else if (RC == &NVPTX::Int32RegsRegClass) {
64     return "%r";
65   } else if (RC == &NVPTX::Int16RegsRegClass) {
66     return "%rs";
67   } else if (RC == &NVPTX::Int8RegsRegClass) {
68     return "%rc";
69   } else if (RC == &NVPTX::Int1RegsRegClass) {
70     return "%p";
71   } else if (RC == &NVPTX::SpecialRegsRegClass) {
72     return "!Special!";
73   } else {
74     return "INTERNAL";
75   }
76   return "";
77 }
78 }
79 
80 NVPTXRegisterInfo::NVPTXRegisterInfo(const TargetInstrInfo &tii,
81                                      const NVPTXSubtarget &st)
82     : NVPTXGenRegisterInfo(0), Is64Bit(st.is64Bit()) {}
83 
84 #define GET_REGINFO_TARGET_DESC
85 #include "NVPTXGenRegisterInfo.inc"
86 
87 /// NVPTX Callee Saved Registers
88 const uint16_t *
89 NVPTXRegisterInfo::getCalleeSavedRegs(const MachineFunction *MF) const {
90   static const uint16_t CalleeSavedRegs[] = { 0 };
91   return CalleeSavedRegs;
92 }
93 
94 // NVPTX Callee Saved Reg Classes
95 const TargetRegisterClass *const *
96 NVPTXRegisterInfo::getCalleeSavedRegClasses(const MachineFunction *MF) const {
97   static const TargetRegisterClass *const CalleeSavedRegClasses[] = { 0 };
98   return CalleeSavedRegClasses;
99 }
100 
101 BitVector NVPTXRegisterInfo::getReservedRegs(const MachineFunction &MF) const {
102   BitVector Reserved(getNumRegs());
103   return Reserved;
104 }
105 
106 void NVPTXRegisterInfo::eliminateFrameIndex(MachineBasicBlock::iterator II,
107                                             int SPAdj, unsigned FIOperandNum,
108                                             RegScavenger *RS) const {
109   assert(SPAdj == 0 && "Unexpected");
110 
111   MachineInstr &MI = *II;
112   int FrameIndex = MI.getOperand(FIOperandNum).getIndex();
113 
114   MachineFunction &MF = *MI.getParent()->getParent();
115   int Offset = MF.getFrameInfo()->getObjectOffset(FrameIndex) +
116                MI.getOperand(FIOperandNum + 1).getImm();
117 
118   // Using I0 as the frame pointer
119   MI.getOperand(FIOperandNum).ChangeToRegister(NVPTX::VRFrame, false);
120   MI.getOperand(FIOperandNum + 1).ChangeToImmediate(Offset);
121 }
122 
123 int NVPTXRegisterInfo::getDwarfRegNum(unsigned RegNum, bool isEH) const {
124   return 0;
125 }
126 
127 unsigned NVPTXRegisterInfo::getFrameRegister(const MachineFunction &MF) const {
128   return NVPTX::VRFrame;
129 }
130 
131 unsigned NVPTXRegisterInfo::getRARegister() const { return 0; }
132