1 //===- NVPTXInstrInfo.cpp - NVPTX Instruction Information -----------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the NVPTX implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTX.h"
15 #include "NVPTXInstrInfo.h"
16 #include "NVPTXTargetMachine.h"
17 #include "llvm/ADT/STLExtras.h"
18 #include "llvm/CodeGen/MachineFunction.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/IR/Function.h"
22 
23 using namespace llvm;
24 
25 #define GET_INSTRINFO_CTOR_DTOR
26 #include "NVPTXGenInstrInfo.inc"
27 
28 // Pin the vtable to this file.
29 void NVPTXInstrInfo::anchor() {}
30 
31 NVPTXInstrInfo::NVPTXInstrInfo() : NVPTXGenInstrInfo(), RegInfo() {}
32 
33 void NVPTXInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
34                                  MachineBasicBlock::iterator I,
35                                  const DebugLoc &DL, unsigned DestReg,
36                                  unsigned SrcReg, bool KillSrc) const {
37   const MachineRegisterInfo &MRI = MBB.getParent()->getRegInfo();
38   const TargetRegisterClass *DestRC = MRI.getRegClass(DestReg);
39   const TargetRegisterClass *SrcRC = MRI.getRegClass(SrcReg);
40 
41   if (DestRC->getSize() != SrcRC->getSize())
42     report_fatal_error("Copy one register into another with a different width");
43 
44   unsigned Op;
45   if (DestRC == &NVPTX::Int1RegsRegClass) {
46     Op = NVPTX::IMOV1rr;
47   } else if (DestRC == &NVPTX::Int16RegsRegClass) {
48     Op = NVPTX::IMOV16rr;
49   } else if (DestRC == &NVPTX::Int32RegsRegClass) {
50     Op = (SrcRC == &NVPTX::Int32RegsRegClass ? NVPTX::IMOV32rr
51                                              : NVPTX::BITCONVERT_32_F2I);
52   } else if (DestRC == &NVPTX::Int64RegsRegClass) {
53     Op = (SrcRC == &NVPTX::Int64RegsRegClass ? NVPTX::IMOV64rr
54                                              : NVPTX::BITCONVERT_64_F2I);
55   } else if (DestRC == &NVPTX::Float32RegsRegClass) {
56     Op = (SrcRC == &NVPTX::Float32RegsRegClass ? NVPTX::FMOV32rr
57                                                : NVPTX::BITCONVERT_32_I2F);
58   } else if (DestRC == &NVPTX::Float64RegsRegClass) {
59     Op = (SrcRC == &NVPTX::Float64RegsRegClass ? NVPTX::FMOV64rr
60                                                : NVPTX::BITCONVERT_64_I2F);
61   } else {
62     llvm_unreachable("Bad register copy");
63   }
64   BuildMI(MBB, I, DL, get(Op), DestReg)
65       .addReg(SrcReg, getKillRegState(KillSrc));
66 }
67 
68 bool NVPTXInstrInfo::isMoveInstr(const MachineInstr &MI, unsigned &SrcReg,
69                                  unsigned &DestReg) const {
70   // Look for the appropriate part of TSFlags
71   bool isMove = false;
72 
73   unsigned TSFlags =
74       (MI.getDesc().TSFlags & NVPTX::SimpleMoveMask) >> NVPTX::SimpleMoveShift;
75   isMove = (TSFlags == 1);
76 
77   if (isMove) {
78     MachineOperand dest = MI.getOperand(0);
79     MachineOperand src = MI.getOperand(1);
80     assert(dest.isReg() && "dest of a movrr is not a reg");
81     assert(src.isReg() && "src of a movrr is not a reg");
82 
83     SrcReg = src.getReg();
84     DestReg = dest.getReg();
85     return true;
86   }
87 
88   return false;
89 }
90 
91 bool NVPTXInstrInfo::isLoadInstr(const MachineInstr &MI,
92                                  unsigned &AddrSpace) const {
93   bool isLoad = false;
94   unsigned TSFlags =
95       (MI.getDesc().TSFlags & NVPTX::isLoadMask) >> NVPTX::isLoadShift;
96   isLoad = (TSFlags == 1);
97   if (isLoad)
98     AddrSpace = getLdStCodeAddrSpace(MI);
99   return isLoad;
100 }
101 
102 bool NVPTXInstrInfo::isStoreInstr(const MachineInstr &MI,
103                                   unsigned &AddrSpace) const {
104   bool isStore = false;
105   unsigned TSFlags =
106       (MI.getDesc().TSFlags & NVPTX::isStoreMask) >> NVPTX::isStoreShift;
107   isStore = (TSFlags == 1);
108   if (isStore)
109     AddrSpace = getLdStCodeAddrSpace(MI);
110   return isStore;
111 }
112 
113 bool NVPTXInstrInfo::CanTailMerge(const MachineInstr *MI) const {
114   unsigned addrspace = 0;
115   if (MI->getOpcode() == NVPTX::INT_CUDA_SYNCTHREADS)
116     return false;
117   if (isLoadInstr(*MI, addrspace))
118     if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
119       return false;
120   if (isStoreInstr(*MI, addrspace))
121     if (addrspace == NVPTX::PTXLdStInstCode::SHARED)
122       return false;
123   return true;
124 }
125 
126 /// AnalyzeBranch - Analyze the branching code at the end of MBB, returning
127 /// true if it cannot be understood (e.g. it's a switch dispatch or isn't
128 /// implemented for a target).  Upon success, this returns false and returns
129 /// with the following information in various cases:
130 ///
131 /// 1. If this block ends with no branches (it just falls through to its succ)
132 ///    just return false, leaving TBB/FBB null.
133 /// 2. If this block ends with only an unconditional branch, it sets TBB to be
134 ///    the destination block.
135 /// 3. If this block ends with an conditional branch and it falls through to
136 ///    an successor block, it sets TBB to be the branch destination block and a
137 ///    list of operands that evaluate the condition. These
138 ///    operands can be passed to other TargetInstrInfo methods to create new
139 ///    branches.
140 /// 4. If this block ends with an conditional branch and an unconditional
141 ///    block, it returns the 'true' destination in TBB, the 'false' destination
142 ///    in FBB, and a list of operands that evaluate the condition. These
143 ///    operands can be passed to other TargetInstrInfo methods to create new
144 ///    branches.
145 ///
146 /// Note that RemoveBranch and InsertBranch must be implemented to support
147 /// cases where this method returns success.
148 ///
149 bool NVPTXInstrInfo::AnalyzeBranch(
150     MachineBasicBlock &MBB, MachineBasicBlock *&TBB, MachineBasicBlock *&FBB,
151     SmallVectorImpl<MachineOperand> &Cond, bool AllowModify) const {
152   // If the block has no terminators, it just falls into the block after it.
153   MachineBasicBlock::iterator I = MBB.end();
154   if (I == MBB.begin() || !isUnpredicatedTerminator(*--I))
155     return false;
156 
157   // Get the last instruction in the block.
158   MachineInstr *LastInst = I;
159 
160   // If there is only one terminator instruction, process it.
161   if (I == MBB.begin() || !isUnpredicatedTerminator(*--I)) {
162     if (LastInst->getOpcode() == NVPTX::GOTO) {
163       TBB = LastInst->getOperand(0).getMBB();
164       return false;
165     } else if (LastInst->getOpcode() == NVPTX::CBranch) {
166       // Block ends with fall-through condbranch.
167       TBB = LastInst->getOperand(1).getMBB();
168       Cond.push_back(LastInst->getOperand(0));
169       return false;
170     }
171     // Otherwise, don't know what this is.
172     return true;
173   }
174 
175   // Get the instruction before it if it's a terminator.
176   MachineInstr *SecondLastInst = I;
177 
178   // If there are three terminators, we don't know what sort of block this is.
179   if (SecondLastInst && I != MBB.begin() && isUnpredicatedTerminator(*--I))
180     return true;
181 
182   // If the block ends with NVPTX::GOTO and NVPTX:CBranch, handle it.
183   if (SecondLastInst->getOpcode() == NVPTX::CBranch &&
184       LastInst->getOpcode() == NVPTX::GOTO) {
185     TBB = SecondLastInst->getOperand(1).getMBB();
186     Cond.push_back(SecondLastInst->getOperand(0));
187     FBB = LastInst->getOperand(0).getMBB();
188     return false;
189   }
190 
191   // If the block ends with two NVPTX:GOTOs, handle it.  The second one is not
192   // executed, so remove it.
193   if (SecondLastInst->getOpcode() == NVPTX::GOTO &&
194       LastInst->getOpcode() == NVPTX::GOTO) {
195     TBB = SecondLastInst->getOperand(0).getMBB();
196     I = LastInst;
197     if (AllowModify)
198       I->eraseFromParent();
199     return false;
200   }
201 
202   // Otherwise, can't handle this.
203   return true;
204 }
205 
206 unsigned NVPTXInstrInfo::RemoveBranch(MachineBasicBlock &MBB) const {
207   MachineBasicBlock::iterator I = MBB.end();
208   if (I == MBB.begin())
209     return 0;
210   --I;
211   if (I->getOpcode() != NVPTX::GOTO && I->getOpcode() != NVPTX::CBranch)
212     return 0;
213 
214   // Remove the branch.
215   I->eraseFromParent();
216 
217   I = MBB.end();
218 
219   if (I == MBB.begin())
220     return 1;
221   --I;
222   if (I->getOpcode() != NVPTX::CBranch)
223     return 1;
224 
225   // Remove the branch.
226   I->eraseFromParent();
227   return 2;
228 }
229 
230 unsigned NVPTXInstrInfo::InsertBranch(MachineBasicBlock &MBB,
231                                       MachineBasicBlock *TBB,
232                                       MachineBasicBlock *FBB,
233                                       ArrayRef<MachineOperand> Cond,
234                                       const DebugLoc &DL) const {
235   // Shouldn't be a fall through.
236   assert(TBB && "InsertBranch must not be told to insert a fallthrough");
237   assert((Cond.size() == 1 || Cond.size() == 0) &&
238          "NVPTX branch conditions have two components!");
239 
240   // One-way branch.
241   if (!FBB) {
242     if (Cond.empty()) // Unconditional branch
243       BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(TBB);
244     else // Conditional branch
245       BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg())
246           .addMBB(TBB);
247     return 1;
248   }
249 
250   // Two-way Conditional Branch.
251   BuildMI(&MBB, DL, get(NVPTX::CBranch)).addReg(Cond[0].getReg()).addMBB(TBB);
252   BuildMI(&MBB, DL, get(NVPTX::GOTO)).addMBB(FBB);
253   return 2;
254 }
255