1 //
2 //                     The LLVM Compiler Infrastructure
3 //
4 // This file is distributed under the University of Illinois Open Source
5 // License. See LICENSE.TXT for details.
6 //
7 //===----------------------------------------------------------------------===//
8 //
9 // This file defines the interfaces that NVPTX uses to lower LLVM code into a
10 // selection DAG.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "NVPTXISelLowering.h"
15 #include "NVPTX.h"
16 #include "NVPTXTargetMachine.h"
17 #include "NVPTXTargetObjectFile.h"
18 #include "NVPTXUtilities.h"
19 #include "llvm/CodeGen/Analysis.h"
20 #include "llvm/CodeGen/MachineFrameInfo.h"
21 #include "llvm/CodeGen/MachineFunction.h"
22 #include "llvm/CodeGen/MachineInstrBuilder.h"
23 #include "llvm/CodeGen/MachineRegisterInfo.h"
24 #include "llvm/CodeGen/TargetLoweringObjectFileImpl.h"
25 #include "llvm/IR/CallSite.h"
26 #include "llvm/IR/DerivedTypes.h"
27 #include "llvm/IR/Function.h"
28 #include "llvm/IR/GlobalValue.h"
29 #include "llvm/IR/IntrinsicInst.h"
30 #include "llvm/IR/Intrinsics.h"
31 #include "llvm/IR/Module.h"
32 #include "llvm/MC/MCSectionELF.h"
33 #include "llvm/Support/CommandLine.h"
34 #include "llvm/Support/Debug.h"
35 #include "llvm/Support/ErrorHandling.h"
36 #include "llvm/Support/MathExtras.h"
37 #include "llvm/Support/raw_ostream.h"
38 #include <sstream>
39 
40 #undef DEBUG_TYPE
41 #define DEBUG_TYPE "nvptx-lower"
42 
43 using namespace llvm;
44 
45 static unsigned int uniqueCallSite = 0;
46 
47 static cl::opt<bool> sched4reg(
48     "nvptx-sched4reg",
49     cl::desc("NVPTX Specific: schedule for register pressue"), cl::init(false));
50 
51 static cl::opt<unsigned>
52 FMAContractLevelOpt("nvptx-fma-level", cl::ZeroOrMore, cl::Hidden,
53                     cl::desc("NVPTX Specific: FMA contraction (0: don't do it"
54                              " 1: do it  2: do it aggressively"),
55                     cl::init(2));
56 
57 static bool IsPTXVectorType(MVT VT) {
58   switch (VT.SimpleTy) {
59   default:
60     return false;
61   case MVT::v2i1:
62   case MVT::v4i1:
63   case MVT::v2i8:
64   case MVT::v4i8:
65   case MVT::v2i16:
66   case MVT::v4i16:
67   case MVT::v2i32:
68   case MVT::v4i32:
69   case MVT::v2i64:
70   case MVT::v2f32:
71   case MVT::v4f32:
72   case MVT::v2f64:
73     return true;
74   }
75 }
76 
77 /// ComputePTXValueVTs - For the given Type \p Ty, returns the set of primitive
78 /// EVTs that compose it.  Unlike ComputeValueVTs, this will break apart vectors
79 /// into their primitive components.
80 /// NOTE: This is a band-aid for code that expects ComputeValueVTs to return the
81 /// same number of types as the Ins/Outs arrays in LowerFormalArguments,
82 /// LowerCall, and LowerReturn.
83 static void ComputePTXValueVTs(const TargetLowering &TLI, const DataLayout &DL,
84                                Type *Ty, SmallVectorImpl<EVT> &ValueVTs,
85                                SmallVectorImpl<uint64_t> *Offsets = nullptr,
86                                uint64_t StartingOffset = 0) {
87   SmallVector<EVT, 16> TempVTs;
88   SmallVector<uint64_t, 16> TempOffsets;
89 
90   ComputeValueVTs(TLI, DL, Ty, TempVTs, &TempOffsets, StartingOffset);
91   for (unsigned i = 0, e = TempVTs.size(); i != e; ++i) {
92     EVT VT = TempVTs[i];
93     uint64_t Off = TempOffsets[i];
94     if (VT.isVector())
95       for (unsigned j = 0, je = VT.getVectorNumElements(); j != je; ++j) {
96         ValueVTs.push_back(VT.getVectorElementType());
97         if (Offsets)
98           Offsets->push_back(Off+j*VT.getVectorElementType().getStoreSize());
99       }
100     else {
101       ValueVTs.push_back(VT);
102       if (Offsets)
103         Offsets->push_back(Off);
104     }
105   }
106 }
107 
108 // NVPTXTargetLowering Constructor.
109 NVPTXTargetLowering::NVPTXTargetLowering(const NVPTXTargetMachine &TM,
110                                          const NVPTXSubtarget &STI)
111     : TargetLowering(TM), nvTM(&TM), STI(STI) {
112 
113   // always lower memset, memcpy, and memmove intrinsics to load/store
114   // instructions, rather
115   // then generating calls to memset, mempcy or memmove.
116   MaxStoresPerMemset = (unsigned) 0xFFFFFFFF;
117   MaxStoresPerMemcpy = (unsigned) 0xFFFFFFFF;
118   MaxStoresPerMemmove = (unsigned) 0xFFFFFFFF;
119 
120   setBooleanContents(ZeroOrNegativeOneBooleanContent);
121   setBooleanVectorContents(ZeroOrNegativeOneBooleanContent);
122 
123   // Jump is Expensive. Don't create extra control flow for 'and', 'or'
124   // condition branches.
125   setJumpIsExpensive(true);
126 
127   // Wide divides are _very_ slow. Try to reduce the width of the divide if
128   // possible.
129   addBypassSlowDiv(64, 32);
130 
131   // By default, use the Source scheduling
132   if (sched4reg)
133     setSchedulingPreference(Sched::RegPressure);
134   else
135     setSchedulingPreference(Sched::Source);
136 
137   addRegisterClass(MVT::i1, &NVPTX::Int1RegsRegClass);
138   addRegisterClass(MVT::i16, &NVPTX::Int16RegsRegClass);
139   addRegisterClass(MVT::i32, &NVPTX::Int32RegsRegClass);
140   addRegisterClass(MVT::i64, &NVPTX::Int64RegsRegClass);
141   addRegisterClass(MVT::f32, &NVPTX::Float32RegsRegClass);
142   addRegisterClass(MVT::f64, &NVPTX::Float64RegsRegClass);
143 
144   // Operations not directly supported by NVPTX.
145   setOperationAction(ISD::SELECT_CC, MVT::f32, Expand);
146   setOperationAction(ISD::SELECT_CC, MVT::f64, Expand);
147   setOperationAction(ISD::SELECT_CC, MVT::i1, Expand);
148   setOperationAction(ISD::SELECT_CC, MVT::i8, Expand);
149   setOperationAction(ISD::SELECT_CC, MVT::i16, Expand);
150   setOperationAction(ISD::SELECT_CC, MVT::i32, Expand);
151   setOperationAction(ISD::SELECT_CC, MVT::i64, Expand);
152   setOperationAction(ISD::BR_CC, MVT::f32, Expand);
153   setOperationAction(ISD::BR_CC, MVT::f64, Expand);
154   setOperationAction(ISD::BR_CC, MVT::i1, Expand);
155   setOperationAction(ISD::BR_CC, MVT::i8, Expand);
156   setOperationAction(ISD::BR_CC, MVT::i16, Expand);
157   setOperationAction(ISD::BR_CC, MVT::i32, Expand);
158   setOperationAction(ISD::BR_CC, MVT::i64, Expand);
159   // Some SIGN_EXTEND_INREG can be done using cvt instruction.
160   // For others we will expand to a SHL/SRA pair.
161   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i64, Legal);
162   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i32, Legal);
163   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i16, Legal);
164   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i8 , Legal);
165   setOperationAction(ISD::SIGN_EXTEND_INREG, MVT::i1, Expand);
166 
167   setOperationAction(ISD::SHL_PARTS, MVT::i32  , Custom);
168   setOperationAction(ISD::SRA_PARTS, MVT::i32  , Custom);
169   setOperationAction(ISD::SRL_PARTS, MVT::i32  , Custom);
170   setOperationAction(ISD::SHL_PARTS, MVT::i64  , Custom);
171   setOperationAction(ISD::SRA_PARTS, MVT::i64  , Custom);
172   setOperationAction(ISD::SRL_PARTS, MVT::i64  , Custom);
173 
174   if (STI.hasROT64()) {
175     setOperationAction(ISD::ROTL, MVT::i64, Legal);
176     setOperationAction(ISD::ROTR, MVT::i64, Legal);
177   } else {
178     setOperationAction(ISD::ROTL, MVT::i64, Expand);
179     setOperationAction(ISD::ROTR, MVT::i64, Expand);
180   }
181   if (STI.hasROT32()) {
182     setOperationAction(ISD::ROTL, MVT::i32, Legal);
183     setOperationAction(ISD::ROTR, MVT::i32, Legal);
184   } else {
185     setOperationAction(ISD::ROTL, MVT::i32, Expand);
186     setOperationAction(ISD::ROTR, MVT::i32, Expand);
187   }
188 
189   setOperationAction(ISD::ROTL, MVT::i16, Expand);
190   setOperationAction(ISD::ROTR, MVT::i16, Expand);
191   setOperationAction(ISD::ROTL, MVT::i8, Expand);
192   setOperationAction(ISD::ROTR, MVT::i8, Expand);
193   setOperationAction(ISD::BSWAP, MVT::i16, Expand);
194   setOperationAction(ISD::BSWAP, MVT::i32, Expand);
195   setOperationAction(ISD::BSWAP, MVT::i64, Expand);
196 
197   // Indirect branch is not supported.
198   // This also disables Jump Table creation.
199   setOperationAction(ISD::BR_JT, MVT::Other, Expand);
200   setOperationAction(ISD::BRIND, MVT::Other, Expand);
201 
202   setOperationAction(ISD::GlobalAddress, MVT::i32, Custom);
203   setOperationAction(ISD::GlobalAddress, MVT::i64, Custom);
204 
205   // We want to legalize constant related memmove and memcopy
206   // intrinsics.
207   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom);
208 
209   // Turn FP extload into load/fextend
210   setLoadExtAction(ISD::EXTLOAD, MVT::f32, MVT::f16, Expand);
211   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f16, Expand);
212   setLoadExtAction(ISD::EXTLOAD, MVT::f64, MVT::f32, Expand);
213   setLoadExtAction(ISD::EXTLOAD, MVT::v2f32, MVT::v2f16, Expand);
214   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f16, Expand);
215   setLoadExtAction(ISD::EXTLOAD, MVT::v2f64, MVT::v2f32, Expand);
216   setLoadExtAction(ISD::EXTLOAD, MVT::v4f32, MVT::v4f16, Expand);
217   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f16, Expand);
218   setLoadExtAction(ISD::EXTLOAD, MVT::v4f64, MVT::v4f32, Expand);
219   // Turn FP truncstore into trunc + store.
220   // FIXME: vector types should also be expanded
221   setTruncStoreAction(MVT::f32, MVT::f16, Expand);
222   setTruncStoreAction(MVT::f64, MVT::f16, Expand);
223   setTruncStoreAction(MVT::f64, MVT::f32, Expand);
224 
225   // PTX does not support load / store predicate registers
226   setOperationAction(ISD::LOAD, MVT::i1, Custom);
227   setOperationAction(ISD::STORE, MVT::i1, Custom);
228 
229   for (MVT VT : MVT::integer_valuetypes()) {
230     setLoadExtAction(ISD::SEXTLOAD, VT, MVT::i1, Promote);
231     setLoadExtAction(ISD::ZEXTLOAD, VT, MVT::i1, Promote);
232     setTruncStoreAction(VT, MVT::i1, Expand);
233   }
234 
235   // This is legal in NVPTX
236   setOperationAction(ISD::ConstantFP, MVT::f64, Legal);
237   setOperationAction(ISD::ConstantFP, MVT::f32, Legal);
238 
239   // TRAP can be lowered to PTX trap
240   setOperationAction(ISD::TRAP, MVT::Other, Legal);
241 
242   setOperationAction(ISD::ADDC, MVT::i64, Expand);
243   setOperationAction(ISD::ADDE, MVT::i64, Expand);
244 
245   // Register custom handling for vector loads/stores
246   for (MVT VT : MVT::vector_valuetypes()) {
247     if (IsPTXVectorType(VT)) {
248       setOperationAction(ISD::LOAD, VT, Custom);
249       setOperationAction(ISD::STORE, VT, Custom);
250       setOperationAction(ISD::INTRINSIC_W_CHAIN, VT, Custom);
251     }
252   }
253 
254   // Custom handling for i8 intrinsics
255   setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i8, Custom);
256 
257   setOperationAction(ISD::CTLZ, MVT::i16, Legal);
258   setOperationAction(ISD::CTLZ, MVT::i32, Legal);
259   setOperationAction(ISD::CTLZ, MVT::i64, Legal);
260   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i16, Legal);
261   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i32, Legal);
262   setOperationAction(ISD::CTLZ_ZERO_UNDEF, MVT::i64, Legal);
263   setOperationAction(ISD::CTTZ, MVT::i16, Expand);
264   setOperationAction(ISD::CTTZ, MVT::i32, Expand);
265   setOperationAction(ISD::CTTZ, MVT::i64, Expand);
266   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i16, Expand);
267   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i32, Expand);
268   setOperationAction(ISD::CTTZ_ZERO_UNDEF, MVT::i64, Expand);
269   setOperationAction(ISD::CTPOP, MVT::i16, Legal);
270   setOperationAction(ISD::CTPOP, MVT::i32, Legal);
271   setOperationAction(ISD::CTPOP, MVT::i64, Legal);
272 
273   // PTX does not directly support SELP of i1, so promote to i32 first
274   setOperationAction(ISD::SELECT, MVT::i1, Custom);
275 
276   // PTX cannot multiply two i64s in a single instruction.
277   setOperationAction(ISD::SMUL_LOHI, MVT::i64, Expand);
278   setOperationAction(ISD::UMUL_LOHI, MVT::i64, Expand);
279 
280   // We have some custom DAG combine patterns for these nodes
281   setTargetDAGCombine(ISD::ADD);
282   setTargetDAGCombine(ISD::AND);
283   setTargetDAGCombine(ISD::FADD);
284   setTargetDAGCombine(ISD::MUL);
285   setTargetDAGCombine(ISD::SHL);
286   setTargetDAGCombine(ISD::SELECT);
287 
288   // Now deduce the information based on the above mentioned
289   // actions
290   computeRegisterProperties(STI.getRegisterInfo());
291 }
292 
293 const char *NVPTXTargetLowering::getTargetNodeName(unsigned Opcode) const {
294   switch ((NVPTXISD::NodeType)Opcode) {
295   case NVPTXISD::FIRST_NUMBER:
296     break;
297   case NVPTXISD::CALL:
298     return "NVPTXISD::CALL";
299   case NVPTXISD::RET_FLAG:
300     return "NVPTXISD::RET_FLAG";
301   case NVPTXISD::LOAD_PARAM:
302     return "NVPTXISD::LOAD_PARAM";
303   case NVPTXISD::Wrapper:
304     return "NVPTXISD::Wrapper";
305   case NVPTXISD::DeclareParam:
306     return "NVPTXISD::DeclareParam";
307   case NVPTXISD::DeclareScalarParam:
308     return "NVPTXISD::DeclareScalarParam";
309   case NVPTXISD::DeclareRet:
310     return "NVPTXISD::DeclareRet";
311   case NVPTXISD::DeclareScalarRet:
312     return "NVPTXISD::DeclareScalarRet";
313   case NVPTXISD::DeclareRetParam:
314     return "NVPTXISD::DeclareRetParam";
315   case NVPTXISD::PrintCall:
316     return "NVPTXISD::PrintCall";
317   case NVPTXISD::PrintCallUni:
318     return "NVPTXISD::PrintCallUni";
319   case NVPTXISD::LoadParam:
320     return "NVPTXISD::LoadParam";
321   case NVPTXISD::LoadParamV2:
322     return "NVPTXISD::LoadParamV2";
323   case NVPTXISD::LoadParamV4:
324     return "NVPTXISD::LoadParamV4";
325   case NVPTXISD::StoreParam:
326     return "NVPTXISD::StoreParam";
327   case NVPTXISD::StoreParamV2:
328     return "NVPTXISD::StoreParamV2";
329   case NVPTXISD::StoreParamV4:
330     return "NVPTXISD::StoreParamV4";
331   case NVPTXISD::StoreParamS32:
332     return "NVPTXISD::StoreParamS32";
333   case NVPTXISD::StoreParamU32:
334     return "NVPTXISD::StoreParamU32";
335   case NVPTXISD::CallArgBegin:
336     return "NVPTXISD::CallArgBegin";
337   case NVPTXISD::CallArg:
338     return "NVPTXISD::CallArg";
339   case NVPTXISD::LastCallArg:
340     return "NVPTXISD::LastCallArg";
341   case NVPTXISD::CallArgEnd:
342     return "NVPTXISD::CallArgEnd";
343   case NVPTXISD::CallVoid:
344     return "NVPTXISD::CallVoid";
345   case NVPTXISD::CallVal:
346     return "NVPTXISD::CallVal";
347   case NVPTXISD::CallSymbol:
348     return "NVPTXISD::CallSymbol";
349   case NVPTXISD::Prototype:
350     return "NVPTXISD::Prototype";
351   case NVPTXISD::MoveParam:
352     return "NVPTXISD::MoveParam";
353   case NVPTXISD::StoreRetval:
354     return "NVPTXISD::StoreRetval";
355   case NVPTXISD::StoreRetvalV2:
356     return "NVPTXISD::StoreRetvalV2";
357   case NVPTXISD::StoreRetvalV4:
358     return "NVPTXISD::StoreRetvalV4";
359   case NVPTXISD::PseudoUseParam:
360     return "NVPTXISD::PseudoUseParam";
361   case NVPTXISD::RETURN:
362     return "NVPTXISD::RETURN";
363   case NVPTXISD::CallSeqBegin:
364     return "NVPTXISD::CallSeqBegin";
365   case NVPTXISD::CallSeqEnd:
366     return "NVPTXISD::CallSeqEnd";
367   case NVPTXISD::CallPrototype:
368     return "NVPTXISD::CallPrototype";
369   case NVPTXISD::LoadV2:
370     return "NVPTXISD::LoadV2";
371   case NVPTXISD::LoadV4:
372     return "NVPTXISD::LoadV4";
373   case NVPTXISD::LDGV2:
374     return "NVPTXISD::LDGV2";
375   case NVPTXISD::LDGV4:
376     return "NVPTXISD::LDGV4";
377   case NVPTXISD::LDUV2:
378     return "NVPTXISD::LDUV2";
379   case NVPTXISD::LDUV4:
380     return "NVPTXISD::LDUV4";
381   case NVPTXISD::StoreV2:
382     return "NVPTXISD::StoreV2";
383   case NVPTXISD::StoreV4:
384     return "NVPTXISD::StoreV4";
385   case NVPTXISD::FUN_SHFL_CLAMP:
386     return "NVPTXISD::FUN_SHFL_CLAMP";
387   case NVPTXISD::FUN_SHFR_CLAMP:
388     return "NVPTXISD::FUN_SHFR_CLAMP";
389   case NVPTXISD::IMAD:
390     return "NVPTXISD::IMAD";
391   case NVPTXISD::Dummy:
392     return "NVPTXISD::Dummy";
393   case NVPTXISD::MUL_WIDE_SIGNED:
394     return "NVPTXISD::MUL_WIDE_SIGNED";
395   case NVPTXISD::MUL_WIDE_UNSIGNED:
396     return "NVPTXISD::MUL_WIDE_UNSIGNED";
397   case NVPTXISD::Tex1DFloatS32:        return "NVPTXISD::Tex1DFloatS32";
398   case NVPTXISD::Tex1DFloatFloat:      return "NVPTXISD::Tex1DFloatFloat";
399   case NVPTXISD::Tex1DFloatFloatLevel:
400     return "NVPTXISD::Tex1DFloatFloatLevel";
401   case NVPTXISD::Tex1DFloatFloatGrad:
402     return "NVPTXISD::Tex1DFloatFloatGrad";
403   case NVPTXISD::Tex1DS32S32:          return "NVPTXISD::Tex1DS32S32";
404   case NVPTXISD::Tex1DS32Float:        return "NVPTXISD::Tex1DS32Float";
405   case NVPTXISD::Tex1DS32FloatLevel:
406     return "NVPTXISD::Tex1DS32FloatLevel";
407   case NVPTXISD::Tex1DS32FloatGrad:
408     return "NVPTXISD::Tex1DS32FloatGrad";
409   case NVPTXISD::Tex1DU32S32:          return "NVPTXISD::Tex1DU32S32";
410   case NVPTXISD::Tex1DU32Float:        return "NVPTXISD::Tex1DU32Float";
411   case NVPTXISD::Tex1DU32FloatLevel:
412     return "NVPTXISD::Tex1DU32FloatLevel";
413   case NVPTXISD::Tex1DU32FloatGrad:
414     return "NVPTXISD::Tex1DU32FloatGrad";
415   case NVPTXISD::Tex1DArrayFloatS32:   return "NVPTXISD::Tex1DArrayFloatS32";
416   case NVPTXISD::Tex1DArrayFloatFloat: return "NVPTXISD::Tex1DArrayFloatFloat";
417   case NVPTXISD::Tex1DArrayFloatFloatLevel:
418     return "NVPTXISD::Tex1DArrayFloatFloatLevel";
419   case NVPTXISD::Tex1DArrayFloatFloatGrad:
420     return "NVPTXISD::Tex1DArrayFloatFloatGrad";
421   case NVPTXISD::Tex1DArrayS32S32:     return "NVPTXISD::Tex1DArrayS32S32";
422   case NVPTXISD::Tex1DArrayS32Float:   return "NVPTXISD::Tex1DArrayS32Float";
423   case NVPTXISD::Tex1DArrayS32FloatLevel:
424     return "NVPTXISD::Tex1DArrayS32FloatLevel";
425   case NVPTXISD::Tex1DArrayS32FloatGrad:
426     return "NVPTXISD::Tex1DArrayS32FloatGrad";
427   case NVPTXISD::Tex1DArrayU32S32:     return "NVPTXISD::Tex1DArrayU32S32";
428   case NVPTXISD::Tex1DArrayU32Float:   return "NVPTXISD::Tex1DArrayU32Float";
429   case NVPTXISD::Tex1DArrayU32FloatLevel:
430     return "NVPTXISD::Tex1DArrayU32FloatLevel";
431   case NVPTXISD::Tex1DArrayU32FloatGrad:
432     return "NVPTXISD::Tex1DArrayU32FloatGrad";
433   case NVPTXISD::Tex2DFloatS32:        return "NVPTXISD::Tex2DFloatS32";
434   case NVPTXISD::Tex2DFloatFloat:      return "NVPTXISD::Tex2DFloatFloat";
435   case NVPTXISD::Tex2DFloatFloatLevel:
436     return "NVPTXISD::Tex2DFloatFloatLevel";
437   case NVPTXISD::Tex2DFloatFloatGrad:
438     return "NVPTXISD::Tex2DFloatFloatGrad";
439   case NVPTXISD::Tex2DS32S32:          return "NVPTXISD::Tex2DS32S32";
440   case NVPTXISD::Tex2DS32Float:        return "NVPTXISD::Tex2DS32Float";
441   case NVPTXISD::Tex2DS32FloatLevel:
442     return "NVPTXISD::Tex2DS32FloatLevel";
443   case NVPTXISD::Tex2DS32FloatGrad:
444     return "NVPTXISD::Tex2DS32FloatGrad";
445   case NVPTXISD::Tex2DU32S32:          return "NVPTXISD::Tex2DU32S32";
446   case NVPTXISD::Tex2DU32Float:        return "NVPTXISD::Tex2DU32Float";
447   case NVPTXISD::Tex2DU32FloatLevel:
448     return "NVPTXISD::Tex2DU32FloatLevel";
449   case NVPTXISD::Tex2DU32FloatGrad:
450     return "NVPTXISD::Tex2DU32FloatGrad";
451   case NVPTXISD::Tex2DArrayFloatS32:   return "NVPTXISD::Tex2DArrayFloatS32";
452   case NVPTXISD::Tex2DArrayFloatFloat: return "NVPTXISD::Tex2DArrayFloatFloat";
453   case NVPTXISD::Tex2DArrayFloatFloatLevel:
454     return "NVPTXISD::Tex2DArrayFloatFloatLevel";
455   case NVPTXISD::Tex2DArrayFloatFloatGrad:
456     return "NVPTXISD::Tex2DArrayFloatFloatGrad";
457   case NVPTXISD::Tex2DArrayS32S32:     return "NVPTXISD::Tex2DArrayS32S32";
458   case NVPTXISD::Tex2DArrayS32Float:   return "NVPTXISD::Tex2DArrayS32Float";
459   case NVPTXISD::Tex2DArrayS32FloatLevel:
460     return "NVPTXISD::Tex2DArrayS32FloatLevel";
461   case NVPTXISD::Tex2DArrayS32FloatGrad:
462     return "NVPTXISD::Tex2DArrayS32FloatGrad";
463   case NVPTXISD::Tex2DArrayU32S32:     return "NVPTXISD::Tex2DArrayU32S32";
464   case NVPTXISD::Tex2DArrayU32Float:   return "NVPTXISD::Tex2DArrayU32Float";
465   case NVPTXISD::Tex2DArrayU32FloatLevel:
466     return "NVPTXISD::Tex2DArrayU32FloatLevel";
467   case NVPTXISD::Tex2DArrayU32FloatGrad:
468     return "NVPTXISD::Tex2DArrayU32FloatGrad";
469   case NVPTXISD::Tex3DFloatS32:        return "NVPTXISD::Tex3DFloatS32";
470   case NVPTXISD::Tex3DFloatFloat:      return "NVPTXISD::Tex3DFloatFloat";
471   case NVPTXISD::Tex3DFloatFloatLevel:
472     return "NVPTXISD::Tex3DFloatFloatLevel";
473   case NVPTXISD::Tex3DFloatFloatGrad:
474     return "NVPTXISD::Tex3DFloatFloatGrad";
475   case NVPTXISD::Tex3DS32S32:          return "NVPTXISD::Tex3DS32S32";
476   case NVPTXISD::Tex3DS32Float:        return "NVPTXISD::Tex3DS32Float";
477   case NVPTXISD::Tex3DS32FloatLevel:
478     return "NVPTXISD::Tex3DS32FloatLevel";
479   case NVPTXISD::Tex3DS32FloatGrad:
480     return "NVPTXISD::Tex3DS32FloatGrad";
481   case NVPTXISD::Tex3DU32S32:          return "NVPTXISD::Tex3DU32S32";
482   case NVPTXISD::Tex3DU32Float:        return "NVPTXISD::Tex3DU32Float";
483   case NVPTXISD::Tex3DU32FloatLevel:
484     return "NVPTXISD::Tex3DU32FloatLevel";
485   case NVPTXISD::Tex3DU32FloatGrad:
486     return "NVPTXISD::Tex3DU32FloatGrad";
487   case NVPTXISD::TexCubeFloatFloat:      return "NVPTXISD::TexCubeFloatFloat";
488   case NVPTXISD::TexCubeFloatFloatLevel:
489     return "NVPTXISD::TexCubeFloatFloatLevel";
490   case NVPTXISD::TexCubeS32Float:        return "NVPTXISD::TexCubeS32Float";
491   case NVPTXISD::TexCubeS32FloatLevel:
492     return "NVPTXISD::TexCubeS32FloatLevel";
493   case NVPTXISD::TexCubeU32Float:        return "NVPTXISD::TexCubeU32Float";
494   case NVPTXISD::TexCubeU32FloatLevel:
495     return "NVPTXISD::TexCubeU32FloatLevel";
496   case NVPTXISD::TexCubeArrayFloatFloat:
497     return "NVPTXISD::TexCubeArrayFloatFloat";
498   case NVPTXISD::TexCubeArrayFloatFloatLevel:
499     return "NVPTXISD::TexCubeArrayFloatFloatLevel";
500   case NVPTXISD::TexCubeArrayS32Float:
501     return "NVPTXISD::TexCubeArrayS32Float";
502   case NVPTXISD::TexCubeArrayS32FloatLevel:
503     return "NVPTXISD::TexCubeArrayS32FloatLevel";
504   case NVPTXISD::TexCubeArrayU32Float:
505     return "NVPTXISD::TexCubeArrayU32Float";
506   case NVPTXISD::TexCubeArrayU32FloatLevel:
507     return "NVPTXISD::TexCubeArrayU32FloatLevel";
508   case NVPTXISD::Tld4R2DFloatFloat:
509     return "NVPTXISD::Tld4R2DFloatFloat";
510   case NVPTXISD::Tld4G2DFloatFloat:
511     return "NVPTXISD::Tld4G2DFloatFloat";
512   case NVPTXISD::Tld4B2DFloatFloat:
513     return "NVPTXISD::Tld4B2DFloatFloat";
514   case NVPTXISD::Tld4A2DFloatFloat:
515     return "NVPTXISD::Tld4A2DFloatFloat";
516   case NVPTXISD::Tld4R2DS64Float:
517     return "NVPTXISD::Tld4R2DS64Float";
518   case NVPTXISD::Tld4G2DS64Float:
519     return "NVPTXISD::Tld4G2DS64Float";
520   case NVPTXISD::Tld4B2DS64Float:
521     return "NVPTXISD::Tld4B2DS64Float";
522   case NVPTXISD::Tld4A2DS64Float:
523     return "NVPTXISD::Tld4A2DS64Float";
524   case NVPTXISD::Tld4R2DU64Float:
525     return "NVPTXISD::Tld4R2DU64Float";
526   case NVPTXISD::Tld4G2DU64Float:
527     return "NVPTXISD::Tld4G2DU64Float";
528   case NVPTXISD::Tld4B2DU64Float:
529     return "NVPTXISD::Tld4B2DU64Float";
530   case NVPTXISD::Tld4A2DU64Float:
531     return "NVPTXISD::Tld4A2DU64Float";
532 
533   case NVPTXISD::TexUnified1DFloatS32:
534     return "NVPTXISD::TexUnified1DFloatS32";
535   case NVPTXISD::TexUnified1DFloatFloat:
536     return "NVPTXISD::TexUnified1DFloatFloat";
537   case NVPTXISD::TexUnified1DFloatFloatLevel:
538     return "NVPTXISD::TexUnified1DFloatFloatLevel";
539   case NVPTXISD::TexUnified1DFloatFloatGrad:
540     return "NVPTXISD::TexUnified1DFloatFloatGrad";
541   case NVPTXISD::TexUnified1DS32S32:
542     return "NVPTXISD::TexUnified1DS32S32";
543   case NVPTXISD::TexUnified1DS32Float:
544     return "NVPTXISD::TexUnified1DS32Float";
545   case NVPTXISD::TexUnified1DS32FloatLevel:
546     return "NVPTXISD::TexUnified1DS32FloatLevel";
547   case NVPTXISD::TexUnified1DS32FloatGrad:
548     return "NVPTXISD::TexUnified1DS32FloatGrad";
549   case NVPTXISD::TexUnified1DU32S32:
550     return "NVPTXISD::TexUnified1DU32S32";
551   case NVPTXISD::TexUnified1DU32Float:
552     return "NVPTXISD::TexUnified1DU32Float";
553   case NVPTXISD::TexUnified1DU32FloatLevel:
554     return "NVPTXISD::TexUnified1DU32FloatLevel";
555   case NVPTXISD::TexUnified1DU32FloatGrad:
556     return "NVPTXISD::TexUnified1DU32FloatGrad";
557   case NVPTXISD::TexUnified1DArrayFloatS32:
558     return "NVPTXISD::TexUnified1DArrayFloatS32";
559   case NVPTXISD::TexUnified1DArrayFloatFloat:
560     return "NVPTXISD::TexUnified1DArrayFloatFloat";
561   case NVPTXISD::TexUnified1DArrayFloatFloatLevel:
562     return "NVPTXISD::TexUnified1DArrayFloatFloatLevel";
563   case NVPTXISD::TexUnified1DArrayFloatFloatGrad:
564     return "NVPTXISD::TexUnified1DArrayFloatFloatGrad";
565   case NVPTXISD::TexUnified1DArrayS32S32:
566     return "NVPTXISD::TexUnified1DArrayS32S32";
567   case NVPTXISD::TexUnified1DArrayS32Float:
568     return "NVPTXISD::TexUnified1DArrayS32Float";
569   case NVPTXISD::TexUnified1DArrayS32FloatLevel:
570     return "NVPTXISD::TexUnified1DArrayS32FloatLevel";
571   case NVPTXISD::TexUnified1DArrayS32FloatGrad:
572     return "NVPTXISD::TexUnified1DArrayS32FloatGrad";
573   case NVPTXISD::TexUnified1DArrayU32S32:
574     return "NVPTXISD::TexUnified1DArrayU32S32";
575   case NVPTXISD::TexUnified1DArrayU32Float:
576     return "NVPTXISD::TexUnified1DArrayU32Float";
577   case NVPTXISD::TexUnified1DArrayU32FloatLevel:
578     return "NVPTXISD::TexUnified1DArrayU32FloatLevel";
579   case NVPTXISD::TexUnified1DArrayU32FloatGrad:
580     return "NVPTXISD::TexUnified1DArrayU32FloatGrad";
581   case NVPTXISD::TexUnified2DFloatS32:
582     return "NVPTXISD::TexUnified2DFloatS32";
583   case NVPTXISD::TexUnified2DFloatFloat:
584     return "NVPTXISD::TexUnified2DFloatFloat";
585   case NVPTXISD::TexUnified2DFloatFloatLevel:
586     return "NVPTXISD::TexUnified2DFloatFloatLevel";
587   case NVPTXISD::TexUnified2DFloatFloatGrad:
588     return "NVPTXISD::TexUnified2DFloatFloatGrad";
589   case NVPTXISD::TexUnified2DS32S32:
590     return "NVPTXISD::TexUnified2DS32S32";
591   case NVPTXISD::TexUnified2DS32Float:
592     return "NVPTXISD::TexUnified2DS32Float";
593   case NVPTXISD::TexUnified2DS32FloatLevel:
594     return "NVPTXISD::TexUnified2DS32FloatLevel";
595   case NVPTXISD::TexUnified2DS32FloatGrad:
596     return "NVPTXISD::TexUnified2DS32FloatGrad";
597   case NVPTXISD::TexUnified2DU32S32:
598     return "NVPTXISD::TexUnified2DU32S32";
599   case NVPTXISD::TexUnified2DU32Float:
600     return "NVPTXISD::TexUnified2DU32Float";
601   case NVPTXISD::TexUnified2DU32FloatLevel:
602     return "NVPTXISD::TexUnified2DU32FloatLevel";
603   case NVPTXISD::TexUnified2DU32FloatGrad:
604     return "NVPTXISD::TexUnified2DU32FloatGrad";
605   case NVPTXISD::TexUnified2DArrayFloatS32:
606     return "NVPTXISD::TexUnified2DArrayFloatS32";
607   case NVPTXISD::TexUnified2DArrayFloatFloat:
608     return "NVPTXISD::TexUnified2DArrayFloatFloat";
609   case NVPTXISD::TexUnified2DArrayFloatFloatLevel:
610     return "NVPTXISD::TexUnified2DArrayFloatFloatLevel";
611   case NVPTXISD::TexUnified2DArrayFloatFloatGrad:
612     return "NVPTXISD::TexUnified2DArrayFloatFloatGrad";
613   case NVPTXISD::TexUnified2DArrayS32S32:
614     return "NVPTXISD::TexUnified2DArrayS32S32";
615   case NVPTXISD::TexUnified2DArrayS32Float:
616     return "NVPTXISD::TexUnified2DArrayS32Float";
617   case NVPTXISD::TexUnified2DArrayS32FloatLevel:
618     return "NVPTXISD::TexUnified2DArrayS32FloatLevel";
619   case NVPTXISD::TexUnified2DArrayS32FloatGrad:
620     return "NVPTXISD::TexUnified2DArrayS32FloatGrad";
621   case NVPTXISD::TexUnified2DArrayU32S32:
622     return "NVPTXISD::TexUnified2DArrayU32S32";
623   case NVPTXISD::TexUnified2DArrayU32Float:
624     return "NVPTXISD::TexUnified2DArrayU32Float";
625   case NVPTXISD::TexUnified2DArrayU32FloatLevel:
626     return "NVPTXISD::TexUnified2DArrayU32FloatLevel";
627   case NVPTXISD::TexUnified2DArrayU32FloatGrad:
628     return "NVPTXISD::TexUnified2DArrayU32FloatGrad";
629   case NVPTXISD::TexUnified3DFloatS32:
630     return "NVPTXISD::TexUnified3DFloatS32";
631   case NVPTXISD::TexUnified3DFloatFloat:
632     return "NVPTXISD::TexUnified3DFloatFloat";
633   case NVPTXISD::TexUnified3DFloatFloatLevel:
634     return "NVPTXISD::TexUnified3DFloatFloatLevel";
635   case NVPTXISD::TexUnified3DFloatFloatGrad:
636     return "NVPTXISD::TexUnified3DFloatFloatGrad";
637   case NVPTXISD::TexUnified3DS32S32:
638     return "NVPTXISD::TexUnified3DS32S32";
639   case NVPTXISD::TexUnified3DS32Float:
640     return "NVPTXISD::TexUnified3DS32Float";
641   case NVPTXISD::TexUnified3DS32FloatLevel:
642     return "NVPTXISD::TexUnified3DS32FloatLevel";
643   case NVPTXISD::TexUnified3DS32FloatGrad:
644     return "NVPTXISD::TexUnified3DS32FloatGrad";
645   case NVPTXISD::TexUnified3DU32S32:
646     return "NVPTXISD::TexUnified3DU32S32";
647   case NVPTXISD::TexUnified3DU32Float:
648     return "NVPTXISD::TexUnified3DU32Float";
649   case NVPTXISD::TexUnified3DU32FloatLevel:
650     return "NVPTXISD::TexUnified3DU32FloatLevel";
651   case NVPTXISD::TexUnified3DU32FloatGrad:
652     return "NVPTXISD::TexUnified3DU32FloatGrad";
653   case NVPTXISD::TexUnifiedCubeFloatFloat:
654     return "NVPTXISD::TexUnifiedCubeFloatFloat";
655   case NVPTXISD::TexUnifiedCubeFloatFloatLevel:
656     return "NVPTXISD::TexUnifiedCubeFloatFloatLevel";
657   case NVPTXISD::TexUnifiedCubeS32Float:
658     return "NVPTXISD::TexUnifiedCubeS32Float";
659   case NVPTXISD::TexUnifiedCubeS32FloatLevel:
660     return "NVPTXISD::TexUnifiedCubeS32FloatLevel";
661   case NVPTXISD::TexUnifiedCubeU32Float:
662     return "NVPTXISD::TexUnifiedCubeU32Float";
663   case NVPTXISD::TexUnifiedCubeU32FloatLevel:
664     return "NVPTXISD::TexUnifiedCubeU32FloatLevel";
665   case NVPTXISD::TexUnifiedCubeArrayFloatFloat:
666     return "NVPTXISD::TexUnifiedCubeArrayFloatFloat";
667   case NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel:
668     return "NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel";
669   case NVPTXISD::TexUnifiedCubeArrayS32Float:
670     return "NVPTXISD::TexUnifiedCubeArrayS32Float";
671   case NVPTXISD::TexUnifiedCubeArrayS32FloatLevel:
672     return "NVPTXISD::TexUnifiedCubeArrayS32FloatLevel";
673   case NVPTXISD::TexUnifiedCubeArrayU32Float:
674     return "NVPTXISD::TexUnifiedCubeArrayU32Float";
675   case NVPTXISD::TexUnifiedCubeArrayU32FloatLevel:
676     return "NVPTXISD::TexUnifiedCubeArrayU32FloatLevel";
677   case NVPTXISD::Tld4UnifiedR2DFloatFloat:
678     return "NVPTXISD::Tld4UnifiedR2DFloatFloat";
679   case NVPTXISD::Tld4UnifiedG2DFloatFloat:
680     return "NVPTXISD::Tld4UnifiedG2DFloatFloat";
681   case NVPTXISD::Tld4UnifiedB2DFloatFloat:
682     return "NVPTXISD::Tld4UnifiedB2DFloatFloat";
683   case NVPTXISD::Tld4UnifiedA2DFloatFloat:
684     return "NVPTXISD::Tld4UnifiedA2DFloatFloat";
685   case NVPTXISD::Tld4UnifiedR2DS64Float:
686     return "NVPTXISD::Tld4UnifiedR2DS64Float";
687   case NVPTXISD::Tld4UnifiedG2DS64Float:
688     return "NVPTXISD::Tld4UnifiedG2DS64Float";
689   case NVPTXISD::Tld4UnifiedB2DS64Float:
690     return "NVPTXISD::Tld4UnifiedB2DS64Float";
691   case NVPTXISD::Tld4UnifiedA2DS64Float:
692     return "NVPTXISD::Tld4UnifiedA2DS64Float";
693   case NVPTXISD::Tld4UnifiedR2DU64Float:
694     return "NVPTXISD::Tld4UnifiedR2DU64Float";
695   case NVPTXISD::Tld4UnifiedG2DU64Float:
696     return "NVPTXISD::Tld4UnifiedG2DU64Float";
697   case NVPTXISD::Tld4UnifiedB2DU64Float:
698     return "NVPTXISD::Tld4UnifiedB2DU64Float";
699   case NVPTXISD::Tld4UnifiedA2DU64Float:
700     return "NVPTXISD::Tld4UnifiedA2DU64Float";
701 
702   case NVPTXISD::Suld1DI8Clamp:          return "NVPTXISD::Suld1DI8Clamp";
703   case NVPTXISD::Suld1DI16Clamp:         return "NVPTXISD::Suld1DI16Clamp";
704   case NVPTXISD::Suld1DI32Clamp:         return "NVPTXISD::Suld1DI32Clamp";
705   case NVPTXISD::Suld1DI64Clamp:         return "NVPTXISD::Suld1DI64Clamp";
706   case NVPTXISD::Suld1DV2I8Clamp:        return "NVPTXISD::Suld1DV2I8Clamp";
707   case NVPTXISD::Suld1DV2I16Clamp:       return "NVPTXISD::Suld1DV2I16Clamp";
708   case NVPTXISD::Suld1DV2I32Clamp:       return "NVPTXISD::Suld1DV2I32Clamp";
709   case NVPTXISD::Suld1DV2I64Clamp:       return "NVPTXISD::Suld1DV2I64Clamp";
710   case NVPTXISD::Suld1DV4I8Clamp:        return "NVPTXISD::Suld1DV4I8Clamp";
711   case NVPTXISD::Suld1DV4I16Clamp:       return "NVPTXISD::Suld1DV4I16Clamp";
712   case NVPTXISD::Suld1DV4I32Clamp:       return "NVPTXISD::Suld1DV4I32Clamp";
713 
714   case NVPTXISD::Suld1DArrayI8Clamp:   return "NVPTXISD::Suld1DArrayI8Clamp";
715   case NVPTXISD::Suld1DArrayI16Clamp:  return "NVPTXISD::Suld1DArrayI16Clamp";
716   case NVPTXISD::Suld1DArrayI32Clamp:  return "NVPTXISD::Suld1DArrayI32Clamp";
717   case NVPTXISD::Suld1DArrayI64Clamp:  return "NVPTXISD::Suld1DArrayI64Clamp";
718   case NVPTXISD::Suld1DArrayV2I8Clamp: return "NVPTXISD::Suld1DArrayV2I8Clamp";
719   case NVPTXISD::Suld1DArrayV2I16Clamp:return "NVPTXISD::Suld1DArrayV2I16Clamp";
720   case NVPTXISD::Suld1DArrayV2I32Clamp:return "NVPTXISD::Suld1DArrayV2I32Clamp";
721   case NVPTXISD::Suld1DArrayV2I64Clamp:return "NVPTXISD::Suld1DArrayV2I64Clamp";
722   case NVPTXISD::Suld1DArrayV4I8Clamp: return "NVPTXISD::Suld1DArrayV4I8Clamp";
723   case NVPTXISD::Suld1DArrayV4I16Clamp:return "NVPTXISD::Suld1DArrayV4I16Clamp";
724   case NVPTXISD::Suld1DArrayV4I32Clamp:return "NVPTXISD::Suld1DArrayV4I32Clamp";
725 
726   case NVPTXISD::Suld2DI8Clamp:          return "NVPTXISD::Suld2DI8Clamp";
727   case NVPTXISD::Suld2DI16Clamp:         return "NVPTXISD::Suld2DI16Clamp";
728   case NVPTXISD::Suld2DI32Clamp:         return "NVPTXISD::Suld2DI32Clamp";
729   case NVPTXISD::Suld2DI64Clamp:         return "NVPTXISD::Suld2DI64Clamp";
730   case NVPTXISD::Suld2DV2I8Clamp:        return "NVPTXISD::Suld2DV2I8Clamp";
731   case NVPTXISD::Suld2DV2I16Clamp:       return "NVPTXISD::Suld2DV2I16Clamp";
732   case NVPTXISD::Suld2DV2I32Clamp:       return "NVPTXISD::Suld2DV2I32Clamp";
733   case NVPTXISD::Suld2DV2I64Clamp:       return "NVPTXISD::Suld2DV2I64Clamp";
734   case NVPTXISD::Suld2DV4I8Clamp:        return "NVPTXISD::Suld2DV4I8Clamp";
735   case NVPTXISD::Suld2DV4I16Clamp:       return "NVPTXISD::Suld2DV4I16Clamp";
736   case NVPTXISD::Suld2DV4I32Clamp:       return "NVPTXISD::Suld2DV4I32Clamp";
737 
738   case NVPTXISD::Suld2DArrayI8Clamp:   return "NVPTXISD::Suld2DArrayI8Clamp";
739   case NVPTXISD::Suld2DArrayI16Clamp:  return "NVPTXISD::Suld2DArrayI16Clamp";
740   case NVPTXISD::Suld2DArrayI32Clamp:  return "NVPTXISD::Suld2DArrayI32Clamp";
741   case NVPTXISD::Suld2DArrayI64Clamp:  return "NVPTXISD::Suld2DArrayI64Clamp";
742   case NVPTXISD::Suld2DArrayV2I8Clamp: return "NVPTXISD::Suld2DArrayV2I8Clamp";
743   case NVPTXISD::Suld2DArrayV2I16Clamp:return "NVPTXISD::Suld2DArrayV2I16Clamp";
744   case NVPTXISD::Suld2DArrayV2I32Clamp:return "NVPTXISD::Suld2DArrayV2I32Clamp";
745   case NVPTXISD::Suld2DArrayV2I64Clamp:return "NVPTXISD::Suld2DArrayV2I64Clamp";
746   case NVPTXISD::Suld2DArrayV4I8Clamp: return "NVPTXISD::Suld2DArrayV4I8Clamp";
747   case NVPTXISD::Suld2DArrayV4I16Clamp:return "NVPTXISD::Suld2DArrayV4I16Clamp";
748   case NVPTXISD::Suld2DArrayV4I32Clamp:return "NVPTXISD::Suld2DArrayV4I32Clamp";
749 
750   case NVPTXISD::Suld3DI8Clamp:          return "NVPTXISD::Suld3DI8Clamp";
751   case NVPTXISD::Suld3DI16Clamp:         return "NVPTXISD::Suld3DI16Clamp";
752   case NVPTXISD::Suld3DI32Clamp:         return "NVPTXISD::Suld3DI32Clamp";
753   case NVPTXISD::Suld3DI64Clamp:         return "NVPTXISD::Suld3DI64Clamp";
754   case NVPTXISD::Suld3DV2I8Clamp:        return "NVPTXISD::Suld3DV2I8Clamp";
755   case NVPTXISD::Suld3DV2I16Clamp:       return "NVPTXISD::Suld3DV2I16Clamp";
756   case NVPTXISD::Suld3DV2I32Clamp:       return "NVPTXISD::Suld3DV2I32Clamp";
757   case NVPTXISD::Suld3DV2I64Clamp:       return "NVPTXISD::Suld3DV2I64Clamp";
758   case NVPTXISD::Suld3DV4I8Clamp:        return "NVPTXISD::Suld3DV4I8Clamp";
759   case NVPTXISD::Suld3DV4I16Clamp:       return "NVPTXISD::Suld3DV4I16Clamp";
760   case NVPTXISD::Suld3DV4I32Clamp:       return "NVPTXISD::Suld3DV4I32Clamp";
761 
762   case NVPTXISD::Suld1DI8Trap:          return "NVPTXISD::Suld1DI8Trap";
763   case NVPTXISD::Suld1DI16Trap:         return "NVPTXISD::Suld1DI16Trap";
764   case NVPTXISD::Suld1DI32Trap:         return "NVPTXISD::Suld1DI32Trap";
765   case NVPTXISD::Suld1DI64Trap:         return "NVPTXISD::Suld1DI64Trap";
766   case NVPTXISD::Suld1DV2I8Trap:        return "NVPTXISD::Suld1DV2I8Trap";
767   case NVPTXISD::Suld1DV2I16Trap:       return "NVPTXISD::Suld1DV2I16Trap";
768   case NVPTXISD::Suld1DV2I32Trap:       return "NVPTXISD::Suld1DV2I32Trap";
769   case NVPTXISD::Suld1DV2I64Trap:       return "NVPTXISD::Suld1DV2I64Trap";
770   case NVPTXISD::Suld1DV4I8Trap:        return "NVPTXISD::Suld1DV4I8Trap";
771   case NVPTXISD::Suld1DV4I16Trap:       return "NVPTXISD::Suld1DV4I16Trap";
772   case NVPTXISD::Suld1DV4I32Trap:       return "NVPTXISD::Suld1DV4I32Trap";
773 
774   case NVPTXISD::Suld1DArrayI8Trap:     return "NVPTXISD::Suld1DArrayI8Trap";
775   case NVPTXISD::Suld1DArrayI16Trap:    return "NVPTXISD::Suld1DArrayI16Trap";
776   case NVPTXISD::Suld1DArrayI32Trap:    return "NVPTXISD::Suld1DArrayI32Trap";
777   case NVPTXISD::Suld1DArrayI64Trap:    return "NVPTXISD::Suld1DArrayI64Trap";
778   case NVPTXISD::Suld1DArrayV2I8Trap:   return "NVPTXISD::Suld1DArrayV2I8Trap";
779   case NVPTXISD::Suld1DArrayV2I16Trap:  return "NVPTXISD::Suld1DArrayV2I16Trap";
780   case NVPTXISD::Suld1DArrayV2I32Trap:  return "NVPTXISD::Suld1DArrayV2I32Trap";
781   case NVPTXISD::Suld1DArrayV2I64Trap:  return "NVPTXISD::Suld1DArrayV2I64Trap";
782   case NVPTXISD::Suld1DArrayV4I8Trap:   return "NVPTXISD::Suld1DArrayV4I8Trap";
783   case NVPTXISD::Suld1DArrayV4I16Trap:  return "NVPTXISD::Suld1DArrayV4I16Trap";
784   case NVPTXISD::Suld1DArrayV4I32Trap:  return "NVPTXISD::Suld1DArrayV4I32Trap";
785 
786   case NVPTXISD::Suld2DI8Trap:          return "NVPTXISD::Suld2DI8Trap";
787   case NVPTXISD::Suld2DI16Trap:         return "NVPTXISD::Suld2DI16Trap";
788   case NVPTXISD::Suld2DI32Trap:         return "NVPTXISD::Suld2DI32Trap";
789   case NVPTXISD::Suld2DI64Trap:         return "NVPTXISD::Suld2DI64Trap";
790   case NVPTXISD::Suld2DV2I8Trap:        return "NVPTXISD::Suld2DV2I8Trap";
791   case NVPTXISD::Suld2DV2I16Trap:       return "NVPTXISD::Suld2DV2I16Trap";
792   case NVPTXISD::Suld2DV2I32Trap:       return "NVPTXISD::Suld2DV2I32Trap";
793   case NVPTXISD::Suld2DV2I64Trap:       return "NVPTXISD::Suld2DV2I64Trap";
794   case NVPTXISD::Suld2DV4I8Trap:        return "NVPTXISD::Suld2DV4I8Trap";
795   case NVPTXISD::Suld2DV4I16Trap:       return "NVPTXISD::Suld2DV4I16Trap";
796   case NVPTXISD::Suld2DV4I32Trap:       return "NVPTXISD::Suld2DV4I32Trap";
797 
798   case NVPTXISD::Suld2DArrayI8Trap:     return "NVPTXISD::Suld2DArrayI8Trap";
799   case NVPTXISD::Suld2DArrayI16Trap:    return "NVPTXISD::Suld2DArrayI16Trap";
800   case NVPTXISD::Suld2DArrayI32Trap:    return "NVPTXISD::Suld2DArrayI32Trap";
801   case NVPTXISD::Suld2DArrayI64Trap:    return "NVPTXISD::Suld2DArrayI64Trap";
802   case NVPTXISD::Suld2DArrayV2I8Trap:   return "NVPTXISD::Suld2DArrayV2I8Trap";
803   case NVPTXISD::Suld2DArrayV2I16Trap:  return "NVPTXISD::Suld2DArrayV2I16Trap";
804   case NVPTXISD::Suld2DArrayV2I32Trap:  return "NVPTXISD::Suld2DArrayV2I32Trap";
805   case NVPTXISD::Suld2DArrayV2I64Trap:  return "NVPTXISD::Suld2DArrayV2I64Trap";
806   case NVPTXISD::Suld2DArrayV4I8Trap:   return "NVPTXISD::Suld2DArrayV4I8Trap";
807   case NVPTXISD::Suld2DArrayV4I16Trap:  return "NVPTXISD::Suld2DArrayV4I16Trap";
808   case NVPTXISD::Suld2DArrayV4I32Trap:  return "NVPTXISD::Suld2DArrayV4I32Trap";
809 
810   case NVPTXISD::Suld3DI8Trap:          return "NVPTXISD::Suld3DI8Trap";
811   case NVPTXISD::Suld3DI16Trap:         return "NVPTXISD::Suld3DI16Trap";
812   case NVPTXISD::Suld3DI32Trap:         return "NVPTXISD::Suld3DI32Trap";
813   case NVPTXISD::Suld3DI64Trap:         return "NVPTXISD::Suld3DI64Trap";
814   case NVPTXISD::Suld3DV2I8Trap:        return "NVPTXISD::Suld3DV2I8Trap";
815   case NVPTXISD::Suld3DV2I16Trap:       return "NVPTXISD::Suld3DV2I16Trap";
816   case NVPTXISD::Suld3DV2I32Trap:       return "NVPTXISD::Suld3DV2I32Trap";
817   case NVPTXISD::Suld3DV2I64Trap:       return "NVPTXISD::Suld3DV2I64Trap";
818   case NVPTXISD::Suld3DV4I8Trap:        return "NVPTXISD::Suld3DV4I8Trap";
819   case NVPTXISD::Suld3DV4I16Trap:       return "NVPTXISD::Suld3DV4I16Trap";
820   case NVPTXISD::Suld3DV4I32Trap:       return "NVPTXISD::Suld3DV4I32Trap";
821 
822   case NVPTXISD::Suld1DI8Zero:          return "NVPTXISD::Suld1DI8Zero";
823   case NVPTXISD::Suld1DI16Zero:         return "NVPTXISD::Suld1DI16Zero";
824   case NVPTXISD::Suld1DI32Zero:         return "NVPTXISD::Suld1DI32Zero";
825   case NVPTXISD::Suld1DI64Zero:         return "NVPTXISD::Suld1DI64Zero";
826   case NVPTXISD::Suld1DV2I8Zero:        return "NVPTXISD::Suld1DV2I8Zero";
827   case NVPTXISD::Suld1DV2I16Zero:       return "NVPTXISD::Suld1DV2I16Zero";
828   case NVPTXISD::Suld1DV2I32Zero:       return "NVPTXISD::Suld1DV2I32Zero";
829   case NVPTXISD::Suld1DV2I64Zero:       return "NVPTXISD::Suld1DV2I64Zero";
830   case NVPTXISD::Suld1DV4I8Zero:        return "NVPTXISD::Suld1DV4I8Zero";
831   case NVPTXISD::Suld1DV4I16Zero:       return "NVPTXISD::Suld1DV4I16Zero";
832   case NVPTXISD::Suld1DV4I32Zero:       return "NVPTXISD::Suld1DV4I32Zero";
833 
834   case NVPTXISD::Suld1DArrayI8Zero:     return "NVPTXISD::Suld1DArrayI8Zero";
835   case NVPTXISD::Suld1DArrayI16Zero:    return "NVPTXISD::Suld1DArrayI16Zero";
836   case NVPTXISD::Suld1DArrayI32Zero:    return "NVPTXISD::Suld1DArrayI32Zero";
837   case NVPTXISD::Suld1DArrayI64Zero:    return "NVPTXISD::Suld1DArrayI64Zero";
838   case NVPTXISD::Suld1DArrayV2I8Zero:   return "NVPTXISD::Suld1DArrayV2I8Zero";
839   case NVPTXISD::Suld1DArrayV2I16Zero:  return "NVPTXISD::Suld1DArrayV2I16Zero";
840   case NVPTXISD::Suld1DArrayV2I32Zero:  return "NVPTXISD::Suld1DArrayV2I32Zero";
841   case NVPTXISD::Suld1DArrayV2I64Zero:  return "NVPTXISD::Suld1DArrayV2I64Zero";
842   case NVPTXISD::Suld1DArrayV4I8Zero:   return "NVPTXISD::Suld1DArrayV4I8Zero";
843   case NVPTXISD::Suld1DArrayV4I16Zero:  return "NVPTXISD::Suld1DArrayV4I16Zero";
844   case NVPTXISD::Suld1DArrayV4I32Zero:  return "NVPTXISD::Suld1DArrayV4I32Zero";
845 
846   case NVPTXISD::Suld2DI8Zero:          return "NVPTXISD::Suld2DI8Zero";
847   case NVPTXISD::Suld2DI16Zero:         return "NVPTXISD::Suld2DI16Zero";
848   case NVPTXISD::Suld2DI32Zero:         return "NVPTXISD::Suld2DI32Zero";
849   case NVPTXISD::Suld2DI64Zero:         return "NVPTXISD::Suld2DI64Zero";
850   case NVPTXISD::Suld2DV2I8Zero:        return "NVPTXISD::Suld2DV2I8Zero";
851   case NVPTXISD::Suld2DV2I16Zero:       return "NVPTXISD::Suld2DV2I16Zero";
852   case NVPTXISD::Suld2DV2I32Zero:       return "NVPTXISD::Suld2DV2I32Zero";
853   case NVPTXISD::Suld2DV2I64Zero:       return "NVPTXISD::Suld2DV2I64Zero";
854   case NVPTXISD::Suld2DV4I8Zero:        return "NVPTXISD::Suld2DV4I8Zero";
855   case NVPTXISD::Suld2DV4I16Zero:       return "NVPTXISD::Suld2DV4I16Zero";
856   case NVPTXISD::Suld2DV4I32Zero:       return "NVPTXISD::Suld2DV4I32Zero";
857 
858   case NVPTXISD::Suld2DArrayI8Zero:     return "NVPTXISD::Suld2DArrayI8Zero";
859   case NVPTXISD::Suld2DArrayI16Zero:    return "NVPTXISD::Suld2DArrayI16Zero";
860   case NVPTXISD::Suld2DArrayI32Zero:    return "NVPTXISD::Suld2DArrayI32Zero";
861   case NVPTXISD::Suld2DArrayI64Zero:    return "NVPTXISD::Suld2DArrayI64Zero";
862   case NVPTXISD::Suld2DArrayV2I8Zero:   return "NVPTXISD::Suld2DArrayV2I8Zero";
863   case NVPTXISD::Suld2DArrayV2I16Zero:  return "NVPTXISD::Suld2DArrayV2I16Zero";
864   case NVPTXISD::Suld2DArrayV2I32Zero:  return "NVPTXISD::Suld2DArrayV2I32Zero";
865   case NVPTXISD::Suld2DArrayV2I64Zero:  return "NVPTXISD::Suld2DArrayV2I64Zero";
866   case NVPTXISD::Suld2DArrayV4I8Zero:   return "NVPTXISD::Suld2DArrayV4I8Zero";
867   case NVPTXISD::Suld2DArrayV4I16Zero:  return "NVPTXISD::Suld2DArrayV4I16Zero";
868   case NVPTXISD::Suld2DArrayV4I32Zero:  return "NVPTXISD::Suld2DArrayV4I32Zero";
869 
870   case NVPTXISD::Suld3DI8Zero:          return "NVPTXISD::Suld3DI8Zero";
871   case NVPTXISD::Suld3DI16Zero:         return "NVPTXISD::Suld3DI16Zero";
872   case NVPTXISD::Suld3DI32Zero:         return "NVPTXISD::Suld3DI32Zero";
873   case NVPTXISD::Suld3DI64Zero:         return "NVPTXISD::Suld3DI64Zero";
874   case NVPTXISD::Suld3DV2I8Zero:        return "NVPTXISD::Suld3DV2I8Zero";
875   case NVPTXISD::Suld3DV2I16Zero:       return "NVPTXISD::Suld3DV2I16Zero";
876   case NVPTXISD::Suld3DV2I32Zero:       return "NVPTXISD::Suld3DV2I32Zero";
877   case NVPTXISD::Suld3DV2I64Zero:       return "NVPTXISD::Suld3DV2I64Zero";
878   case NVPTXISD::Suld3DV4I8Zero:        return "NVPTXISD::Suld3DV4I8Zero";
879   case NVPTXISD::Suld3DV4I16Zero:       return "NVPTXISD::Suld3DV4I16Zero";
880   case NVPTXISD::Suld3DV4I32Zero:       return "NVPTXISD::Suld3DV4I32Zero";
881   }
882   return nullptr;
883 }
884 
885 TargetLoweringBase::LegalizeTypeAction
886 NVPTXTargetLowering::getPreferredVectorAction(EVT VT) const {
887   if (VT.getVectorNumElements() != 1 && VT.getScalarType() == MVT::i1)
888     return TypeSplitVector;
889 
890   return TargetLoweringBase::getPreferredVectorAction(VT);
891 }
892 
893 SDValue
894 NVPTXTargetLowering::LowerGlobalAddress(SDValue Op, SelectionDAG &DAG) const {
895   SDLoc dl(Op);
896   const GlobalValue *GV = cast<GlobalAddressSDNode>(Op)->getGlobal();
897   auto PtrVT = getPointerTy(DAG.getDataLayout());
898   Op = DAG.getTargetGlobalAddress(GV, dl, PtrVT);
899   return DAG.getNode(NVPTXISD::Wrapper, dl, PtrVT, Op);
900 }
901 
902 std::string NVPTXTargetLowering::getPrototype(
903     const DataLayout &DL, Type *retTy, const ArgListTy &Args,
904     const SmallVectorImpl<ISD::OutputArg> &Outs, unsigned retAlignment,
905     const ImmutableCallSite *CS) const {
906   auto PtrVT = getPointerTy(DL);
907 
908   bool isABI = (STI.getSmVersion() >= 20);
909   assert(isABI && "Non-ABI compilation is not supported");
910   if (!isABI)
911     return "";
912 
913   std::stringstream O;
914   O << "prototype_" << uniqueCallSite << " : .callprototype ";
915 
916   if (retTy->getTypeID() == Type::VoidTyID) {
917     O << "()";
918   } else {
919     O << "(";
920     if (retTy->isFloatingPointTy() || retTy->isIntegerTy()) {
921       unsigned size = 0;
922       if (auto *ITy = dyn_cast<IntegerType>(retTy)) {
923         size = ITy->getBitWidth();
924         if (size < 32)
925           size = 32;
926       } else {
927         assert(retTy->isFloatingPointTy() &&
928                "Floating point type expected here");
929         size = retTy->getPrimitiveSizeInBits();
930       }
931 
932       O << ".param .b" << size << " _";
933     } else if (isa<PointerType>(retTy)) {
934       O << ".param .b" << PtrVT.getSizeInBits() << " _";
935     } else if ((retTy->getTypeID() == Type::StructTyID) ||
936                isa<VectorType>(retTy)) {
937       auto &DL = CS->getCalledFunction()->getParent()->getDataLayout();
938       O << ".param .align " << retAlignment << " .b8 _["
939         << DL.getTypeAllocSize(retTy) << "]";
940     } else {
941       llvm_unreachable("Unknown return type");
942     }
943     O << ") ";
944   }
945   O << "_ (";
946 
947   bool first = true;
948 
949   unsigned OIdx = 0;
950   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
951     Type *Ty = Args[i].Ty;
952     if (!first) {
953       O << ", ";
954     }
955     first = false;
956 
957     if (!Outs[OIdx].Flags.isByVal()) {
958       if (Ty->isAggregateType() || Ty->isVectorTy()) {
959         unsigned align = 0;
960         const CallInst *CallI = cast<CallInst>(CS->getInstruction());
961         // +1 because index 0 is reserved for return type alignment
962         if (!llvm::getAlign(*CallI, i + 1, align))
963           align = DL.getABITypeAlignment(Ty);
964         unsigned sz = DL.getTypeAllocSize(Ty);
965         O << ".param .align " << align << " .b8 ";
966         O << "_";
967         O << "[" << sz << "]";
968         // update the index for Outs
969         SmallVector<EVT, 16> vtparts;
970         ComputeValueVTs(*this, DL, Ty, vtparts);
971         if (unsigned len = vtparts.size())
972           OIdx += len - 1;
973         continue;
974       }
975        // i8 types in IR will be i16 types in SDAG
976       assert((getValueType(DL, Ty) == Outs[OIdx].VT ||
977               (getValueType(DL, Ty) == MVT::i8 && Outs[OIdx].VT == MVT::i16)) &&
978              "type mismatch between callee prototype and arguments");
979       // scalar type
980       unsigned sz = 0;
981       if (isa<IntegerType>(Ty)) {
982         sz = cast<IntegerType>(Ty)->getBitWidth();
983         if (sz < 32)
984           sz = 32;
985       } else if (isa<PointerType>(Ty))
986         sz = PtrVT.getSizeInBits();
987       else
988         sz = Ty->getPrimitiveSizeInBits();
989       O << ".param .b" << sz << " ";
990       O << "_";
991       continue;
992     }
993     auto *PTy = dyn_cast<PointerType>(Ty);
994     assert(PTy && "Param with byval attribute should be a pointer type");
995     Type *ETy = PTy->getElementType();
996 
997     unsigned align = Outs[OIdx].Flags.getByValAlign();
998     unsigned sz = DL.getTypeAllocSize(ETy);
999     O << ".param .align " << align << " .b8 ";
1000     O << "_";
1001     O << "[" << sz << "]";
1002   }
1003   O << ");";
1004   return O.str();
1005 }
1006 
1007 unsigned
1008 NVPTXTargetLowering::getArgumentAlignment(SDValue Callee,
1009                                           const ImmutableCallSite *CS,
1010                                           Type *Ty,
1011                                           unsigned Idx) const {
1012   unsigned Align = 0;
1013   const Value *DirectCallee = CS->getCalledFunction();
1014 
1015   if (!DirectCallee) {
1016     // We don't have a direct function symbol, but that may be because of
1017     // constant cast instructions in the call.
1018     const Instruction *CalleeI = CS->getInstruction();
1019     assert(CalleeI && "Call target is not a function or derived value?");
1020 
1021     // With bitcast'd call targets, the instruction will be the call
1022     if (isa<CallInst>(CalleeI)) {
1023       // Check if we have call alignment metadata
1024       if (llvm::getAlign(*cast<CallInst>(CalleeI), Idx, Align))
1025         return Align;
1026 
1027       const Value *CalleeV = cast<CallInst>(CalleeI)->getCalledValue();
1028       // Ignore any bitcast instructions
1029       while(isa<ConstantExpr>(CalleeV)) {
1030         const ConstantExpr *CE = cast<ConstantExpr>(CalleeV);
1031         if (!CE->isCast())
1032           break;
1033         // Look through the bitcast
1034         CalleeV = cast<ConstantExpr>(CalleeV)->getOperand(0);
1035       }
1036 
1037       // We have now looked past all of the bitcasts.  Do we finally have a
1038       // Function?
1039       if (isa<Function>(CalleeV))
1040         DirectCallee = CalleeV;
1041     }
1042   }
1043 
1044   // Check for function alignment information if we found that the
1045   // ultimate target is a Function
1046   if (DirectCallee)
1047     if (llvm::getAlign(*cast<Function>(DirectCallee), Idx, Align))
1048       return Align;
1049 
1050   // Call is indirect or alignment information is not available, fall back to
1051   // the ABI type alignment
1052   auto &DL = CS->getCaller()->getParent()->getDataLayout();
1053   return DL.getABITypeAlignment(Ty);
1054 }
1055 
1056 SDValue NVPTXTargetLowering::LowerCall(TargetLowering::CallLoweringInfo &CLI,
1057                                        SmallVectorImpl<SDValue> &InVals) const {
1058   SelectionDAG &DAG = CLI.DAG;
1059   SDLoc dl = CLI.DL;
1060   SmallVectorImpl<ISD::OutputArg> &Outs = CLI.Outs;
1061   SmallVectorImpl<SDValue> &OutVals = CLI.OutVals;
1062   SmallVectorImpl<ISD::InputArg> &Ins = CLI.Ins;
1063   SDValue Chain = CLI.Chain;
1064   SDValue Callee = CLI.Callee;
1065   bool &isTailCall = CLI.IsTailCall;
1066   ArgListTy &Args = CLI.getArgs();
1067   Type *retTy = CLI.RetTy;
1068   ImmutableCallSite *CS = CLI.CS;
1069 
1070   bool isABI = (STI.getSmVersion() >= 20);
1071   assert(isABI && "Non-ABI compilation is not supported");
1072   if (!isABI)
1073     return Chain;
1074   MachineFunction &MF = DAG.getMachineFunction();
1075   const Function *F = MF.getFunction();
1076   auto &DL = MF.getDataLayout();
1077 
1078   SDValue tempChain = Chain;
1079   Chain = DAG.getCALLSEQ_START(Chain,
1080                                DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1081                                dl);
1082   SDValue InFlag = Chain.getValue(1);
1083 
1084   unsigned paramCount = 0;
1085   // Args.size() and Outs.size() need not match.
1086   // Outs.size() will be larger
1087   //   * if there is an aggregate argument with multiple fields (each field
1088   //     showing up separately in Outs)
1089   //   * if there is a vector argument with more than typical vector-length
1090   //     elements (generally if more than 4) where each vector element is
1091   //     individually present in Outs.
1092   // So a different index should be used for indexing into Outs/OutVals.
1093   // See similar issue in LowerFormalArguments.
1094   unsigned OIdx = 0;
1095   // Declare the .params or .reg need to pass values
1096   // to the function
1097   for (unsigned i = 0, e = Args.size(); i != e; ++i, ++OIdx) {
1098     EVT VT = Outs[OIdx].VT;
1099     Type *Ty = Args[i].Ty;
1100 
1101     if (!Outs[OIdx].Flags.isByVal()) {
1102       if (Ty->isAggregateType()) {
1103         // aggregate
1104         SmallVector<EVT, 16> vtparts;
1105         SmallVector<uint64_t, 16> Offsets;
1106         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &Offsets,
1107                            0);
1108 
1109         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1110         // declare .param .align <align> .b8 .param<n>[<size>];
1111         unsigned sz = DL.getTypeAllocSize(Ty);
1112         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1113         SDValue DeclareParamOps[] = { Chain, DAG.getConstant(align, dl,
1114                                                              MVT::i32),
1115                                       DAG.getConstant(paramCount, dl, MVT::i32),
1116                                       DAG.getConstant(sz, dl, MVT::i32),
1117                                       InFlag };
1118         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1119                             DeclareParamOps);
1120         InFlag = Chain.getValue(1);
1121         for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1122           EVT elemtype = vtparts[j];
1123           unsigned ArgAlign = GreatestCommonDivisor64(align, Offsets[j]);
1124           if (elemtype.isInteger() && (sz < 8))
1125             sz = 8;
1126           SDValue StVal = OutVals[OIdx];
1127           if (elemtype.getSizeInBits() < 16) {
1128             StVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, StVal);
1129           }
1130           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1131           SDValue CopyParamOps[] = { Chain,
1132                                      DAG.getConstant(paramCount, dl, MVT::i32),
1133                                      DAG.getConstant(Offsets[j], dl, MVT::i32),
1134                                      StVal, InFlag };
1135           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1136                                           CopyParamVTs, CopyParamOps,
1137                                           elemtype, MachinePointerInfo(),
1138                                           ArgAlign);
1139           InFlag = Chain.getValue(1);
1140           ++OIdx;
1141         }
1142         if (vtparts.size() > 0)
1143           --OIdx;
1144         ++paramCount;
1145         continue;
1146       }
1147       if (Ty->isVectorTy()) {
1148         EVT ObjectVT = getValueType(DL, Ty);
1149         unsigned align = getArgumentAlignment(Callee, CS, Ty, paramCount + 1);
1150         // declare .param .align <align> .b8 .param<n>[<size>];
1151         unsigned sz = DL.getTypeAllocSize(Ty);
1152         SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1153         SDValue DeclareParamOps[] = { Chain,
1154                                       DAG.getConstant(align, dl, MVT::i32),
1155                                       DAG.getConstant(paramCount, dl, MVT::i32),
1156                                       DAG.getConstant(sz, dl, MVT::i32),
1157                                       InFlag };
1158         Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1159                             DeclareParamOps);
1160         InFlag = Chain.getValue(1);
1161         unsigned NumElts = ObjectVT.getVectorNumElements();
1162         EVT EltVT = ObjectVT.getVectorElementType();
1163         EVT MemVT = EltVT;
1164         bool NeedExtend = false;
1165         if (EltVT.getSizeInBits() < 16) {
1166           NeedExtend = true;
1167           EltVT = MVT::i16;
1168         }
1169 
1170         // V1 store
1171         if (NumElts == 1) {
1172           SDValue Elt = OutVals[OIdx++];
1173           if (NeedExtend)
1174             Elt = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt);
1175 
1176           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1177           SDValue CopyParamOps[] = { Chain,
1178                                      DAG.getConstant(paramCount, dl, MVT::i32),
1179                                      DAG.getConstant(0, dl, MVT::i32), Elt,
1180                                      InFlag };
1181           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl,
1182                                           CopyParamVTs, CopyParamOps,
1183                                           MemVT, MachinePointerInfo());
1184           InFlag = Chain.getValue(1);
1185         } else if (NumElts == 2) {
1186           SDValue Elt0 = OutVals[OIdx++];
1187           SDValue Elt1 = OutVals[OIdx++];
1188           if (NeedExtend) {
1189             Elt0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt0);
1190             Elt1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Elt1);
1191           }
1192 
1193           SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1194           SDValue CopyParamOps[] = { Chain,
1195                                      DAG.getConstant(paramCount, dl, MVT::i32),
1196                                      DAG.getConstant(0, dl, MVT::i32), Elt0,
1197                                      Elt1, InFlag };
1198           Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParamV2, dl,
1199                                           CopyParamVTs, CopyParamOps,
1200                                           MemVT, MachinePointerInfo());
1201           InFlag = Chain.getValue(1);
1202         } else {
1203           unsigned curOffset = 0;
1204           // V4 stores
1205           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
1206           // the
1207           // vector will be expanded to a power of 2 elements, so we know we can
1208           // always round up to the next multiple of 4 when creating the vector
1209           // stores.
1210           // e.g.  4 elem => 1 st.v4
1211           //       6 elem => 2 st.v4
1212           //       8 elem => 2 st.v4
1213           //      11 elem => 3 st.v4
1214           unsigned VecSize = 4;
1215           if (EltVT.getSizeInBits() == 64)
1216             VecSize = 2;
1217 
1218           // This is potentially only part of a vector, so assume all elements
1219           // are packed together.
1220           unsigned PerStoreOffset = MemVT.getStoreSizeInBits() / 8 * VecSize;
1221 
1222           for (unsigned i = 0; i < NumElts; i += VecSize) {
1223             // Get values
1224             SDValue StoreVal;
1225             SmallVector<SDValue, 8> Ops;
1226             Ops.push_back(Chain);
1227             Ops.push_back(DAG.getConstant(paramCount, dl, MVT::i32));
1228             Ops.push_back(DAG.getConstant(curOffset, dl, MVT::i32));
1229 
1230             unsigned Opc = NVPTXISD::StoreParamV2;
1231 
1232             StoreVal = OutVals[OIdx++];
1233             if (NeedExtend)
1234               StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1235             Ops.push_back(StoreVal);
1236 
1237             if (i + 1 < NumElts) {
1238               StoreVal = OutVals[OIdx++];
1239               if (NeedExtend)
1240                 StoreVal =
1241                     DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1242             } else {
1243               StoreVal = DAG.getUNDEF(EltVT);
1244             }
1245             Ops.push_back(StoreVal);
1246 
1247             if (VecSize == 4) {
1248               Opc = NVPTXISD::StoreParamV4;
1249               if (i + 2 < NumElts) {
1250                 StoreVal = OutVals[OIdx++];
1251                 if (NeedExtend)
1252                   StoreVal =
1253                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1254               } else {
1255                 StoreVal = DAG.getUNDEF(EltVT);
1256               }
1257               Ops.push_back(StoreVal);
1258 
1259               if (i + 3 < NumElts) {
1260                 StoreVal = OutVals[OIdx++];
1261                 if (NeedExtend)
1262                   StoreVal =
1263                       DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
1264               } else {
1265                 StoreVal = DAG.getUNDEF(EltVT);
1266               }
1267               Ops.push_back(StoreVal);
1268             }
1269 
1270             Ops.push_back(InFlag);
1271 
1272             SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1273             Chain = DAG.getMemIntrinsicNode(Opc, dl, CopyParamVTs, Ops,
1274                                             MemVT, MachinePointerInfo());
1275             InFlag = Chain.getValue(1);
1276             curOffset += PerStoreOffset;
1277           }
1278         }
1279         ++paramCount;
1280         --OIdx;
1281         continue;
1282       }
1283       // Plain scalar
1284       // for ABI,    declare .param .b<size> .param<n>;
1285       unsigned sz = VT.getSizeInBits();
1286       bool needExtend = false;
1287       if (VT.isInteger()) {
1288         if (sz < 16)
1289           needExtend = true;
1290         if (sz < 32)
1291           sz = 32;
1292       }
1293       SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1294       SDValue DeclareParamOps[] = { Chain,
1295                                     DAG.getConstant(paramCount, dl, MVT::i32),
1296                                     DAG.getConstant(sz, dl, MVT::i32),
1297                                     DAG.getConstant(0, dl, MVT::i32), InFlag };
1298       Chain = DAG.getNode(NVPTXISD::DeclareScalarParam, dl, DeclareParamVTs,
1299                           DeclareParamOps);
1300       InFlag = Chain.getValue(1);
1301       SDValue OutV = OutVals[OIdx];
1302       if (needExtend) {
1303         // zext/sext i1 to i16
1304         unsigned opc = ISD::ZERO_EXTEND;
1305         if (Outs[OIdx].Flags.isSExt())
1306           opc = ISD::SIGN_EXTEND;
1307         OutV = DAG.getNode(opc, dl, MVT::i16, OutV);
1308       }
1309       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1310       SDValue CopyParamOps[] = { Chain,
1311                                  DAG.getConstant(paramCount, dl, MVT::i32),
1312                                  DAG.getConstant(0, dl, MVT::i32), OutV,
1313                                  InFlag };
1314 
1315       unsigned opcode = NVPTXISD::StoreParam;
1316       if (Outs[OIdx].Flags.isZExt())
1317         opcode = NVPTXISD::StoreParamU32;
1318       else if (Outs[OIdx].Flags.isSExt())
1319         opcode = NVPTXISD::StoreParamS32;
1320       Chain = DAG.getMemIntrinsicNode(opcode, dl, CopyParamVTs, CopyParamOps,
1321                                       VT, MachinePointerInfo());
1322 
1323       InFlag = Chain.getValue(1);
1324       ++paramCount;
1325       continue;
1326     }
1327     // struct or vector
1328     SmallVector<EVT, 16> vtparts;
1329     SmallVector<uint64_t, 16> Offsets;
1330     auto *PTy = dyn_cast<PointerType>(Args[i].Ty);
1331     assert(PTy && "Type of a byval parameter should be pointer");
1332     ComputePTXValueVTs(*this, DAG.getDataLayout(), PTy->getElementType(),
1333                        vtparts, &Offsets, 0);
1334 
1335     // declare .param .align <align> .b8 .param<n>[<size>];
1336     unsigned sz = Outs[OIdx].Flags.getByValSize();
1337     SDVTList DeclareParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1338     unsigned ArgAlign = Outs[OIdx].Flags.getByValAlign();
1339     // The ByValAlign in the Outs[OIdx].Flags is alway set at this point,
1340     // so we don't need to worry about natural alignment or not.
1341     // See TargetLowering::LowerCallTo().
1342     SDValue DeclareParamOps[] = {
1343       Chain, DAG.getConstant(Outs[OIdx].Flags.getByValAlign(), dl, MVT::i32),
1344       DAG.getConstant(paramCount, dl, MVT::i32),
1345       DAG.getConstant(sz, dl, MVT::i32), InFlag
1346     };
1347     Chain = DAG.getNode(NVPTXISD::DeclareParam, dl, DeclareParamVTs,
1348                         DeclareParamOps);
1349     InFlag = Chain.getValue(1);
1350     for (unsigned j = 0, je = vtparts.size(); j != je; ++j) {
1351       EVT elemtype = vtparts[j];
1352       int curOffset = Offsets[j];
1353       unsigned PartAlign = GreatestCommonDivisor64(ArgAlign, curOffset);
1354       auto PtrVT = getPointerTy(DAG.getDataLayout());
1355       SDValue srcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, OutVals[OIdx],
1356                                     DAG.getConstant(curOffset, dl, PtrVT));
1357       SDValue theVal = DAG.getLoad(elemtype, dl, tempChain, srcAddr,
1358                                    MachinePointerInfo(), false, false, false,
1359                                    PartAlign);
1360       if (elemtype.getSizeInBits() < 16) {
1361         theVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, theVal);
1362       }
1363       SDVTList CopyParamVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1364       SDValue CopyParamOps[] = { Chain,
1365                                  DAG.getConstant(paramCount, dl, MVT::i32),
1366                                  DAG.getConstant(curOffset, dl, MVT::i32),
1367                                  theVal, InFlag };
1368       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreParam, dl, CopyParamVTs,
1369                                       CopyParamOps, elemtype,
1370                                       MachinePointerInfo());
1371 
1372       InFlag = Chain.getValue(1);
1373     }
1374     ++paramCount;
1375   }
1376 
1377   GlobalAddressSDNode *Func = dyn_cast<GlobalAddressSDNode>(Callee.getNode());
1378   unsigned retAlignment = 0;
1379 
1380   // Handle Result
1381   if (Ins.size() > 0) {
1382     SmallVector<EVT, 16> resvtparts;
1383     ComputeValueVTs(*this, DL, retTy, resvtparts);
1384 
1385     // Declare
1386     //  .param .align 16 .b8 retval0[<size-in-bytes>], or
1387     //  .param .b<size-in-bits> retval0
1388     unsigned resultsz = DL.getTypeAllocSizeInBits(retTy);
1389     // Emit ".param .b<size-in-bits> retval0" instead of byte arrays only for
1390     // these three types to match the logic in
1391     // NVPTXAsmPrinter::printReturnValStr and NVPTXTargetLowering::getPrototype.
1392     // Plus, this behavior is consistent with nvcc's.
1393     if (retTy->isFloatingPointTy() || retTy->isIntegerTy() ||
1394         retTy->isPointerTy()) {
1395       // Scalar needs to be at least 32bit wide
1396       if (resultsz < 32)
1397         resultsz = 32;
1398       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1399       SDValue DeclareRetOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1400                                   DAG.getConstant(resultsz, dl, MVT::i32),
1401                                   DAG.getConstant(0, dl, MVT::i32), InFlag };
1402       Chain = DAG.getNode(NVPTXISD::DeclareRet, dl, DeclareRetVTs,
1403                           DeclareRetOps);
1404       InFlag = Chain.getValue(1);
1405     } else {
1406       retAlignment = getArgumentAlignment(Callee, CS, retTy, 0);
1407       SDVTList DeclareRetVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1408       SDValue DeclareRetOps[] = { Chain,
1409                                   DAG.getConstant(retAlignment, dl, MVT::i32),
1410                                   DAG.getConstant(resultsz / 8, dl, MVT::i32),
1411                                   DAG.getConstant(0, dl, MVT::i32), InFlag };
1412       Chain = DAG.getNode(NVPTXISD::DeclareRetParam, dl, DeclareRetVTs,
1413                           DeclareRetOps);
1414       InFlag = Chain.getValue(1);
1415     }
1416   }
1417 
1418   if (!Func) {
1419     // This is indirect function call case : PTX requires a prototype of the
1420     // form
1421     // proto_0 : .callprototype(.param .b32 _) _ (.param .b32 _);
1422     // to be emitted, and the label has to used as the last arg of call
1423     // instruction.
1424     // The prototype is embedded in a string and put as the operand for a
1425     // CallPrototype SDNode which will print out to the value of the string.
1426     SDVTList ProtoVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1427     std::string Proto =
1428         getPrototype(DAG.getDataLayout(), retTy, Args, Outs, retAlignment, CS);
1429     const char *ProtoStr =
1430       nvTM->getManagedStrPool()->getManagedString(Proto.c_str())->c_str();
1431     SDValue ProtoOps[] = {
1432       Chain, DAG.getTargetExternalSymbol(ProtoStr, MVT::i32), InFlag,
1433     };
1434     Chain = DAG.getNode(NVPTXISD::CallPrototype, dl, ProtoVTs, ProtoOps);
1435     InFlag = Chain.getValue(1);
1436   }
1437   // Op to just print "call"
1438   SDVTList PrintCallVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1439   SDValue PrintCallOps[] = {
1440     Chain, DAG.getConstant((Ins.size() == 0) ? 0 : 1, dl, MVT::i32), InFlag
1441   };
1442   Chain = DAG.getNode(Func ? (NVPTXISD::PrintCallUni) : (NVPTXISD::PrintCall),
1443                       dl, PrintCallVTs, PrintCallOps);
1444   InFlag = Chain.getValue(1);
1445 
1446   // Ops to print out the function name
1447   SDVTList CallVoidVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1448   SDValue CallVoidOps[] = { Chain, Callee, InFlag };
1449   Chain = DAG.getNode(NVPTXISD::CallVoid, dl, CallVoidVTs, CallVoidOps);
1450   InFlag = Chain.getValue(1);
1451 
1452   // Ops to print out the param list
1453   SDVTList CallArgBeginVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1454   SDValue CallArgBeginOps[] = { Chain, InFlag };
1455   Chain = DAG.getNode(NVPTXISD::CallArgBegin, dl, CallArgBeginVTs,
1456                       CallArgBeginOps);
1457   InFlag = Chain.getValue(1);
1458 
1459   for (unsigned i = 0, e = paramCount; i != e; ++i) {
1460     unsigned opcode;
1461     if (i == (e - 1))
1462       opcode = NVPTXISD::LastCallArg;
1463     else
1464       opcode = NVPTXISD::CallArg;
1465     SDVTList CallArgVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1466     SDValue CallArgOps[] = { Chain, DAG.getConstant(1, dl, MVT::i32),
1467                              DAG.getConstant(i, dl, MVT::i32), InFlag };
1468     Chain = DAG.getNode(opcode, dl, CallArgVTs, CallArgOps);
1469     InFlag = Chain.getValue(1);
1470   }
1471   SDVTList CallArgEndVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1472   SDValue CallArgEndOps[] = { Chain,
1473                               DAG.getConstant(Func ? 1 : 0, dl, MVT::i32),
1474                               InFlag };
1475   Chain = DAG.getNode(NVPTXISD::CallArgEnd, dl, CallArgEndVTs, CallArgEndOps);
1476   InFlag = Chain.getValue(1);
1477 
1478   if (!Func) {
1479     SDVTList PrototypeVTs = DAG.getVTList(MVT::Other, MVT::Glue);
1480     SDValue PrototypeOps[] = { Chain,
1481                                DAG.getConstant(uniqueCallSite, dl, MVT::i32),
1482                                InFlag };
1483     Chain = DAG.getNode(NVPTXISD::Prototype, dl, PrototypeVTs, PrototypeOps);
1484     InFlag = Chain.getValue(1);
1485   }
1486 
1487   // Generate loads from param memory/moves from registers for result
1488   if (Ins.size() > 0) {
1489     if (retTy && retTy->isVectorTy()) {
1490       EVT ObjectVT = getValueType(DL, retTy);
1491       unsigned NumElts = ObjectVT.getVectorNumElements();
1492       EVT EltVT = ObjectVT.getVectorElementType();
1493       assert(STI.getTargetLowering()->getNumRegisters(F->getContext(),
1494                                                       ObjectVT) == NumElts &&
1495              "Vector was not scalarized");
1496       unsigned sz = EltVT.getSizeInBits();
1497       bool needTruncate = sz < 8;
1498 
1499       if (NumElts == 1) {
1500         // Just a simple load
1501         SmallVector<EVT, 4> LoadRetVTs;
1502         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1503           // If loading i1/i8 result, generate
1504           //   load.b8 i16
1505           //   if i1
1506           //   trunc i16 to i1
1507           LoadRetVTs.push_back(MVT::i16);
1508         } else
1509           LoadRetVTs.push_back(EltVT);
1510         LoadRetVTs.push_back(MVT::Other);
1511         LoadRetVTs.push_back(MVT::Glue);
1512         SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1513                                 DAG.getConstant(0, dl, MVT::i32), InFlag};
1514         SDValue retval = DAG.getMemIntrinsicNode(
1515             NVPTXISD::LoadParam, dl,
1516             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1517         Chain = retval.getValue(1);
1518         InFlag = retval.getValue(2);
1519         SDValue Ret0 = retval;
1520         if (needTruncate)
1521           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Ret0);
1522         InVals.push_back(Ret0);
1523       } else if (NumElts == 2) {
1524         // LoadV2
1525         SmallVector<EVT, 4> LoadRetVTs;
1526         if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1527           // If loading i1/i8 result, generate
1528           //   load.b8 i16
1529           //   if i1
1530           //   trunc i16 to i1
1531           LoadRetVTs.push_back(MVT::i16);
1532           LoadRetVTs.push_back(MVT::i16);
1533         } else {
1534           LoadRetVTs.push_back(EltVT);
1535           LoadRetVTs.push_back(EltVT);
1536         }
1537         LoadRetVTs.push_back(MVT::Other);
1538         LoadRetVTs.push_back(MVT::Glue);
1539         SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1540                                 DAG.getConstant(0, dl, MVT::i32), InFlag};
1541         SDValue retval = DAG.getMemIntrinsicNode(
1542             NVPTXISD::LoadParamV2, dl,
1543             DAG.getVTList(LoadRetVTs), LoadRetOps, EltVT, MachinePointerInfo());
1544         Chain = retval.getValue(2);
1545         InFlag = retval.getValue(3);
1546         SDValue Ret0 = retval.getValue(0);
1547         SDValue Ret1 = retval.getValue(1);
1548         if (needTruncate) {
1549           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret0);
1550           InVals.push_back(Ret0);
1551           Ret1 = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, Ret1);
1552           InVals.push_back(Ret1);
1553         } else {
1554           InVals.push_back(Ret0);
1555           InVals.push_back(Ret1);
1556         }
1557       } else {
1558         // Split into N LoadV4
1559         unsigned Ofst = 0;
1560         unsigned VecSize = 4;
1561         unsigned Opc = NVPTXISD::LoadParamV4;
1562         if (EltVT.getSizeInBits() == 64) {
1563           VecSize = 2;
1564           Opc = NVPTXISD::LoadParamV2;
1565         }
1566         EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
1567         for (unsigned i = 0; i < NumElts; i += VecSize) {
1568           SmallVector<EVT, 8> LoadRetVTs;
1569           if (EltVT == MVT::i1 || EltVT == MVT::i8) {
1570             // If loading i1/i8 result, generate
1571             //   load.b8 i16
1572             //   if i1
1573             //   trunc i16 to i1
1574             for (unsigned j = 0; j < VecSize; ++j)
1575               LoadRetVTs.push_back(MVT::i16);
1576           } else {
1577             for (unsigned j = 0; j < VecSize; ++j)
1578               LoadRetVTs.push_back(EltVT);
1579           }
1580           LoadRetVTs.push_back(MVT::Other);
1581           LoadRetVTs.push_back(MVT::Glue);
1582           SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1583                                   DAG.getConstant(Ofst, dl, MVT::i32), InFlag};
1584           SDValue retval = DAG.getMemIntrinsicNode(
1585               Opc, dl, DAG.getVTList(LoadRetVTs),
1586               LoadRetOps, EltVT, MachinePointerInfo());
1587           if (VecSize == 2) {
1588             Chain = retval.getValue(2);
1589             InFlag = retval.getValue(3);
1590           } else {
1591             Chain = retval.getValue(4);
1592             InFlag = retval.getValue(5);
1593           }
1594 
1595           for (unsigned j = 0; j < VecSize; ++j) {
1596             if (i + j >= NumElts)
1597               break;
1598             SDValue Elt = retval.getValue(j);
1599             if (needTruncate)
1600               Elt = DAG.getNode(ISD::TRUNCATE, dl, EltVT, Elt);
1601             InVals.push_back(Elt);
1602           }
1603           Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
1604         }
1605       }
1606     } else {
1607       SmallVector<EVT, 16> VTs;
1608       SmallVector<uint64_t, 16> Offsets;
1609       ComputePTXValueVTs(*this, DAG.getDataLayout(), retTy, VTs, &Offsets, 0);
1610       assert(VTs.size() == Ins.size() && "Bad value decomposition");
1611       unsigned RetAlign = getArgumentAlignment(Callee, CS, retTy, 0);
1612       for (unsigned i = 0, e = Ins.size(); i != e; ++i) {
1613         unsigned sz = VTs[i].getSizeInBits();
1614         unsigned AlignI = GreatestCommonDivisor64(RetAlign, Offsets[i]);
1615         bool needTruncate = sz < 8;
1616         if (VTs[i].isInteger() && (sz < 8))
1617           sz = 8;
1618 
1619         SmallVector<EVT, 4> LoadRetVTs;
1620         EVT TheLoadType = VTs[i];
1621         if (retTy->isIntegerTy() && DL.getTypeAllocSizeInBits(retTy) < 32) {
1622           // This is for integer types only, and specifically not for
1623           // aggregates.
1624           LoadRetVTs.push_back(MVT::i32);
1625           TheLoadType = MVT::i32;
1626         } else if (sz < 16) {
1627           // If loading i1/i8 result, generate
1628           //   load i8 (-> i16)
1629           //   trunc i16 to i1/i8
1630           LoadRetVTs.push_back(MVT::i16);
1631         } else
1632           LoadRetVTs.push_back(Ins[i].VT);
1633         LoadRetVTs.push_back(MVT::Other);
1634         LoadRetVTs.push_back(MVT::Glue);
1635 
1636         SDValue LoadRetOps[] = {Chain, DAG.getConstant(1, dl, MVT::i32),
1637                                 DAG.getConstant(Offsets[i], dl, MVT::i32),
1638                                 InFlag};
1639         SDValue retval = DAG.getMemIntrinsicNode(
1640             NVPTXISD::LoadParam, dl,
1641             DAG.getVTList(LoadRetVTs), LoadRetOps,
1642             TheLoadType, MachinePointerInfo(), AlignI);
1643         Chain = retval.getValue(1);
1644         InFlag = retval.getValue(2);
1645         SDValue Ret0 = retval.getValue(0);
1646         if (needTruncate)
1647           Ret0 = DAG.getNode(ISD::TRUNCATE, dl, Ins[i].VT, Ret0);
1648         InVals.push_back(Ret0);
1649       }
1650     }
1651   }
1652 
1653   Chain = DAG.getCALLSEQ_END(Chain,
1654                              DAG.getIntPtrConstant(uniqueCallSite, dl, true),
1655                              DAG.getIntPtrConstant(uniqueCallSite + 1, dl,
1656                                                    true),
1657                              InFlag, dl);
1658   uniqueCallSite++;
1659 
1660   // set isTailCall to false for now, until we figure out how to express
1661   // tail call optimization in PTX
1662   isTailCall = false;
1663   return Chain;
1664 }
1665 
1666 // By default CONCAT_VECTORS is lowered by ExpandVectorBuildThroughStack()
1667 // (see LegalizeDAG.cpp). This is slow and uses local memory.
1668 // We use extract/insert/build vector just as what LegalizeOp() does in llvm 2.5
1669 SDValue
1670 NVPTXTargetLowering::LowerCONCAT_VECTORS(SDValue Op, SelectionDAG &DAG) const {
1671   SDNode *Node = Op.getNode();
1672   SDLoc dl(Node);
1673   SmallVector<SDValue, 8> Ops;
1674   unsigned NumOperands = Node->getNumOperands();
1675   for (unsigned i = 0; i < NumOperands; ++i) {
1676     SDValue SubOp = Node->getOperand(i);
1677     EVT VVT = SubOp.getNode()->getValueType(0);
1678     EVT EltVT = VVT.getVectorElementType();
1679     unsigned NumSubElem = VVT.getVectorNumElements();
1680     for (unsigned j = 0; j < NumSubElem; ++j) {
1681       Ops.push_back(DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, SubOp,
1682                                 DAG.getIntPtrConstant(j, dl)));
1683     }
1684   }
1685   return DAG.getNode(ISD::BUILD_VECTOR, dl, Node->getValueType(0), Ops);
1686 }
1687 
1688 /// LowerShiftRightParts - Lower SRL_PARTS, SRA_PARTS, which
1689 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1690 ///    amount, or
1691 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1692 ///    amount.
1693 SDValue NVPTXTargetLowering::LowerShiftRightParts(SDValue Op,
1694                                                   SelectionDAG &DAG) const {
1695   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1696   assert(Op.getOpcode() == ISD::SRA_PARTS || Op.getOpcode() == ISD::SRL_PARTS);
1697 
1698   EVT VT = Op.getValueType();
1699   unsigned VTBits = VT.getSizeInBits();
1700   SDLoc dl(Op);
1701   SDValue ShOpLo = Op.getOperand(0);
1702   SDValue ShOpHi = Op.getOperand(1);
1703   SDValue ShAmt  = Op.getOperand(2);
1704   unsigned Opc = (Op.getOpcode() == ISD::SRA_PARTS) ? ISD::SRA : ISD::SRL;
1705 
1706   if (VTBits == 32 && STI.getSmVersion() >= 35) {
1707 
1708     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1709     // {dHi, dLo} = {aHi, aLo} >> Amt
1710     //   dHi = aHi >> Amt
1711     //   dLo = shf.r.clamp aLo, aHi, Amt
1712 
1713     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1714     SDValue Lo = DAG.getNode(NVPTXISD::FUN_SHFR_CLAMP, dl, VT, ShOpLo, ShOpHi,
1715                              ShAmt);
1716 
1717     SDValue Ops[2] = { Lo, Hi };
1718     return DAG.getMergeValues(Ops, dl);
1719   }
1720   else {
1721 
1722     // {dHi, dLo} = {aHi, aLo} >> Amt
1723     // - if (Amt>=size) then
1724     //      dLo = aHi >> (Amt-size)
1725     //      dHi = aHi >> Amt (this is either all 0 or all 1)
1726     //   else
1727     //      dLo = (aLo >>logic Amt) | (aHi << (size-Amt))
1728     //      dHi = aHi >> Amt
1729 
1730     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1731                                    DAG.getConstant(VTBits, dl, MVT::i32),
1732                                    ShAmt);
1733     SDValue Tmp1 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, ShAmt);
1734     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1735                                      DAG.getConstant(VTBits, dl, MVT::i32));
1736     SDValue Tmp2 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, RevShAmt);
1737     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1738     SDValue TrueVal = DAG.getNode(Opc, dl, VT, ShOpHi, ExtraShAmt);
1739 
1740     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1741                                DAG.getConstant(VTBits, dl, MVT::i32),
1742                                ISD::SETGE);
1743     SDValue Hi = DAG.getNode(Opc, dl, VT, ShOpHi, ShAmt);
1744     SDValue Lo = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1745 
1746     SDValue Ops[2] = { Lo, Hi };
1747     return DAG.getMergeValues(Ops, dl);
1748   }
1749 }
1750 
1751 /// LowerShiftLeftParts - Lower SHL_PARTS, which
1752 /// 1) returns two i32 values and take a 2 x i32 value to shift plus a shift
1753 ///    amount, or
1754 /// 2) returns two i64 values and take a 2 x i64 value to shift plus a shift
1755 ///    amount.
1756 SDValue NVPTXTargetLowering::LowerShiftLeftParts(SDValue Op,
1757                                                  SelectionDAG &DAG) const {
1758   assert(Op.getNumOperands() == 3 && "Not a double-shift!");
1759   assert(Op.getOpcode() == ISD::SHL_PARTS);
1760 
1761   EVT VT = Op.getValueType();
1762   unsigned VTBits = VT.getSizeInBits();
1763   SDLoc dl(Op);
1764   SDValue ShOpLo = Op.getOperand(0);
1765   SDValue ShOpHi = Op.getOperand(1);
1766   SDValue ShAmt  = Op.getOperand(2);
1767 
1768   if (VTBits == 32 && STI.getSmVersion() >= 35) {
1769 
1770     // For 32bit and sm35, we can use the funnel shift 'shf' instruction.
1771     // {dHi, dLo} = {aHi, aLo} << Amt
1772     //   dHi = shf.l.clamp aLo, aHi, Amt
1773     //   dLo = aLo << Amt
1774 
1775     SDValue Hi = DAG.getNode(NVPTXISD::FUN_SHFL_CLAMP, dl, VT, ShOpLo, ShOpHi,
1776                              ShAmt);
1777     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1778 
1779     SDValue Ops[2] = { Lo, Hi };
1780     return DAG.getMergeValues(Ops, dl);
1781   }
1782   else {
1783 
1784     // {dHi, dLo} = {aHi, aLo} << Amt
1785     // - if (Amt>=size) then
1786     //      dLo = aLo << Amt (all 0)
1787     //      dLo = aLo << (Amt-size)
1788     //   else
1789     //      dLo = aLo << Amt
1790     //      dHi = (aHi << Amt) | (aLo >> (size-Amt))
1791 
1792     SDValue RevShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32,
1793                                    DAG.getConstant(VTBits, dl, MVT::i32),
1794                                    ShAmt);
1795     SDValue Tmp1 = DAG.getNode(ISD::SHL, dl, VT, ShOpHi, ShAmt);
1796     SDValue ExtraShAmt = DAG.getNode(ISD::SUB, dl, MVT::i32, ShAmt,
1797                                      DAG.getConstant(VTBits, dl, MVT::i32));
1798     SDValue Tmp2 = DAG.getNode(ISD::SRL, dl, VT, ShOpLo, RevShAmt);
1799     SDValue FalseVal = DAG.getNode(ISD::OR, dl, VT, Tmp1, Tmp2);
1800     SDValue TrueVal = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ExtraShAmt);
1801 
1802     SDValue Cmp = DAG.getSetCC(dl, MVT::i1, ShAmt,
1803                                DAG.getConstant(VTBits, dl, MVT::i32),
1804                                ISD::SETGE);
1805     SDValue Lo = DAG.getNode(ISD::SHL, dl, VT, ShOpLo, ShAmt);
1806     SDValue Hi = DAG.getNode(ISD::SELECT, dl, VT, Cmp, TrueVal, FalseVal);
1807 
1808     SDValue Ops[2] = { Lo, Hi };
1809     return DAG.getMergeValues(Ops, dl);
1810   }
1811 }
1812 
1813 SDValue
1814 NVPTXTargetLowering::LowerOperation(SDValue Op, SelectionDAG &DAG) const {
1815   switch (Op.getOpcode()) {
1816   case ISD::RETURNADDR:
1817     return SDValue();
1818   case ISD::FRAMEADDR:
1819     return SDValue();
1820   case ISD::GlobalAddress:
1821     return LowerGlobalAddress(Op, DAG);
1822   case ISD::INTRINSIC_W_CHAIN:
1823     return Op;
1824   case ISD::BUILD_VECTOR:
1825   case ISD::EXTRACT_SUBVECTOR:
1826     return Op;
1827   case ISD::CONCAT_VECTORS:
1828     return LowerCONCAT_VECTORS(Op, DAG);
1829   case ISD::STORE:
1830     return LowerSTORE(Op, DAG);
1831   case ISD::LOAD:
1832     return LowerLOAD(Op, DAG);
1833   case ISD::SHL_PARTS:
1834     return LowerShiftLeftParts(Op, DAG);
1835   case ISD::SRA_PARTS:
1836   case ISD::SRL_PARTS:
1837     return LowerShiftRightParts(Op, DAG);
1838   case ISD::SELECT:
1839     return LowerSelect(Op, DAG);
1840   default:
1841     llvm_unreachable("Custom lowering not defined for operation");
1842   }
1843 }
1844 
1845 SDValue NVPTXTargetLowering::LowerSelect(SDValue Op, SelectionDAG &DAG) const {
1846   SDValue Op0 = Op->getOperand(0);
1847   SDValue Op1 = Op->getOperand(1);
1848   SDValue Op2 = Op->getOperand(2);
1849   SDLoc DL(Op.getNode());
1850 
1851   assert(Op.getValueType() == MVT::i1 && "Custom lowering enabled only for i1");
1852 
1853   Op1 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op1);
1854   Op2 = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i32, Op2);
1855   SDValue Select = DAG.getNode(ISD::SELECT, DL, MVT::i32, Op0, Op1, Op2);
1856   SDValue Trunc = DAG.getNode(ISD::TRUNCATE, DL, MVT::i1, Select);
1857 
1858   return Trunc;
1859 }
1860 
1861 SDValue NVPTXTargetLowering::LowerLOAD(SDValue Op, SelectionDAG &DAG) const {
1862   if (Op.getValueType() == MVT::i1)
1863     return LowerLOADi1(Op, DAG);
1864   else
1865     return SDValue();
1866 }
1867 
1868 // v = ld i1* addr
1869 //   =>
1870 // v1 = ld i8* addr (-> i16)
1871 // v = trunc i16 to i1
1872 SDValue NVPTXTargetLowering::LowerLOADi1(SDValue Op, SelectionDAG &DAG) const {
1873   SDNode *Node = Op.getNode();
1874   LoadSDNode *LD = cast<LoadSDNode>(Node);
1875   SDLoc dl(Node);
1876   assert(LD->getExtensionType() == ISD::NON_EXTLOAD);
1877   assert(Node->getValueType(0) == MVT::i1 &&
1878          "Custom lowering for i1 load only");
1879   SDValue newLD =
1880       DAG.getLoad(MVT::i16, dl, LD->getChain(), LD->getBasePtr(),
1881                   LD->getPointerInfo(), LD->isVolatile(), LD->isNonTemporal(),
1882                   LD->isInvariant(), LD->getAlignment());
1883   SDValue result = DAG.getNode(ISD::TRUNCATE, dl, MVT::i1, newLD);
1884   // The legalizer (the caller) is expecting two values from the legalized
1885   // load, so we build a MergeValues node for it. See ExpandUnalignedLoad()
1886   // in LegalizeDAG.cpp which also uses MergeValues.
1887   SDValue Ops[] = { result, LD->getChain() };
1888   return DAG.getMergeValues(Ops, dl);
1889 }
1890 
1891 SDValue NVPTXTargetLowering::LowerSTORE(SDValue Op, SelectionDAG &DAG) const {
1892   EVT ValVT = Op.getOperand(1).getValueType();
1893   if (ValVT == MVT::i1)
1894     return LowerSTOREi1(Op, DAG);
1895   else if (ValVT.isVector())
1896     return LowerSTOREVector(Op, DAG);
1897   else
1898     return SDValue();
1899 }
1900 
1901 SDValue
1902 NVPTXTargetLowering::LowerSTOREVector(SDValue Op, SelectionDAG &DAG) const {
1903   SDNode *N = Op.getNode();
1904   SDValue Val = N->getOperand(1);
1905   SDLoc DL(N);
1906   EVT ValVT = Val.getValueType();
1907 
1908   if (ValVT.isVector()) {
1909     // We only handle "native" vector sizes for now, e.g. <4 x double> is not
1910     // legal.  We can (and should) split that into 2 stores of <2 x double> here
1911     // but I'm leaving that as a TODO for now.
1912     if (!ValVT.isSimple())
1913       return SDValue();
1914     switch (ValVT.getSimpleVT().SimpleTy) {
1915     default:
1916       return SDValue();
1917     case MVT::v2i8:
1918     case MVT::v2i16:
1919     case MVT::v2i32:
1920     case MVT::v2i64:
1921     case MVT::v2f32:
1922     case MVT::v2f64:
1923     case MVT::v4i8:
1924     case MVT::v4i16:
1925     case MVT::v4i32:
1926     case MVT::v4f32:
1927       // This is a "native" vector type
1928       break;
1929     }
1930 
1931     MemSDNode *MemSD = cast<MemSDNode>(N);
1932     const DataLayout &TD = DAG.getDataLayout();
1933 
1934     unsigned Align = MemSD->getAlignment();
1935     unsigned PrefAlign =
1936         TD.getPrefTypeAlignment(ValVT.getTypeForEVT(*DAG.getContext()));
1937     if (Align < PrefAlign) {
1938       // This store is not sufficiently aligned, so bail out and let this vector
1939       // store be scalarized.  Note that we may still be able to emit smaller
1940       // vector stores.  For example, if we are storing a <4 x float> with an
1941       // alignment of 8, this check will fail but the legalizer will try again
1942       // with 2 x <2 x float>, which will succeed with an alignment of 8.
1943       return SDValue();
1944     }
1945 
1946     unsigned Opcode = 0;
1947     EVT EltVT = ValVT.getVectorElementType();
1948     unsigned NumElts = ValVT.getVectorNumElements();
1949 
1950     // Since StoreV2 is a target node, we cannot rely on DAG type legalization.
1951     // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
1952     // stored type to i16 and propagate the "real" type as the memory type.
1953     bool NeedExt = false;
1954     if (EltVT.getSizeInBits() < 16)
1955       NeedExt = true;
1956 
1957     switch (NumElts) {
1958     default:
1959       return SDValue();
1960     case 2:
1961       Opcode = NVPTXISD::StoreV2;
1962       break;
1963     case 4: {
1964       Opcode = NVPTXISD::StoreV4;
1965       break;
1966     }
1967     }
1968 
1969     SmallVector<SDValue, 8> Ops;
1970 
1971     // First is the chain
1972     Ops.push_back(N->getOperand(0));
1973 
1974     // Then the split values
1975     for (unsigned i = 0; i < NumElts; ++i) {
1976       SDValue ExtVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, DL, EltVT, Val,
1977                                    DAG.getIntPtrConstant(i, DL));
1978       if (NeedExt)
1979         ExtVal = DAG.getNode(ISD::ANY_EXTEND, DL, MVT::i16, ExtVal);
1980       Ops.push_back(ExtVal);
1981     }
1982 
1983     // Then any remaining arguments
1984     Ops.append(N->op_begin() + 2, N->op_end());
1985 
1986     SDValue NewSt = DAG.getMemIntrinsicNode(
1987         Opcode, DL, DAG.getVTList(MVT::Other), Ops,
1988         MemSD->getMemoryVT(), MemSD->getMemOperand());
1989 
1990     //return DCI.CombineTo(N, NewSt, true);
1991     return NewSt;
1992   }
1993 
1994   return SDValue();
1995 }
1996 
1997 // st i1 v, addr
1998 //    =>
1999 // v1 = zxt v to i16
2000 // st.u8 i16, addr
2001 SDValue NVPTXTargetLowering::LowerSTOREi1(SDValue Op, SelectionDAG &DAG) const {
2002   SDNode *Node = Op.getNode();
2003   SDLoc dl(Node);
2004   StoreSDNode *ST = cast<StoreSDNode>(Node);
2005   SDValue Tmp1 = ST->getChain();
2006   SDValue Tmp2 = ST->getBasePtr();
2007   SDValue Tmp3 = ST->getValue();
2008   assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2009   unsigned Alignment = ST->getAlignment();
2010   bool isVolatile = ST->isVolatile();
2011   bool isNonTemporal = ST->isNonTemporal();
2012   Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2013   SDValue Result = DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2,
2014                                      ST->getPointerInfo(), MVT::i8, isNonTemporal,
2015                                      isVolatile, Alignment);
2016   return Result;
2017 }
2018 
2019 SDValue
2020 NVPTXTargetLowering::getParamSymbol(SelectionDAG &DAG, int idx, EVT v) const {
2021   std::string ParamSym;
2022   raw_string_ostream ParamStr(ParamSym);
2023 
2024   ParamStr << DAG.getMachineFunction().getName() << "_param_" << idx;
2025   ParamStr.flush();
2026 
2027   std::string *SavedStr =
2028     nvTM->getManagedStrPool()->getManagedString(ParamSym.c_str());
2029   return DAG.getTargetExternalSymbol(SavedStr->c_str(), v);
2030 }
2031 
2032 // Check to see if the kernel argument is image*_t or sampler_t
2033 
2034 bool llvm::isImageOrSamplerVal(const Value *arg, const Module *context) {
2035   static const char *const specialTypes[] = { "struct._image2d_t",
2036                                               "struct._image3d_t",
2037                                               "struct._sampler_t" };
2038 
2039   Type *Ty = arg->getType();
2040   auto *PTy = dyn_cast<PointerType>(Ty);
2041 
2042   if (!PTy)
2043     return false;
2044 
2045   if (!context)
2046     return false;
2047 
2048   auto *STy = dyn_cast<StructType>(PTy->getElementType());
2049   const std::string TypeName = STy && !STy->isLiteral() ? STy->getName() : "";
2050 
2051   return std::find(std::begin(specialTypes), std::end(specialTypes),
2052                    TypeName) != std::end(specialTypes);
2053 }
2054 
2055 SDValue NVPTXTargetLowering::LowerFormalArguments(
2056     SDValue Chain, CallingConv::ID CallConv, bool isVarArg,
2057     const SmallVectorImpl<ISD::InputArg> &Ins, SDLoc dl, SelectionDAG &DAG,
2058     SmallVectorImpl<SDValue> &InVals) const {
2059   MachineFunction &MF = DAG.getMachineFunction();
2060   const DataLayout &DL = DAG.getDataLayout();
2061   auto PtrVT = getPointerTy(DAG.getDataLayout());
2062 
2063   const Function *F = MF.getFunction();
2064   const AttributeSet &PAL = F->getAttributes();
2065   const TargetLowering *TLI = STI.getTargetLowering();
2066 
2067   SDValue Root = DAG.getRoot();
2068   std::vector<SDValue> OutChains;
2069 
2070   bool isKernel = llvm::isKernelFunction(*F);
2071   bool isABI = (STI.getSmVersion() >= 20);
2072   assert(isABI && "Non-ABI compilation is not supported");
2073   if (!isABI)
2074     return Chain;
2075 
2076   std::vector<Type *> argTypes;
2077   std::vector<const Argument *> theArgs;
2078   for (const Argument &I : F->args()) {
2079     theArgs.push_back(&I);
2080     argTypes.push_back(I.getType());
2081   }
2082   // argTypes.size() (or theArgs.size()) and Ins.size() need not match.
2083   // Ins.size() will be larger
2084   //   * if there is an aggregate argument with multiple fields (each field
2085   //     showing up separately in Ins)
2086   //   * if there is a vector argument with more than typical vector-length
2087   //     elements (generally if more than 4) where each vector element is
2088   //     individually present in Ins.
2089   // So a different index should be used for indexing into Ins.
2090   // See similar issue in LowerCall.
2091   unsigned InsIdx = 0;
2092 
2093   int idx = 0;
2094   for (unsigned i = 0, e = theArgs.size(); i != e; ++i, ++idx, ++InsIdx) {
2095     Type *Ty = argTypes[i];
2096 
2097     // If the kernel argument is image*_t or sampler_t, convert it to
2098     // a i32 constant holding the parameter position. This can later
2099     // matched in the AsmPrinter to output the correct mangled name.
2100     if (isImageOrSamplerVal(
2101             theArgs[i],
2102             (theArgs[i]->getParent() ? theArgs[i]->getParent()->getParent()
2103                                      : nullptr))) {
2104       assert(isKernel && "Only kernels can have image/sampler params");
2105       InVals.push_back(DAG.getConstant(i + 1, dl, MVT::i32));
2106       continue;
2107     }
2108 
2109     if (theArgs[i]->use_empty()) {
2110       // argument is dead
2111       if (Ty->isAggregateType()) {
2112         SmallVector<EVT, 16> vtparts;
2113 
2114         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts);
2115         assert(vtparts.size() > 0 && "empty aggregate type not expected");
2116         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2117              ++parti) {
2118           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2119           ++InsIdx;
2120         }
2121         if (vtparts.size() > 0)
2122           --InsIdx;
2123         continue;
2124       }
2125       if (Ty->isVectorTy()) {
2126         EVT ObjectVT = getValueType(DL, Ty);
2127         unsigned NumRegs = TLI->getNumRegisters(F->getContext(), ObjectVT);
2128         for (unsigned parti = 0; parti < NumRegs; ++parti) {
2129           InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2130           ++InsIdx;
2131         }
2132         if (NumRegs > 0)
2133           --InsIdx;
2134         continue;
2135       }
2136       InVals.push_back(DAG.getNode(ISD::UNDEF, dl, Ins[InsIdx].VT));
2137       continue;
2138     }
2139 
2140     // In the following cases, assign a node order of "idx+1"
2141     // to newly created nodes. The SDNodes for params have to
2142     // appear in the same order as their order of appearance
2143     // in the original function. "idx+1" holds that order.
2144     if (!PAL.hasAttribute(i + 1, Attribute::ByVal)) {
2145       if (Ty->isAggregateType()) {
2146         SmallVector<EVT, 16> vtparts;
2147         SmallVector<uint64_t, 16> offsets;
2148 
2149         // NOTE: Here, we lose the ability to issue vector loads for vectors
2150         // that are a part of a struct.  This should be investigated in the
2151         // future.
2152         ComputePTXValueVTs(*this, DAG.getDataLayout(), Ty, vtparts, &offsets,
2153                            0);
2154         assert(vtparts.size() > 0 && "empty aggregate type not expected");
2155         bool aggregateIsPacked = false;
2156         if (StructType *STy = llvm::dyn_cast<StructType>(Ty))
2157           aggregateIsPacked = STy->isPacked();
2158 
2159         SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2160         for (unsigned parti = 0, parte = vtparts.size(); parti != parte;
2161              ++parti) {
2162           EVT partVT = vtparts[parti];
2163           Value *srcValue = Constant::getNullValue(
2164               PointerType::get(partVT.getTypeForEVT(F->getContext()),
2165                                llvm::ADDRESS_SPACE_PARAM));
2166           SDValue srcAddr =
2167               DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2168                           DAG.getConstant(offsets[parti], dl, PtrVT));
2169           unsigned partAlign = aggregateIsPacked
2170                                    ? 1
2171                                    : DL.getABITypeAlignment(
2172                                          partVT.getTypeForEVT(F->getContext()));
2173           SDValue p;
2174           if (Ins[InsIdx].VT.getSizeInBits() > partVT.getSizeInBits()) {
2175             ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2176                                      ISD::SEXTLOAD : ISD::ZEXTLOAD;
2177             p = DAG.getExtLoad(ExtOp, dl, Ins[InsIdx].VT, Root, srcAddr,
2178                                MachinePointerInfo(srcValue), partVT, false,
2179                                false, false, partAlign);
2180           } else {
2181             p = DAG.getLoad(partVT, dl, Root, srcAddr,
2182                             MachinePointerInfo(srcValue), false, false, false,
2183                             partAlign);
2184           }
2185           if (p.getNode())
2186             p.getNode()->setIROrder(idx + 1);
2187           InVals.push_back(p);
2188           ++InsIdx;
2189         }
2190         if (vtparts.size() > 0)
2191           --InsIdx;
2192         continue;
2193       }
2194       if (Ty->isVectorTy()) {
2195         EVT ObjectVT = getValueType(DL, Ty);
2196         SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2197         unsigned NumElts = ObjectVT.getVectorNumElements();
2198         assert(TLI->getNumRegisters(F->getContext(), ObjectVT) == NumElts &&
2199                "Vector was not scalarized");
2200         EVT EltVT = ObjectVT.getVectorElementType();
2201 
2202         // V1 load
2203         // f32 = load ...
2204         if (NumElts == 1) {
2205           // We only have one element, so just directly load it
2206           Value *SrcValue = Constant::getNullValue(PointerType::get(
2207               EltVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2208           SDValue P = DAG.getLoad(
2209               EltVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2210               true,
2211               DL.getABITypeAlignment(EltVT.getTypeForEVT(F->getContext())));
2212           if (P.getNode())
2213             P.getNode()->setIROrder(idx + 1);
2214 
2215           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2216             P = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, P);
2217           InVals.push_back(P);
2218           ++InsIdx;
2219         } else if (NumElts == 2) {
2220           // V2 load
2221           // f32,f32 = load ...
2222           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, 2);
2223           Value *SrcValue = Constant::getNullValue(PointerType::get(
2224               VecVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2225           SDValue P = DAG.getLoad(
2226               VecVT, dl, Root, Arg, MachinePointerInfo(SrcValue), false, false,
2227               true,
2228               DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2229           if (P.getNode())
2230             P.getNode()->setIROrder(idx + 1);
2231 
2232           SDValue Elt0 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2233                                      DAG.getIntPtrConstant(0, dl));
2234           SDValue Elt1 = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2235                                      DAG.getIntPtrConstant(1, dl));
2236 
2237           if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits()) {
2238             Elt0 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt0);
2239             Elt1 = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt1);
2240           }
2241 
2242           InVals.push_back(Elt0);
2243           InVals.push_back(Elt1);
2244           InsIdx += 2;
2245         } else {
2246           // V4 loads
2247           // We have at least 4 elements (<3 x Ty> expands to 4 elements) and
2248           // the
2249           // vector will be expanded to a power of 2 elements, so we know we can
2250           // always round up to the next multiple of 4 when creating the vector
2251           // loads.
2252           // e.g.  4 elem => 1 ld.v4
2253           //       6 elem => 2 ld.v4
2254           //       8 elem => 2 ld.v4
2255           //      11 elem => 3 ld.v4
2256           unsigned VecSize = 4;
2257           if (EltVT.getSizeInBits() == 64) {
2258             VecSize = 2;
2259           }
2260           EVT VecVT = EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2261           unsigned Ofst = 0;
2262           for (unsigned i = 0; i < NumElts; i += VecSize) {
2263             Value *SrcValue = Constant::getNullValue(
2264                 PointerType::get(VecVT.getTypeForEVT(F->getContext()),
2265                                  llvm::ADDRESS_SPACE_PARAM));
2266             SDValue SrcAddr = DAG.getNode(ISD::ADD, dl, PtrVT, Arg,
2267                                           DAG.getConstant(Ofst, dl, PtrVT));
2268             SDValue P = DAG.getLoad(
2269                 VecVT, dl, Root, SrcAddr, MachinePointerInfo(SrcValue), false,
2270                 false, true,
2271                 DL.getABITypeAlignment(VecVT.getTypeForEVT(F->getContext())));
2272             if (P.getNode())
2273               P.getNode()->setIROrder(idx + 1);
2274 
2275             for (unsigned j = 0; j < VecSize; ++j) {
2276               if (i + j >= NumElts)
2277                 break;
2278               SDValue Elt = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl, EltVT, P,
2279                                         DAG.getIntPtrConstant(j, dl));
2280               if (Ins[InsIdx].VT.getSizeInBits() > EltVT.getSizeInBits())
2281                 Elt = DAG.getNode(ISD::ANY_EXTEND, dl, Ins[InsIdx].VT, Elt);
2282               InVals.push_back(Elt);
2283             }
2284             Ofst += DL.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2285           }
2286           InsIdx += NumElts;
2287         }
2288 
2289         if (NumElts > 0)
2290           --InsIdx;
2291         continue;
2292       }
2293       // A plain scalar.
2294       EVT ObjectVT = getValueType(DL, Ty);
2295       // If ABI, load from the param symbol
2296       SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2297       Value *srcValue = Constant::getNullValue(PointerType::get(
2298           ObjectVT.getTypeForEVT(F->getContext()), llvm::ADDRESS_SPACE_PARAM));
2299       SDValue p;
2300        if (ObjectVT.getSizeInBits() < Ins[InsIdx].VT.getSizeInBits()) {
2301         ISD::LoadExtType ExtOp = Ins[InsIdx].Flags.isSExt() ?
2302                                        ISD::SEXTLOAD : ISD::ZEXTLOAD;
2303         p = DAG.getExtLoad(
2304             ExtOp, dl, Ins[InsIdx].VT, Root, Arg, MachinePointerInfo(srcValue),
2305             ObjectVT, false, false, false,
2306             DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2307       } else {
2308         p = DAG.getLoad(
2309             Ins[InsIdx].VT, dl, Root, Arg, MachinePointerInfo(srcValue), false,
2310             false, false,
2311             DL.getABITypeAlignment(ObjectVT.getTypeForEVT(F->getContext())));
2312       }
2313       if (p.getNode())
2314         p.getNode()->setIROrder(idx + 1);
2315       InVals.push_back(p);
2316       continue;
2317     }
2318 
2319     // Param has ByVal attribute
2320     // Return MoveParam(param symbol).
2321     // Ideally, the param symbol can be returned directly,
2322     // but when SDNode builder decides to use it in a CopyToReg(),
2323     // machine instruction fails because TargetExternalSymbol
2324     // (not lowered) is target dependent, and CopyToReg assumes
2325     // the source is lowered.
2326     EVT ObjectVT = getValueType(DL, Ty);
2327     assert(ObjectVT == Ins[InsIdx].VT &&
2328            "Ins type did not match function type");
2329     SDValue Arg = getParamSymbol(DAG, idx, PtrVT);
2330     SDValue p = DAG.getNode(NVPTXISD::MoveParam, dl, ObjectVT, Arg);
2331     if (p.getNode())
2332       p.getNode()->setIROrder(idx + 1);
2333     if (isKernel)
2334       InVals.push_back(p);
2335     else {
2336       SDValue p2 = DAG.getNode(
2337           ISD::INTRINSIC_WO_CHAIN, dl, ObjectVT,
2338           DAG.getConstant(Intrinsic::nvvm_ptr_local_to_gen, dl, MVT::i32), p);
2339       InVals.push_back(p2);
2340     }
2341   }
2342 
2343   // Clang will check explicit VarArg and issue error if any. However, Clang
2344   // will let code with
2345   // implicit var arg like f() pass. See bug 617733.
2346   // We treat this case as if the arg list is empty.
2347   // if (F.isVarArg()) {
2348   // assert(0 && "VarArg not supported yet!");
2349   //}
2350 
2351   if (!OutChains.empty())
2352     DAG.setRoot(DAG.getNode(ISD::TokenFactor, dl, MVT::Other, OutChains));
2353 
2354   return Chain;
2355 }
2356 
2357 
2358 SDValue
2359 NVPTXTargetLowering::LowerReturn(SDValue Chain, CallingConv::ID CallConv,
2360                                  bool isVarArg,
2361                                  const SmallVectorImpl<ISD::OutputArg> &Outs,
2362                                  const SmallVectorImpl<SDValue> &OutVals,
2363                                  SDLoc dl, SelectionDAG &DAG) const {
2364   MachineFunction &MF = DAG.getMachineFunction();
2365   const Function *F = MF.getFunction();
2366   Type *RetTy = F->getReturnType();
2367   const DataLayout &TD = DAG.getDataLayout();
2368 
2369   bool isABI = (STI.getSmVersion() >= 20);
2370   assert(isABI && "Non-ABI compilation is not supported");
2371   if (!isABI)
2372     return Chain;
2373 
2374   if (VectorType *VTy = dyn_cast<VectorType>(RetTy)) {
2375     // If we have a vector type, the OutVals array will be the scalarized
2376     // components and we have combine them into 1 or more vector stores.
2377     unsigned NumElts = VTy->getNumElements();
2378     assert(NumElts == Outs.size() && "Bad scalarization of return value");
2379 
2380     // const_cast can be removed in later LLVM versions
2381     EVT EltVT = getValueType(TD, RetTy).getVectorElementType();
2382     bool NeedExtend = false;
2383     if (EltVT.getSizeInBits() < 16)
2384       NeedExtend = true;
2385 
2386     // V1 store
2387     if (NumElts == 1) {
2388       SDValue StoreVal = OutVals[0];
2389       // We only have one element, so just directly store it
2390       if (NeedExtend)
2391         StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal);
2392       SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal };
2393       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2394                                       DAG.getVTList(MVT::Other), Ops,
2395                                       EltVT, MachinePointerInfo());
2396 
2397     } else if (NumElts == 2) {
2398       // V2 store
2399       SDValue StoreVal0 = OutVals[0];
2400       SDValue StoreVal1 = OutVals[1];
2401 
2402       if (NeedExtend) {
2403         StoreVal0 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal0);
2404         StoreVal1 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, StoreVal1);
2405       }
2406 
2407       SDValue Ops[] = { Chain, DAG.getConstant(0, dl, MVT::i32), StoreVal0,
2408                         StoreVal1 };
2409       Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetvalV2, dl,
2410                                       DAG.getVTList(MVT::Other), Ops,
2411                                       EltVT, MachinePointerInfo());
2412     } else {
2413       // V4 stores
2414       // We have at least 4 elements (<3 x Ty> expands to 4 elements) and the
2415       // vector will be expanded to a power of 2 elements, so we know we can
2416       // always round up to the next multiple of 4 when creating the vector
2417       // stores.
2418       // e.g.  4 elem => 1 st.v4
2419       //       6 elem => 2 st.v4
2420       //       8 elem => 2 st.v4
2421       //      11 elem => 3 st.v4
2422 
2423       unsigned VecSize = 4;
2424       if (OutVals[0].getValueType().getSizeInBits() == 64)
2425         VecSize = 2;
2426 
2427       unsigned Offset = 0;
2428 
2429       EVT VecVT =
2430           EVT::getVectorVT(F->getContext(), EltVT, VecSize);
2431       unsigned PerStoreOffset =
2432           TD.getTypeAllocSize(VecVT.getTypeForEVT(F->getContext()));
2433 
2434       for (unsigned i = 0; i < NumElts; i += VecSize) {
2435         // Get values
2436         SDValue StoreVal;
2437         SmallVector<SDValue, 8> Ops;
2438         Ops.push_back(Chain);
2439         Ops.push_back(DAG.getConstant(Offset, dl, MVT::i32));
2440         unsigned Opc = NVPTXISD::StoreRetvalV2;
2441         EVT ExtendedVT = (NeedExtend) ? MVT::i16 : OutVals[0].getValueType();
2442 
2443         StoreVal = OutVals[i];
2444         if (NeedExtend)
2445           StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2446         Ops.push_back(StoreVal);
2447 
2448         if (i + 1 < NumElts) {
2449           StoreVal = OutVals[i + 1];
2450           if (NeedExtend)
2451             StoreVal = DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2452         } else {
2453           StoreVal = DAG.getUNDEF(ExtendedVT);
2454         }
2455         Ops.push_back(StoreVal);
2456 
2457         if (VecSize == 4) {
2458           Opc = NVPTXISD::StoreRetvalV4;
2459           if (i + 2 < NumElts) {
2460             StoreVal = OutVals[i + 2];
2461             if (NeedExtend)
2462               StoreVal =
2463                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2464           } else {
2465             StoreVal = DAG.getUNDEF(ExtendedVT);
2466           }
2467           Ops.push_back(StoreVal);
2468 
2469           if (i + 3 < NumElts) {
2470             StoreVal = OutVals[i + 3];
2471             if (NeedExtend)
2472               StoreVal =
2473                   DAG.getNode(ISD::ZERO_EXTEND, dl, ExtendedVT, StoreVal);
2474           } else {
2475             StoreVal = DAG.getUNDEF(ExtendedVT);
2476           }
2477           Ops.push_back(StoreVal);
2478         }
2479 
2480         // Chain = DAG.getNode(Opc, dl, MVT::Other, &Ops[0], Ops.size());
2481         Chain =
2482             DAG.getMemIntrinsicNode(Opc, dl, DAG.getVTList(MVT::Other), Ops,
2483                                     EltVT, MachinePointerInfo());
2484         Offset += PerStoreOffset;
2485       }
2486     }
2487   } else {
2488     SmallVector<EVT, 16> ValVTs;
2489     SmallVector<uint64_t, 16> Offsets;
2490     ComputePTXValueVTs(*this, DAG.getDataLayout(), RetTy, ValVTs, &Offsets, 0);
2491     assert(ValVTs.size() == OutVals.size() && "Bad return value decomposition");
2492 
2493     for (unsigned i = 0, e = Outs.size(); i != e; ++i) {
2494       SDValue theVal = OutVals[i];
2495       EVT TheValType = theVal.getValueType();
2496       unsigned numElems = 1;
2497       if (TheValType.isVector())
2498         numElems = TheValType.getVectorNumElements();
2499       for (unsigned j = 0, je = numElems; j != je; ++j) {
2500         SDValue TmpVal = theVal;
2501         if (TheValType.isVector())
2502           TmpVal = DAG.getNode(ISD::EXTRACT_VECTOR_ELT, dl,
2503                                TheValType.getVectorElementType(), TmpVal,
2504                                DAG.getIntPtrConstant(j, dl));
2505         EVT TheStoreType = ValVTs[i];
2506         if (RetTy->isIntegerTy() && TD.getTypeAllocSizeInBits(RetTy) < 32) {
2507           // The following zero-extension is for integer types only, and
2508           // specifically not for aggregates.
2509           TmpVal = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i32, TmpVal);
2510           TheStoreType = MVT::i32;
2511         }
2512         else if (TmpVal.getValueType().getSizeInBits() < 16)
2513           TmpVal = DAG.getNode(ISD::ANY_EXTEND, dl, MVT::i16, TmpVal);
2514 
2515         SDValue Ops[] = {
2516           Chain,
2517           DAG.getConstant(Offsets[i], dl, MVT::i32),
2518           TmpVal };
2519         Chain = DAG.getMemIntrinsicNode(NVPTXISD::StoreRetval, dl,
2520                                         DAG.getVTList(MVT::Other), Ops,
2521                                         TheStoreType,
2522                                         MachinePointerInfo());
2523       }
2524     }
2525   }
2526 
2527   return DAG.getNode(NVPTXISD::RET_FLAG, dl, MVT::Other, Chain);
2528 }
2529 
2530 
2531 void NVPTXTargetLowering::LowerAsmOperandForConstraint(
2532     SDValue Op, std::string &Constraint, std::vector<SDValue> &Ops,
2533     SelectionDAG &DAG) const {
2534   if (Constraint.length() > 1)
2535     return;
2536   else
2537     TargetLowering::LowerAsmOperandForConstraint(Op, Constraint, Ops, DAG);
2538 }
2539 
2540 static unsigned getOpcForTextureInstr(unsigned Intrinsic) {
2541   switch (Intrinsic) {
2542   default:
2543     return 0;
2544 
2545   case Intrinsic::nvvm_tex_1d_v4f32_s32:
2546     return NVPTXISD::Tex1DFloatS32;
2547   case Intrinsic::nvvm_tex_1d_v4f32_f32:
2548     return NVPTXISD::Tex1DFloatFloat;
2549   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
2550     return NVPTXISD::Tex1DFloatFloatLevel;
2551   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
2552     return NVPTXISD::Tex1DFloatFloatGrad;
2553   case Intrinsic::nvvm_tex_1d_v4s32_s32:
2554     return NVPTXISD::Tex1DS32S32;
2555   case Intrinsic::nvvm_tex_1d_v4s32_f32:
2556     return NVPTXISD::Tex1DS32Float;
2557   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
2558     return NVPTXISD::Tex1DS32FloatLevel;
2559   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
2560     return NVPTXISD::Tex1DS32FloatGrad;
2561   case Intrinsic::nvvm_tex_1d_v4u32_s32:
2562     return NVPTXISD::Tex1DU32S32;
2563   case Intrinsic::nvvm_tex_1d_v4u32_f32:
2564     return NVPTXISD::Tex1DU32Float;
2565   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
2566     return NVPTXISD::Tex1DU32FloatLevel;
2567   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
2568     return NVPTXISD::Tex1DU32FloatGrad;
2569 
2570   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
2571     return NVPTXISD::Tex1DArrayFloatS32;
2572   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
2573     return NVPTXISD::Tex1DArrayFloatFloat;
2574   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
2575     return NVPTXISD::Tex1DArrayFloatFloatLevel;
2576   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
2577     return NVPTXISD::Tex1DArrayFloatFloatGrad;
2578   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
2579     return NVPTXISD::Tex1DArrayS32S32;
2580   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
2581     return NVPTXISD::Tex1DArrayS32Float;
2582   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
2583     return NVPTXISD::Tex1DArrayS32FloatLevel;
2584   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
2585     return NVPTXISD::Tex1DArrayS32FloatGrad;
2586   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
2587     return NVPTXISD::Tex1DArrayU32S32;
2588   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
2589     return NVPTXISD::Tex1DArrayU32Float;
2590   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
2591     return NVPTXISD::Tex1DArrayU32FloatLevel;
2592   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
2593     return NVPTXISD::Tex1DArrayU32FloatGrad;
2594 
2595   case Intrinsic::nvvm_tex_2d_v4f32_s32:
2596     return NVPTXISD::Tex2DFloatS32;
2597   case Intrinsic::nvvm_tex_2d_v4f32_f32:
2598     return NVPTXISD::Tex2DFloatFloat;
2599   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
2600     return NVPTXISD::Tex2DFloatFloatLevel;
2601   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
2602     return NVPTXISD::Tex2DFloatFloatGrad;
2603   case Intrinsic::nvvm_tex_2d_v4s32_s32:
2604     return NVPTXISD::Tex2DS32S32;
2605   case Intrinsic::nvvm_tex_2d_v4s32_f32:
2606     return NVPTXISD::Tex2DS32Float;
2607   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
2608     return NVPTXISD::Tex2DS32FloatLevel;
2609   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
2610     return NVPTXISD::Tex2DS32FloatGrad;
2611   case Intrinsic::nvvm_tex_2d_v4u32_s32:
2612     return NVPTXISD::Tex2DU32S32;
2613   case Intrinsic::nvvm_tex_2d_v4u32_f32:
2614     return NVPTXISD::Tex2DU32Float;
2615   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
2616     return NVPTXISD::Tex2DU32FloatLevel;
2617   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
2618     return NVPTXISD::Tex2DU32FloatGrad;
2619 
2620   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
2621     return NVPTXISD::Tex2DArrayFloatS32;
2622   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
2623     return NVPTXISD::Tex2DArrayFloatFloat;
2624   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
2625     return NVPTXISD::Tex2DArrayFloatFloatLevel;
2626   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
2627     return NVPTXISD::Tex2DArrayFloatFloatGrad;
2628   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
2629     return NVPTXISD::Tex2DArrayS32S32;
2630   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
2631     return NVPTXISD::Tex2DArrayS32Float;
2632   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
2633     return NVPTXISD::Tex2DArrayS32FloatLevel;
2634   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
2635     return NVPTXISD::Tex2DArrayS32FloatGrad;
2636   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
2637     return NVPTXISD::Tex2DArrayU32S32;
2638   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
2639     return NVPTXISD::Tex2DArrayU32Float;
2640   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
2641     return NVPTXISD::Tex2DArrayU32FloatLevel;
2642   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
2643     return NVPTXISD::Tex2DArrayU32FloatGrad;
2644 
2645   case Intrinsic::nvvm_tex_3d_v4f32_s32:
2646     return NVPTXISD::Tex3DFloatS32;
2647   case Intrinsic::nvvm_tex_3d_v4f32_f32:
2648     return NVPTXISD::Tex3DFloatFloat;
2649   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
2650     return NVPTXISD::Tex3DFloatFloatLevel;
2651   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
2652     return NVPTXISD::Tex3DFloatFloatGrad;
2653   case Intrinsic::nvvm_tex_3d_v4s32_s32:
2654     return NVPTXISD::Tex3DS32S32;
2655   case Intrinsic::nvvm_tex_3d_v4s32_f32:
2656     return NVPTXISD::Tex3DS32Float;
2657   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
2658     return NVPTXISD::Tex3DS32FloatLevel;
2659   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
2660     return NVPTXISD::Tex3DS32FloatGrad;
2661   case Intrinsic::nvvm_tex_3d_v4u32_s32:
2662     return NVPTXISD::Tex3DU32S32;
2663   case Intrinsic::nvvm_tex_3d_v4u32_f32:
2664     return NVPTXISD::Tex3DU32Float;
2665   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
2666     return NVPTXISD::Tex3DU32FloatLevel;
2667   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
2668     return NVPTXISD::Tex3DU32FloatGrad;
2669 
2670   case Intrinsic::nvvm_tex_cube_v4f32_f32:
2671     return NVPTXISD::TexCubeFloatFloat;
2672   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
2673     return NVPTXISD::TexCubeFloatFloatLevel;
2674   case Intrinsic::nvvm_tex_cube_v4s32_f32:
2675     return NVPTXISD::TexCubeS32Float;
2676   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
2677     return NVPTXISD::TexCubeS32FloatLevel;
2678   case Intrinsic::nvvm_tex_cube_v4u32_f32:
2679     return NVPTXISD::TexCubeU32Float;
2680   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
2681     return NVPTXISD::TexCubeU32FloatLevel;
2682 
2683   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
2684     return NVPTXISD::TexCubeArrayFloatFloat;
2685   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
2686     return NVPTXISD::TexCubeArrayFloatFloatLevel;
2687   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
2688     return NVPTXISD::TexCubeArrayS32Float;
2689   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
2690     return NVPTXISD::TexCubeArrayS32FloatLevel;
2691   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
2692     return NVPTXISD::TexCubeArrayU32Float;
2693   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
2694     return NVPTXISD::TexCubeArrayU32FloatLevel;
2695 
2696   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
2697     return NVPTXISD::Tld4R2DFloatFloat;
2698   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
2699     return NVPTXISD::Tld4G2DFloatFloat;
2700   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
2701     return NVPTXISD::Tld4B2DFloatFloat;
2702   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
2703     return NVPTXISD::Tld4A2DFloatFloat;
2704   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
2705     return NVPTXISD::Tld4R2DS64Float;
2706   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
2707     return NVPTXISD::Tld4G2DS64Float;
2708   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
2709     return NVPTXISD::Tld4B2DS64Float;
2710   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
2711     return NVPTXISD::Tld4A2DS64Float;
2712   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
2713     return NVPTXISD::Tld4R2DU64Float;
2714   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
2715     return NVPTXISD::Tld4G2DU64Float;
2716   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
2717     return NVPTXISD::Tld4B2DU64Float;
2718   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
2719     return NVPTXISD::Tld4A2DU64Float;
2720 
2721   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
2722     return NVPTXISD::TexUnified1DFloatS32;
2723   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
2724     return NVPTXISD::TexUnified1DFloatFloat;
2725   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
2726     return NVPTXISD::TexUnified1DFloatFloatLevel;
2727   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
2728     return NVPTXISD::TexUnified1DFloatFloatGrad;
2729   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
2730     return NVPTXISD::TexUnified1DS32S32;
2731   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
2732     return NVPTXISD::TexUnified1DS32Float;
2733   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
2734     return NVPTXISD::TexUnified1DS32FloatLevel;
2735   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
2736     return NVPTXISD::TexUnified1DS32FloatGrad;
2737   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
2738     return NVPTXISD::TexUnified1DU32S32;
2739   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
2740     return NVPTXISD::TexUnified1DU32Float;
2741   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
2742     return NVPTXISD::TexUnified1DU32FloatLevel;
2743   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
2744     return NVPTXISD::TexUnified1DU32FloatGrad;
2745 
2746   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
2747     return NVPTXISD::TexUnified1DArrayFloatS32;
2748   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
2749     return NVPTXISD::TexUnified1DArrayFloatFloat;
2750   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
2751     return NVPTXISD::TexUnified1DArrayFloatFloatLevel;
2752   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
2753     return NVPTXISD::TexUnified1DArrayFloatFloatGrad;
2754   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
2755     return NVPTXISD::TexUnified1DArrayS32S32;
2756   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
2757     return NVPTXISD::TexUnified1DArrayS32Float;
2758   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
2759     return NVPTXISD::TexUnified1DArrayS32FloatLevel;
2760   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
2761     return NVPTXISD::TexUnified1DArrayS32FloatGrad;
2762   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
2763     return NVPTXISD::TexUnified1DArrayU32S32;
2764   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
2765     return NVPTXISD::TexUnified1DArrayU32Float;
2766   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
2767     return NVPTXISD::TexUnified1DArrayU32FloatLevel;
2768   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
2769     return NVPTXISD::TexUnified1DArrayU32FloatGrad;
2770 
2771   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
2772     return NVPTXISD::TexUnified2DFloatS32;
2773   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
2774     return NVPTXISD::TexUnified2DFloatFloat;
2775   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
2776     return NVPTXISD::TexUnified2DFloatFloatLevel;
2777   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
2778     return NVPTXISD::TexUnified2DFloatFloatGrad;
2779   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
2780     return NVPTXISD::TexUnified2DS32S32;
2781   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
2782     return NVPTXISD::TexUnified2DS32Float;
2783   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
2784     return NVPTXISD::TexUnified2DS32FloatLevel;
2785   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
2786     return NVPTXISD::TexUnified2DS32FloatGrad;
2787   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
2788     return NVPTXISD::TexUnified2DU32S32;
2789   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
2790     return NVPTXISD::TexUnified2DU32Float;
2791   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
2792     return NVPTXISD::TexUnified2DU32FloatLevel;
2793   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
2794     return NVPTXISD::TexUnified2DU32FloatGrad;
2795 
2796   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
2797     return NVPTXISD::TexUnified2DArrayFloatS32;
2798   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
2799     return NVPTXISD::TexUnified2DArrayFloatFloat;
2800   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
2801     return NVPTXISD::TexUnified2DArrayFloatFloatLevel;
2802   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
2803     return NVPTXISD::TexUnified2DArrayFloatFloatGrad;
2804   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
2805     return NVPTXISD::TexUnified2DArrayS32S32;
2806   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
2807     return NVPTXISD::TexUnified2DArrayS32Float;
2808   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
2809     return NVPTXISD::TexUnified2DArrayS32FloatLevel;
2810   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
2811     return NVPTXISD::TexUnified2DArrayS32FloatGrad;
2812   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
2813     return NVPTXISD::TexUnified2DArrayU32S32;
2814   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
2815     return NVPTXISD::TexUnified2DArrayU32Float;
2816   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
2817     return NVPTXISD::TexUnified2DArrayU32FloatLevel;
2818   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
2819     return NVPTXISD::TexUnified2DArrayU32FloatGrad;
2820 
2821   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
2822     return NVPTXISD::TexUnified3DFloatS32;
2823   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
2824     return NVPTXISD::TexUnified3DFloatFloat;
2825   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
2826     return NVPTXISD::TexUnified3DFloatFloatLevel;
2827   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
2828     return NVPTXISD::TexUnified3DFloatFloatGrad;
2829   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
2830     return NVPTXISD::TexUnified3DS32S32;
2831   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
2832     return NVPTXISD::TexUnified3DS32Float;
2833   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
2834     return NVPTXISD::TexUnified3DS32FloatLevel;
2835   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
2836     return NVPTXISD::TexUnified3DS32FloatGrad;
2837   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
2838     return NVPTXISD::TexUnified3DU32S32;
2839   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
2840     return NVPTXISD::TexUnified3DU32Float;
2841   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
2842     return NVPTXISD::TexUnified3DU32FloatLevel;
2843   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
2844     return NVPTXISD::TexUnified3DU32FloatGrad;
2845 
2846   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
2847     return NVPTXISD::TexUnifiedCubeFloatFloat;
2848   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
2849     return NVPTXISD::TexUnifiedCubeFloatFloatLevel;
2850   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
2851     return NVPTXISD::TexUnifiedCubeS32Float;
2852   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
2853     return NVPTXISD::TexUnifiedCubeS32FloatLevel;
2854   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
2855     return NVPTXISD::TexUnifiedCubeU32Float;
2856   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
2857     return NVPTXISD::TexUnifiedCubeU32FloatLevel;
2858 
2859   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
2860     return NVPTXISD::TexUnifiedCubeArrayFloatFloat;
2861   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
2862     return NVPTXISD::TexUnifiedCubeArrayFloatFloatLevel;
2863   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
2864     return NVPTXISD::TexUnifiedCubeArrayS32Float;
2865   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
2866     return NVPTXISD::TexUnifiedCubeArrayS32FloatLevel;
2867   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
2868     return NVPTXISD::TexUnifiedCubeArrayU32Float;
2869   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
2870     return NVPTXISD::TexUnifiedCubeArrayU32FloatLevel;
2871 
2872   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
2873     return NVPTXISD::Tld4UnifiedR2DFloatFloat;
2874   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
2875     return NVPTXISD::Tld4UnifiedG2DFloatFloat;
2876   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
2877     return NVPTXISD::Tld4UnifiedB2DFloatFloat;
2878   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32:
2879     return NVPTXISD::Tld4UnifiedA2DFloatFloat;
2880   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
2881     return NVPTXISD::Tld4UnifiedR2DS64Float;
2882   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
2883     return NVPTXISD::Tld4UnifiedG2DS64Float;
2884   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
2885     return NVPTXISD::Tld4UnifiedB2DS64Float;
2886   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
2887     return NVPTXISD::Tld4UnifiedA2DS64Float;
2888   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
2889     return NVPTXISD::Tld4UnifiedR2DU64Float;
2890   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
2891     return NVPTXISD::Tld4UnifiedG2DU64Float;
2892   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
2893     return NVPTXISD::Tld4UnifiedB2DU64Float;
2894   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32:
2895     return NVPTXISD::Tld4UnifiedA2DU64Float;
2896   }
2897 }
2898 
2899 static unsigned getOpcForSurfaceInstr(unsigned Intrinsic) {
2900   switch (Intrinsic) {
2901   default:
2902     return 0;
2903   case Intrinsic::nvvm_suld_1d_i8_clamp:
2904     return NVPTXISD::Suld1DI8Clamp;
2905   case Intrinsic::nvvm_suld_1d_i16_clamp:
2906     return NVPTXISD::Suld1DI16Clamp;
2907   case Intrinsic::nvvm_suld_1d_i32_clamp:
2908     return NVPTXISD::Suld1DI32Clamp;
2909   case Intrinsic::nvvm_suld_1d_i64_clamp:
2910     return NVPTXISD::Suld1DI64Clamp;
2911   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
2912     return NVPTXISD::Suld1DV2I8Clamp;
2913   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
2914     return NVPTXISD::Suld1DV2I16Clamp;
2915   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
2916     return NVPTXISD::Suld1DV2I32Clamp;
2917   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
2918     return NVPTXISD::Suld1DV2I64Clamp;
2919   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
2920     return NVPTXISD::Suld1DV4I8Clamp;
2921   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
2922     return NVPTXISD::Suld1DV4I16Clamp;
2923   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
2924     return NVPTXISD::Suld1DV4I32Clamp;
2925   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
2926     return NVPTXISD::Suld1DArrayI8Clamp;
2927   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
2928     return NVPTXISD::Suld1DArrayI16Clamp;
2929   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
2930     return NVPTXISD::Suld1DArrayI32Clamp;
2931   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
2932     return NVPTXISD::Suld1DArrayI64Clamp;
2933   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
2934     return NVPTXISD::Suld1DArrayV2I8Clamp;
2935   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
2936     return NVPTXISD::Suld1DArrayV2I16Clamp;
2937   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
2938     return NVPTXISD::Suld1DArrayV2I32Clamp;
2939   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
2940     return NVPTXISD::Suld1DArrayV2I64Clamp;
2941   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
2942     return NVPTXISD::Suld1DArrayV4I8Clamp;
2943   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
2944     return NVPTXISD::Suld1DArrayV4I16Clamp;
2945   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
2946     return NVPTXISD::Suld1DArrayV4I32Clamp;
2947   case Intrinsic::nvvm_suld_2d_i8_clamp:
2948     return NVPTXISD::Suld2DI8Clamp;
2949   case Intrinsic::nvvm_suld_2d_i16_clamp:
2950     return NVPTXISD::Suld2DI16Clamp;
2951   case Intrinsic::nvvm_suld_2d_i32_clamp:
2952     return NVPTXISD::Suld2DI32Clamp;
2953   case Intrinsic::nvvm_suld_2d_i64_clamp:
2954     return NVPTXISD::Suld2DI64Clamp;
2955   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
2956     return NVPTXISD::Suld2DV2I8Clamp;
2957   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
2958     return NVPTXISD::Suld2DV2I16Clamp;
2959   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
2960     return NVPTXISD::Suld2DV2I32Clamp;
2961   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
2962     return NVPTXISD::Suld2DV2I64Clamp;
2963   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
2964     return NVPTXISD::Suld2DV4I8Clamp;
2965   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
2966     return NVPTXISD::Suld2DV4I16Clamp;
2967   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
2968     return NVPTXISD::Suld2DV4I32Clamp;
2969   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
2970     return NVPTXISD::Suld2DArrayI8Clamp;
2971   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
2972     return NVPTXISD::Suld2DArrayI16Clamp;
2973   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
2974     return NVPTXISD::Suld2DArrayI32Clamp;
2975   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
2976     return NVPTXISD::Suld2DArrayI64Clamp;
2977   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
2978     return NVPTXISD::Suld2DArrayV2I8Clamp;
2979   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
2980     return NVPTXISD::Suld2DArrayV2I16Clamp;
2981   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
2982     return NVPTXISD::Suld2DArrayV2I32Clamp;
2983   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
2984     return NVPTXISD::Suld2DArrayV2I64Clamp;
2985   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
2986     return NVPTXISD::Suld2DArrayV4I8Clamp;
2987   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
2988     return NVPTXISD::Suld2DArrayV4I16Clamp;
2989   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
2990     return NVPTXISD::Suld2DArrayV4I32Clamp;
2991   case Intrinsic::nvvm_suld_3d_i8_clamp:
2992     return NVPTXISD::Suld3DI8Clamp;
2993   case Intrinsic::nvvm_suld_3d_i16_clamp:
2994     return NVPTXISD::Suld3DI16Clamp;
2995   case Intrinsic::nvvm_suld_3d_i32_clamp:
2996     return NVPTXISD::Suld3DI32Clamp;
2997   case Intrinsic::nvvm_suld_3d_i64_clamp:
2998     return NVPTXISD::Suld3DI64Clamp;
2999   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3000     return NVPTXISD::Suld3DV2I8Clamp;
3001   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3002     return NVPTXISD::Suld3DV2I16Clamp;
3003   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3004     return NVPTXISD::Suld3DV2I32Clamp;
3005   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3006     return NVPTXISD::Suld3DV2I64Clamp;
3007   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3008     return NVPTXISD::Suld3DV4I8Clamp;
3009   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3010     return NVPTXISD::Suld3DV4I16Clamp;
3011   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3012     return NVPTXISD::Suld3DV4I32Clamp;
3013   case Intrinsic::nvvm_suld_1d_i8_trap:
3014     return NVPTXISD::Suld1DI8Trap;
3015   case Intrinsic::nvvm_suld_1d_i16_trap:
3016     return NVPTXISD::Suld1DI16Trap;
3017   case Intrinsic::nvvm_suld_1d_i32_trap:
3018     return NVPTXISD::Suld1DI32Trap;
3019   case Intrinsic::nvvm_suld_1d_i64_trap:
3020     return NVPTXISD::Suld1DI64Trap;
3021   case Intrinsic::nvvm_suld_1d_v2i8_trap:
3022     return NVPTXISD::Suld1DV2I8Trap;
3023   case Intrinsic::nvvm_suld_1d_v2i16_trap:
3024     return NVPTXISD::Suld1DV2I16Trap;
3025   case Intrinsic::nvvm_suld_1d_v2i32_trap:
3026     return NVPTXISD::Suld1DV2I32Trap;
3027   case Intrinsic::nvvm_suld_1d_v2i64_trap:
3028     return NVPTXISD::Suld1DV2I64Trap;
3029   case Intrinsic::nvvm_suld_1d_v4i8_trap:
3030     return NVPTXISD::Suld1DV4I8Trap;
3031   case Intrinsic::nvvm_suld_1d_v4i16_trap:
3032     return NVPTXISD::Suld1DV4I16Trap;
3033   case Intrinsic::nvvm_suld_1d_v4i32_trap:
3034     return NVPTXISD::Suld1DV4I32Trap;
3035   case Intrinsic::nvvm_suld_1d_array_i8_trap:
3036     return NVPTXISD::Suld1DArrayI8Trap;
3037   case Intrinsic::nvvm_suld_1d_array_i16_trap:
3038     return NVPTXISD::Suld1DArrayI16Trap;
3039   case Intrinsic::nvvm_suld_1d_array_i32_trap:
3040     return NVPTXISD::Suld1DArrayI32Trap;
3041   case Intrinsic::nvvm_suld_1d_array_i64_trap:
3042     return NVPTXISD::Suld1DArrayI64Trap;
3043   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3044     return NVPTXISD::Suld1DArrayV2I8Trap;
3045   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3046     return NVPTXISD::Suld1DArrayV2I16Trap;
3047   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3048     return NVPTXISD::Suld1DArrayV2I32Trap;
3049   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3050     return NVPTXISD::Suld1DArrayV2I64Trap;
3051   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3052     return NVPTXISD::Suld1DArrayV4I8Trap;
3053   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3054     return NVPTXISD::Suld1DArrayV4I16Trap;
3055   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3056     return NVPTXISD::Suld1DArrayV4I32Trap;
3057   case Intrinsic::nvvm_suld_2d_i8_trap:
3058     return NVPTXISD::Suld2DI8Trap;
3059   case Intrinsic::nvvm_suld_2d_i16_trap:
3060     return NVPTXISD::Suld2DI16Trap;
3061   case Intrinsic::nvvm_suld_2d_i32_trap:
3062     return NVPTXISD::Suld2DI32Trap;
3063   case Intrinsic::nvvm_suld_2d_i64_trap:
3064     return NVPTXISD::Suld2DI64Trap;
3065   case Intrinsic::nvvm_suld_2d_v2i8_trap:
3066     return NVPTXISD::Suld2DV2I8Trap;
3067   case Intrinsic::nvvm_suld_2d_v2i16_trap:
3068     return NVPTXISD::Suld2DV2I16Trap;
3069   case Intrinsic::nvvm_suld_2d_v2i32_trap:
3070     return NVPTXISD::Suld2DV2I32Trap;
3071   case Intrinsic::nvvm_suld_2d_v2i64_trap:
3072     return NVPTXISD::Suld2DV2I64Trap;
3073   case Intrinsic::nvvm_suld_2d_v4i8_trap:
3074     return NVPTXISD::Suld2DV4I8Trap;
3075   case Intrinsic::nvvm_suld_2d_v4i16_trap:
3076     return NVPTXISD::Suld2DV4I16Trap;
3077   case Intrinsic::nvvm_suld_2d_v4i32_trap:
3078     return NVPTXISD::Suld2DV4I32Trap;
3079   case Intrinsic::nvvm_suld_2d_array_i8_trap:
3080     return NVPTXISD::Suld2DArrayI8Trap;
3081   case Intrinsic::nvvm_suld_2d_array_i16_trap:
3082     return NVPTXISD::Suld2DArrayI16Trap;
3083   case Intrinsic::nvvm_suld_2d_array_i32_trap:
3084     return NVPTXISD::Suld2DArrayI32Trap;
3085   case Intrinsic::nvvm_suld_2d_array_i64_trap:
3086     return NVPTXISD::Suld2DArrayI64Trap;
3087   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3088     return NVPTXISD::Suld2DArrayV2I8Trap;
3089   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3090     return NVPTXISD::Suld2DArrayV2I16Trap;
3091   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3092     return NVPTXISD::Suld2DArrayV2I32Trap;
3093   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3094     return NVPTXISD::Suld2DArrayV2I64Trap;
3095   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3096     return NVPTXISD::Suld2DArrayV4I8Trap;
3097   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3098     return NVPTXISD::Suld2DArrayV4I16Trap;
3099   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3100     return NVPTXISD::Suld2DArrayV4I32Trap;
3101   case Intrinsic::nvvm_suld_3d_i8_trap:
3102     return NVPTXISD::Suld3DI8Trap;
3103   case Intrinsic::nvvm_suld_3d_i16_trap:
3104     return NVPTXISD::Suld3DI16Trap;
3105   case Intrinsic::nvvm_suld_3d_i32_trap:
3106     return NVPTXISD::Suld3DI32Trap;
3107   case Intrinsic::nvvm_suld_3d_i64_trap:
3108     return NVPTXISD::Suld3DI64Trap;
3109   case Intrinsic::nvvm_suld_3d_v2i8_trap:
3110     return NVPTXISD::Suld3DV2I8Trap;
3111   case Intrinsic::nvvm_suld_3d_v2i16_trap:
3112     return NVPTXISD::Suld3DV2I16Trap;
3113   case Intrinsic::nvvm_suld_3d_v2i32_trap:
3114     return NVPTXISD::Suld3DV2I32Trap;
3115   case Intrinsic::nvvm_suld_3d_v2i64_trap:
3116     return NVPTXISD::Suld3DV2I64Trap;
3117   case Intrinsic::nvvm_suld_3d_v4i8_trap:
3118     return NVPTXISD::Suld3DV4I8Trap;
3119   case Intrinsic::nvvm_suld_3d_v4i16_trap:
3120     return NVPTXISD::Suld3DV4I16Trap;
3121   case Intrinsic::nvvm_suld_3d_v4i32_trap:
3122     return NVPTXISD::Suld3DV4I32Trap;
3123   case Intrinsic::nvvm_suld_1d_i8_zero:
3124     return NVPTXISD::Suld1DI8Zero;
3125   case Intrinsic::nvvm_suld_1d_i16_zero:
3126     return NVPTXISD::Suld1DI16Zero;
3127   case Intrinsic::nvvm_suld_1d_i32_zero:
3128     return NVPTXISD::Suld1DI32Zero;
3129   case Intrinsic::nvvm_suld_1d_i64_zero:
3130     return NVPTXISD::Suld1DI64Zero;
3131   case Intrinsic::nvvm_suld_1d_v2i8_zero:
3132     return NVPTXISD::Suld1DV2I8Zero;
3133   case Intrinsic::nvvm_suld_1d_v2i16_zero:
3134     return NVPTXISD::Suld1DV2I16Zero;
3135   case Intrinsic::nvvm_suld_1d_v2i32_zero:
3136     return NVPTXISD::Suld1DV2I32Zero;
3137   case Intrinsic::nvvm_suld_1d_v2i64_zero:
3138     return NVPTXISD::Suld1DV2I64Zero;
3139   case Intrinsic::nvvm_suld_1d_v4i8_zero:
3140     return NVPTXISD::Suld1DV4I8Zero;
3141   case Intrinsic::nvvm_suld_1d_v4i16_zero:
3142     return NVPTXISD::Suld1DV4I16Zero;
3143   case Intrinsic::nvvm_suld_1d_v4i32_zero:
3144     return NVPTXISD::Suld1DV4I32Zero;
3145   case Intrinsic::nvvm_suld_1d_array_i8_zero:
3146     return NVPTXISD::Suld1DArrayI8Zero;
3147   case Intrinsic::nvvm_suld_1d_array_i16_zero:
3148     return NVPTXISD::Suld1DArrayI16Zero;
3149   case Intrinsic::nvvm_suld_1d_array_i32_zero:
3150     return NVPTXISD::Suld1DArrayI32Zero;
3151   case Intrinsic::nvvm_suld_1d_array_i64_zero:
3152     return NVPTXISD::Suld1DArrayI64Zero;
3153   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3154     return NVPTXISD::Suld1DArrayV2I8Zero;
3155   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3156     return NVPTXISD::Suld1DArrayV2I16Zero;
3157   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3158     return NVPTXISD::Suld1DArrayV2I32Zero;
3159   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3160     return NVPTXISD::Suld1DArrayV2I64Zero;
3161   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3162     return NVPTXISD::Suld1DArrayV4I8Zero;
3163   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3164     return NVPTXISD::Suld1DArrayV4I16Zero;
3165   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3166     return NVPTXISD::Suld1DArrayV4I32Zero;
3167   case Intrinsic::nvvm_suld_2d_i8_zero:
3168     return NVPTXISD::Suld2DI8Zero;
3169   case Intrinsic::nvvm_suld_2d_i16_zero:
3170     return NVPTXISD::Suld2DI16Zero;
3171   case Intrinsic::nvvm_suld_2d_i32_zero:
3172     return NVPTXISD::Suld2DI32Zero;
3173   case Intrinsic::nvvm_suld_2d_i64_zero:
3174     return NVPTXISD::Suld2DI64Zero;
3175   case Intrinsic::nvvm_suld_2d_v2i8_zero:
3176     return NVPTXISD::Suld2DV2I8Zero;
3177   case Intrinsic::nvvm_suld_2d_v2i16_zero:
3178     return NVPTXISD::Suld2DV2I16Zero;
3179   case Intrinsic::nvvm_suld_2d_v2i32_zero:
3180     return NVPTXISD::Suld2DV2I32Zero;
3181   case Intrinsic::nvvm_suld_2d_v2i64_zero:
3182     return NVPTXISD::Suld2DV2I64Zero;
3183   case Intrinsic::nvvm_suld_2d_v4i8_zero:
3184     return NVPTXISD::Suld2DV4I8Zero;
3185   case Intrinsic::nvvm_suld_2d_v4i16_zero:
3186     return NVPTXISD::Suld2DV4I16Zero;
3187   case Intrinsic::nvvm_suld_2d_v4i32_zero:
3188     return NVPTXISD::Suld2DV4I32Zero;
3189   case Intrinsic::nvvm_suld_2d_array_i8_zero:
3190     return NVPTXISD::Suld2DArrayI8Zero;
3191   case Intrinsic::nvvm_suld_2d_array_i16_zero:
3192     return NVPTXISD::Suld2DArrayI16Zero;
3193   case Intrinsic::nvvm_suld_2d_array_i32_zero:
3194     return NVPTXISD::Suld2DArrayI32Zero;
3195   case Intrinsic::nvvm_suld_2d_array_i64_zero:
3196     return NVPTXISD::Suld2DArrayI64Zero;
3197   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3198     return NVPTXISD::Suld2DArrayV2I8Zero;
3199   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3200     return NVPTXISD::Suld2DArrayV2I16Zero;
3201   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3202     return NVPTXISD::Suld2DArrayV2I32Zero;
3203   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3204     return NVPTXISD::Suld2DArrayV2I64Zero;
3205   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3206     return NVPTXISD::Suld2DArrayV4I8Zero;
3207   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3208     return NVPTXISD::Suld2DArrayV4I16Zero;
3209   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3210     return NVPTXISD::Suld2DArrayV4I32Zero;
3211   case Intrinsic::nvvm_suld_3d_i8_zero:
3212     return NVPTXISD::Suld3DI8Zero;
3213   case Intrinsic::nvvm_suld_3d_i16_zero:
3214     return NVPTXISD::Suld3DI16Zero;
3215   case Intrinsic::nvvm_suld_3d_i32_zero:
3216     return NVPTXISD::Suld3DI32Zero;
3217   case Intrinsic::nvvm_suld_3d_i64_zero:
3218     return NVPTXISD::Suld3DI64Zero;
3219   case Intrinsic::nvvm_suld_3d_v2i8_zero:
3220     return NVPTXISD::Suld3DV2I8Zero;
3221   case Intrinsic::nvvm_suld_3d_v2i16_zero:
3222     return NVPTXISD::Suld3DV2I16Zero;
3223   case Intrinsic::nvvm_suld_3d_v2i32_zero:
3224     return NVPTXISD::Suld3DV2I32Zero;
3225   case Intrinsic::nvvm_suld_3d_v2i64_zero:
3226     return NVPTXISD::Suld3DV2I64Zero;
3227   case Intrinsic::nvvm_suld_3d_v4i8_zero:
3228     return NVPTXISD::Suld3DV4I8Zero;
3229   case Intrinsic::nvvm_suld_3d_v4i16_zero:
3230     return NVPTXISD::Suld3DV4I16Zero;
3231   case Intrinsic::nvvm_suld_3d_v4i32_zero:
3232     return NVPTXISD::Suld3DV4I32Zero;
3233   }
3234 }
3235 
3236 // llvm.ptx.memcpy.const and llvm.ptx.memmove.const need to be modeled as
3237 // TgtMemIntrinsic
3238 // because we need the information that is only available in the "Value" type
3239 // of destination
3240 // pointer. In particular, the address space information.
3241 bool NVPTXTargetLowering::getTgtMemIntrinsic(
3242     IntrinsicInfo &Info, const CallInst &I, unsigned Intrinsic) const {
3243   switch (Intrinsic) {
3244   default:
3245     return false;
3246 
3247   case Intrinsic::nvvm_atomic_load_add_f32:
3248     Info.opc = ISD::INTRINSIC_W_CHAIN;
3249     Info.memVT = MVT::f32;
3250     Info.ptrVal = I.getArgOperand(0);
3251     Info.offset = 0;
3252     Info.vol = 0;
3253     Info.readMem = true;
3254     Info.writeMem = true;
3255     Info.align = 0;
3256     return true;
3257 
3258   case Intrinsic::nvvm_atomic_load_inc_32:
3259   case Intrinsic::nvvm_atomic_load_dec_32:
3260     Info.opc = ISD::INTRINSIC_W_CHAIN;
3261     Info.memVT = MVT::i32;
3262     Info.ptrVal = I.getArgOperand(0);
3263     Info.offset = 0;
3264     Info.vol = 0;
3265     Info.readMem = true;
3266     Info.writeMem = true;
3267     Info.align = 0;
3268     return true;
3269 
3270   case Intrinsic::nvvm_ldu_global_i:
3271   case Intrinsic::nvvm_ldu_global_f:
3272   case Intrinsic::nvvm_ldu_global_p: {
3273     auto &DL = I.getModule()->getDataLayout();
3274     Info.opc = ISD::INTRINSIC_W_CHAIN;
3275     if (Intrinsic == Intrinsic::nvvm_ldu_global_i)
3276       Info.memVT = getValueType(DL, I.getType());
3277     else if(Intrinsic == Intrinsic::nvvm_ldu_global_p)
3278       Info.memVT = getPointerTy(DL);
3279     else
3280       Info.memVT = getValueType(DL, I.getType());
3281     Info.ptrVal = I.getArgOperand(0);
3282     Info.offset = 0;
3283     Info.vol = 0;
3284     Info.readMem = true;
3285     Info.writeMem = false;
3286     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3287 
3288     return true;
3289   }
3290   case Intrinsic::nvvm_ldg_global_i:
3291   case Intrinsic::nvvm_ldg_global_f:
3292   case Intrinsic::nvvm_ldg_global_p: {
3293     auto &DL = I.getModule()->getDataLayout();
3294 
3295     Info.opc = ISD::INTRINSIC_W_CHAIN;
3296     if (Intrinsic == Intrinsic::nvvm_ldg_global_i)
3297       Info.memVT = getValueType(DL, I.getType());
3298     else if(Intrinsic == Intrinsic::nvvm_ldg_global_p)
3299       Info.memVT = getPointerTy(DL);
3300     else
3301       Info.memVT = getValueType(DL, I.getType());
3302     Info.ptrVal = I.getArgOperand(0);
3303     Info.offset = 0;
3304     Info.vol = 0;
3305     Info.readMem = true;
3306     Info.writeMem = false;
3307     Info.align = cast<ConstantInt>(I.getArgOperand(1))->getZExtValue();
3308 
3309     return true;
3310   }
3311 
3312   case Intrinsic::nvvm_tex_1d_v4f32_s32:
3313   case Intrinsic::nvvm_tex_1d_v4f32_f32:
3314   case Intrinsic::nvvm_tex_1d_level_v4f32_f32:
3315   case Intrinsic::nvvm_tex_1d_grad_v4f32_f32:
3316   case Intrinsic::nvvm_tex_1d_array_v4f32_s32:
3317   case Intrinsic::nvvm_tex_1d_array_v4f32_f32:
3318   case Intrinsic::nvvm_tex_1d_array_level_v4f32_f32:
3319   case Intrinsic::nvvm_tex_1d_array_grad_v4f32_f32:
3320   case Intrinsic::nvvm_tex_2d_v4f32_s32:
3321   case Intrinsic::nvvm_tex_2d_v4f32_f32:
3322   case Intrinsic::nvvm_tex_2d_level_v4f32_f32:
3323   case Intrinsic::nvvm_tex_2d_grad_v4f32_f32:
3324   case Intrinsic::nvvm_tex_2d_array_v4f32_s32:
3325   case Intrinsic::nvvm_tex_2d_array_v4f32_f32:
3326   case Intrinsic::nvvm_tex_2d_array_level_v4f32_f32:
3327   case Intrinsic::nvvm_tex_2d_array_grad_v4f32_f32:
3328   case Intrinsic::nvvm_tex_3d_v4f32_s32:
3329   case Intrinsic::nvvm_tex_3d_v4f32_f32:
3330   case Intrinsic::nvvm_tex_3d_level_v4f32_f32:
3331   case Intrinsic::nvvm_tex_3d_grad_v4f32_f32:
3332   case Intrinsic::nvvm_tex_cube_v4f32_f32:
3333   case Intrinsic::nvvm_tex_cube_level_v4f32_f32:
3334   case Intrinsic::nvvm_tex_cube_array_v4f32_f32:
3335   case Intrinsic::nvvm_tex_cube_array_level_v4f32_f32:
3336   case Intrinsic::nvvm_tld4_r_2d_v4f32_f32:
3337   case Intrinsic::nvvm_tld4_g_2d_v4f32_f32:
3338   case Intrinsic::nvvm_tld4_b_2d_v4f32_f32:
3339   case Intrinsic::nvvm_tld4_a_2d_v4f32_f32:
3340   case Intrinsic::nvvm_tex_unified_1d_v4f32_s32:
3341   case Intrinsic::nvvm_tex_unified_1d_v4f32_f32:
3342   case Intrinsic::nvvm_tex_unified_1d_level_v4f32_f32:
3343   case Intrinsic::nvvm_tex_unified_1d_grad_v4f32_f32:
3344   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_s32:
3345   case Intrinsic::nvvm_tex_unified_1d_array_v4f32_f32:
3346   case Intrinsic::nvvm_tex_unified_1d_array_level_v4f32_f32:
3347   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4f32_f32:
3348   case Intrinsic::nvvm_tex_unified_2d_v4f32_s32:
3349   case Intrinsic::nvvm_tex_unified_2d_v4f32_f32:
3350   case Intrinsic::nvvm_tex_unified_2d_level_v4f32_f32:
3351   case Intrinsic::nvvm_tex_unified_2d_grad_v4f32_f32:
3352   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_s32:
3353   case Intrinsic::nvvm_tex_unified_2d_array_v4f32_f32:
3354   case Intrinsic::nvvm_tex_unified_2d_array_level_v4f32_f32:
3355   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4f32_f32:
3356   case Intrinsic::nvvm_tex_unified_3d_v4f32_s32:
3357   case Intrinsic::nvvm_tex_unified_3d_v4f32_f32:
3358   case Intrinsic::nvvm_tex_unified_3d_level_v4f32_f32:
3359   case Intrinsic::nvvm_tex_unified_3d_grad_v4f32_f32:
3360   case Intrinsic::nvvm_tex_unified_cube_v4f32_f32:
3361   case Intrinsic::nvvm_tex_unified_cube_level_v4f32_f32:
3362   case Intrinsic::nvvm_tex_unified_cube_array_v4f32_f32:
3363   case Intrinsic::nvvm_tex_unified_cube_array_level_v4f32_f32:
3364   case Intrinsic::nvvm_tld4_unified_r_2d_v4f32_f32:
3365   case Intrinsic::nvvm_tld4_unified_g_2d_v4f32_f32:
3366   case Intrinsic::nvvm_tld4_unified_b_2d_v4f32_f32:
3367   case Intrinsic::nvvm_tld4_unified_a_2d_v4f32_f32: {
3368     Info.opc = getOpcForTextureInstr(Intrinsic);
3369     Info.memVT = MVT::v4f32;
3370     Info.ptrVal = nullptr;
3371     Info.offset = 0;
3372     Info.vol = 0;
3373     Info.readMem = true;
3374     Info.writeMem = false;
3375     Info.align = 16;
3376     return true;
3377   }
3378   case Intrinsic::nvvm_tex_1d_v4s32_s32:
3379   case Intrinsic::nvvm_tex_1d_v4s32_f32:
3380   case Intrinsic::nvvm_tex_1d_level_v4s32_f32:
3381   case Intrinsic::nvvm_tex_1d_grad_v4s32_f32:
3382   case Intrinsic::nvvm_tex_1d_array_v4s32_s32:
3383   case Intrinsic::nvvm_tex_1d_array_v4s32_f32:
3384   case Intrinsic::nvvm_tex_1d_array_level_v4s32_f32:
3385   case Intrinsic::nvvm_tex_1d_array_grad_v4s32_f32:
3386   case Intrinsic::nvvm_tex_2d_v4s32_s32:
3387   case Intrinsic::nvvm_tex_2d_v4s32_f32:
3388   case Intrinsic::nvvm_tex_2d_level_v4s32_f32:
3389   case Intrinsic::nvvm_tex_2d_grad_v4s32_f32:
3390   case Intrinsic::nvvm_tex_2d_array_v4s32_s32:
3391   case Intrinsic::nvvm_tex_2d_array_v4s32_f32:
3392   case Intrinsic::nvvm_tex_2d_array_level_v4s32_f32:
3393   case Intrinsic::nvvm_tex_2d_array_grad_v4s32_f32:
3394   case Intrinsic::nvvm_tex_3d_v4s32_s32:
3395   case Intrinsic::nvvm_tex_3d_v4s32_f32:
3396   case Intrinsic::nvvm_tex_3d_level_v4s32_f32:
3397   case Intrinsic::nvvm_tex_3d_grad_v4s32_f32:
3398   case Intrinsic::nvvm_tex_cube_v4s32_f32:
3399   case Intrinsic::nvvm_tex_cube_level_v4s32_f32:
3400   case Intrinsic::nvvm_tex_cube_array_v4s32_f32:
3401   case Intrinsic::nvvm_tex_cube_array_level_v4s32_f32:
3402   case Intrinsic::nvvm_tex_cube_v4u32_f32:
3403   case Intrinsic::nvvm_tex_cube_level_v4u32_f32:
3404   case Intrinsic::nvvm_tex_cube_array_v4u32_f32:
3405   case Intrinsic::nvvm_tex_cube_array_level_v4u32_f32:
3406   case Intrinsic::nvvm_tex_1d_v4u32_s32:
3407   case Intrinsic::nvvm_tex_1d_v4u32_f32:
3408   case Intrinsic::nvvm_tex_1d_level_v4u32_f32:
3409   case Intrinsic::nvvm_tex_1d_grad_v4u32_f32:
3410   case Intrinsic::nvvm_tex_1d_array_v4u32_s32:
3411   case Intrinsic::nvvm_tex_1d_array_v4u32_f32:
3412   case Intrinsic::nvvm_tex_1d_array_level_v4u32_f32:
3413   case Intrinsic::nvvm_tex_1d_array_grad_v4u32_f32:
3414   case Intrinsic::nvvm_tex_2d_v4u32_s32:
3415   case Intrinsic::nvvm_tex_2d_v4u32_f32:
3416   case Intrinsic::nvvm_tex_2d_level_v4u32_f32:
3417   case Intrinsic::nvvm_tex_2d_grad_v4u32_f32:
3418   case Intrinsic::nvvm_tex_2d_array_v4u32_s32:
3419   case Intrinsic::nvvm_tex_2d_array_v4u32_f32:
3420   case Intrinsic::nvvm_tex_2d_array_level_v4u32_f32:
3421   case Intrinsic::nvvm_tex_2d_array_grad_v4u32_f32:
3422   case Intrinsic::nvvm_tex_3d_v4u32_s32:
3423   case Intrinsic::nvvm_tex_3d_v4u32_f32:
3424   case Intrinsic::nvvm_tex_3d_level_v4u32_f32:
3425   case Intrinsic::nvvm_tex_3d_grad_v4u32_f32:
3426   case Intrinsic::nvvm_tld4_r_2d_v4s32_f32:
3427   case Intrinsic::nvvm_tld4_g_2d_v4s32_f32:
3428   case Intrinsic::nvvm_tld4_b_2d_v4s32_f32:
3429   case Intrinsic::nvvm_tld4_a_2d_v4s32_f32:
3430   case Intrinsic::nvvm_tld4_r_2d_v4u32_f32:
3431   case Intrinsic::nvvm_tld4_g_2d_v4u32_f32:
3432   case Intrinsic::nvvm_tld4_b_2d_v4u32_f32:
3433   case Intrinsic::nvvm_tld4_a_2d_v4u32_f32:
3434   case Intrinsic::nvvm_tex_unified_1d_v4s32_s32:
3435   case Intrinsic::nvvm_tex_unified_1d_v4s32_f32:
3436   case Intrinsic::nvvm_tex_unified_1d_level_v4s32_f32:
3437   case Intrinsic::nvvm_tex_unified_1d_grad_v4s32_f32:
3438   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_s32:
3439   case Intrinsic::nvvm_tex_unified_1d_array_v4s32_f32:
3440   case Intrinsic::nvvm_tex_unified_1d_array_level_v4s32_f32:
3441   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4s32_f32:
3442   case Intrinsic::nvvm_tex_unified_2d_v4s32_s32:
3443   case Intrinsic::nvvm_tex_unified_2d_v4s32_f32:
3444   case Intrinsic::nvvm_tex_unified_2d_level_v4s32_f32:
3445   case Intrinsic::nvvm_tex_unified_2d_grad_v4s32_f32:
3446   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_s32:
3447   case Intrinsic::nvvm_tex_unified_2d_array_v4s32_f32:
3448   case Intrinsic::nvvm_tex_unified_2d_array_level_v4s32_f32:
3449   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4s32_f32:
3450   case Intrinsic::nvvm_tex_unified_3d_v4s32_s32:
3451   case Intrinsic::nvvm_tex_unified_3d_v4s32_f32:
3452   case Intrinsic::nvvm_tex_unified_3d_level_v4s32_f32:
3453   case Intrinsic::nvvm_tex_unified_3d_grad_v4s32_f32:
3454   case Intrinsic::nvvm_tex_unified_1d_v4u32_s32:
3455   case Intrinsic::nvvm_tex_unified_1d_v4u32_f32:
3456   case Intrinsic::nvvm_tex_unified_1d_level_v4u32_f32:
3457   case Intrinsic::nvvm_tex_unified_1d_grad_v4u32_f32:
3458   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_s32:
3459   case Intrinsic::nvvm_tex_unified_1d_array_v4u32_f32:
3460   case Intrinsic::nvvm_tex_unified_1d_array_level_v4u32_f32:
3461   case Intrinsic::nvvm_tex_unified_1d_array_grad_v4u32_f32:
3462   case Intrinsic::nvvm_tex_unified_2d_v4u32_s32:
3463   case Intrinsic::nvvm_tex_unified_2d_v4u32_f32:
3464   case Intrinsic::nvvm_tex_unified_2d_level_v4u32_f32:
3465   case Intrinsic::nvvm_tex_unified_2d_grad_v4u32_f32:
3466   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_s32:
3467   case Intrinsic::nvvm_tex_unified_2d_array_v4u32_f32:
3468   case Intrinsic::nvvm_tex_unified_2d_array_level_v4u32_f32:
3469   case Intrinsic::nvvm_tex_unified_2d_array_grad_v4u32_f32:
3470   case Intrinsic::nvvm_tex_unified_3d_v4u32_s32:
3471   case Intrinsic::nvvm_tex_unified_3d_v4u32_f32:
3472   case Intrinsic::nvvm_tex_unified_3d_level_v4u32_f32:
3473   case Intrinsic::nvvm_tex_unified_3d_grad_v4u32_f32:
3474   case Intrinsic::nvvm_tex_unified_cube_v4s32_f32:
3475   case Intrinsic::nvvm_tex_unified_cube_level_v4s32_f32:
3476   case Intrinsic::nvvm_tex_unified_cube_array_v4s32_f32:
3477   case Intrinsic::nvvm_tex_unified_cube_array_level_v4s32_f32:
3478   case Intrinsic::nvvm_tex_unified_cube_v4u32_f32:
3479   case Intrinsic::nvvm_tex_unified_cube_level_v4u32_f32:
3480   case Intrinsic::nvvm_tex_unified_cube_array_v4u32_f32:
3481   case Intrinsic::nvvm_tex_unified_cube_array_level_v4u32_f32:
3482   case Intrinsic::nvvm_tld4_unified_r_2d_v4s32_f32:
3483   case Intrinsic::nvvm_tld4_unified_g_2d_v4s32_f32:
3484   case Intrinsic::nvvm_tld4_unified_b_2d_v4s32_f32:
3485   case Intrinsic::nvvm_tld4_unified_a_2d_v4s32_f32:
3486   case Intrinsic::nvvm_tld4_unified_r_2d_v4u32_f32:
3487   case Intrinsic::nvvm_tld4_unified_g_2d_v4u32_f32:
3488   case Intrinsic::nvvm_tld4_unified_b_2d_v4u32_f32:
3489   case Intrinsic::nvvm_tld4_unified_a_2d_v4u32_f32: {
3490     Info.opc = getOpcForTextureInstr(Intrinsic);
3491     Info.memVT = MVT::v4i32;
3492     Info.ptrVal = nullptr;
3493     Info.offset = 0;
3494     Info.vol = 0;
3495     Info.readMem = true;
3496     Info.writeMem = false;
3497     Info.align = 16;
3498     return true;
3499   }
3500   case Intrinsic::nvvm_suld_1d_i8_clamp:
3501   case Intrinsic::nvvm_suld_1d_v2i8_clamp:
3502   case Intrinsic::nvvm_suld_1d_v4i8_clamp:
3503   case Intrinsic::nvvm_suld_1d_array_i8_clamp:
3504   case Intrinsic::nvvm_suld_1d_array_v2i8_clamp:
3505   case Intrinsic::nvvm_suld_1d_array_v4i8_clamp:
3506   case Intrinsic::nvvm_suld_2d_i8_clamp:
3507   case Intrinsic::nvvm_suld_2d_v2i8_clamp:
3508   case Intrinsic::nvvm_suld_2d_v4i8_clamp:
3509   case Intrinsic::nvvm_suld_2d_array_i8_clamp:
3510   case Intrinsic::nvvm_suld_2d_array_v2i8_clamp:
3511   case Intrinsic::nvvm_suld_2d_array_v4i8_clamp:
3512   case Intrinsic::nvvm_suld_3d_i8_clamp:
3513   case Intrinsic::nvvm_suld_3d_v2i8_clamp:
3514   case Intrinsic::nvvm_suld_3d_v4i8_clamp:
3515   case Intrinsic::nvvm_suld_1d_i8_trap:
3516   case Intrinsic::nvvm_suld_1d_v2i8_trap:
3517   case Intrinsic::nvvm_suld_1d_v4i8_trap:
3518   case Intrinsic::nvvm_suld_1d_array_i8_trap:
3519   case Intrinsic::nvvm_suld_1d_array_v2i8_trap:
3520   case Intrinsic::nvvm_suld_1d_array_v4i8_trap:
3521   case Intrinsic::nvvm_suld_2d_i8_trap:
3522   case Intrinsic::nvvm_suld_2d_v2i8_trap:
3523   case Intrinsic::nvvm_suld_2d_v4i8_trap:
3524   case Intrinsic::nvvm_suld_2d_array_i8_trap:
3525   case Intrinsic::nvvm_suld_2d_array_v2i8_trap:
3526   case Intrinsic::nvvm_suld_2d_array_v4i8_trap:
3527   case Intrinsic::nvvm_suld_3d_i8_trap:
3528   case Intrinsic::nvvm_suld_3d_v2i8_trap:
3529   case Intrinsic::nvvm_suld_3d_v4i8_trap:
3530   case Intrinsic::nvvm_suld_1d_i8_zero:
3531   case Intrinsic::nvvm_suld_1d_v2i8_zero:
3532   case Intrinsic::nvvm_suld_1d_v4i8_zero:
3533   case Intrinsic::nvvm_suld_1d_array_i8_zero:
3534   case Intrinsic::nvvm_suld_1d_array_v2i8_zero:
3535   case Intrinsic::nvvm_suld_1d_array_v4i8_zero:
3536   case Intrinsic::nvvm_suld_2d_i8_zero:
3537   case Intrinsic::nvvm_suld_2d_v2i8_zero:
3538   case Intrinsic::nvvm_suld_2d_v4i8_zero:
3539   case Intrinsic::nvvm_suld_2d_array_i8_zero:
3540   case Intrinsic::nvvm_suld_2d_array_v2i8_zero:
3541   case Intrinsic::nvvm_suld_2d_array_v4i8_zero:
3542   case Intrinsic::nvvm_suld_3d_i8_zero:
3543   case Intrinsic::nvvm_suld_3d_v2i8_zero:
3544   case Intrinsic::nvvm_suld_3d_v4i8_zero: {
3545     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3546     Info.memVT = MVT::i8;
3547     Info.ptrVal = nullptr;
3548     Info.offset = 0;
3549     Info.vol = 0;
3550     Info.readMem = true;
3551     Info.writeMem = false;
3552     Info.align = 16;
3553     return true;
3554   }
3555   case Intrinsic::nvvm_suld_1d_i16_clamp:
3556   case Intrinsic::nvvm_suld_1d_v2i16_clamp:
3557   case Intrinsic::nvvm_suld_1d_v4i16_clamp:
3558   case Intrinsic::nvvm_suld_1d_array_i16_clamp:
3559   case Intrinsic::nvvm_suld_1d_array_v2i16_clamp:
3560   case Intrinsic::nvvm_suld_1d_array_v4i16_clamp:
3561   case Intrinsic::nvvm_suld_2d_i16_clamp:
3562   case Intrinsic::nvvm_suld_2d_v2i16_clamp:
3563   case Intrinsic::nvvm_suld_2d_v4i16_clamp:
3564   case Intrinsic::nvvm_suld_2d_array_i16_clamp:
3565   case Intrinsic::nvvm_suld_2d_array_v2i16_clamp:
3566   case Intrinsic::nvvm_suld_2d_array_v4i16_clamp:
3567   case Intrinsic::nvvm_suld_3d_i16_clamp:
3568   case Intrinsic::nvvm_suld_3d_v2i16_clamp:
3569   case Intrinsic::nvvm_suld_3d_v4i16_clamp:
3570   case Intrinsic::nvvm_suld_1d_i16_trap:
3571   case Intrinsic::nvvm_suld_1d_v2i16_trap:
3572   case Intrinsic::nvvm_suld_1d_v4i16_trap:
3573   case Intrinsic::nvvm_suld_1d_array_i16_trap:
3574   case Intrinsic::nvvm_suld_1d_array_v2i16_trap:
3575   case Intrinsic::nvvm_suld_1d_array_v4i16_trap:
3576   case Intrinsic::nvvm_suld_2d_i16_trap:
3577   case Intrinsic::nvvm_suld_2d_v2i16_trap:
3578   case Intrinsic::nvvm_suld_2d_v4i16_trap:
3579   case Intrinsic::nvvm_suld_2d_array_i16_trap:
3580   case Intrinsic::nvvm_suld_2d_array_v2i16_trap:
3581   case Intrinsic::nvvm_suld_2d_array_v4i16_trap:
3582   case Intrinsic::nvvm_suld_3d_i16_trap:
3583   case Intrinsic::nvvm_suld_3d_v2i16_trap:
3584   case Intrinsic::nvvm_suld_3d_v4i16_trap:
3585   case Intrinsic::nvvm_suld_1d_i16_zero:
3586   case Intrinsic::nvvm_suld_1d_v2i16_zero:
3587   case Intrinsic::nvvm_suld_1d_v4i16_zero:
3588   case Intrinsic::nvvm_suld_1d_array_i16_zero:
3589   case Intrinsic::nvvm_suld_1d_array_v2i16_zero:
3590   case Intrinsic::nvvm_suld_1d_array_v4i16_zero:
3591   case Intrinsic::nvvm_suld_2d_i16_zero:
3592   case Intrinsic::nvvm_suld_2d_v2i16_zero:
3593   case Intrinsic::nvvm_suld_2d_v4i16_zero:
3594   case Intrinsic::nvvm_suld_2d_array_i16_zero:
3595   case Intrinsic::nvvm_suld_2d_array_v2i16_zero:
3596   case Intrinsic::nvvm_suld_2d_array_v4i16_zero:
3597   case Intrinsic::nvvm_suld_3d_i16_zero:
3598   case Intrinsic::nvvm_suld_3d_v2i16_zero:
3599   case Intrinsic::nvvm_suld_3d_v4i16_zero: {
3600     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3601     Info.memVT = MVT::i16;
3602     Info.ptrVal = nullptr;
3603     Info.offset = 0;
3604     Info.vol = 0;
3605     Info.readMem = true;
3606     Info.writeMem = false;
3607     Info.align = 16;
3608     return true;
3609   }
3610   case Intrinsic::nvvm_suld_1d_i32_clamp:
3611   case Intrinsic::nvvm_suld_1d_v2i32_clamp:
3612   case Intrinsic::nvvm_suld_1d_v4i32_clamp:
3613   case Intrinsic::nvvm_suld_1d_array_i32_clamp:
3614   case Intrinsic::nvvm_suld_1d_array_v2i32_clamp:
3615   case Intrinsic::nvvm_suld_1d_array_v4i32_clamp:
3616   case Intrinsic::nvvm_suld_2d_i32_clamp:
3617   case Intrinsic::nvvm_suld_2d_v2i32_clamp:
3618   case Intrinsic::nvvm_suld_2d_v4i32_clamp:
3619   case Intrinsic::nvvm_suld_2d_array_i32_clamp:
3620   case Intrinsic::nvvm_suld_2d_array_v2i32_clamp:
3621   case Intrinsic::nvvm_suld_2d_array_v4i32_clamp:
3622   case Intrinsic::nvvm_suld_3d_i32_clamp:
3623   case Intrinsic::nvvm_suld_3d_v2i32_clamp:
3624   case Intrinsic::nvvm_suld_3d_v4i32_clamp:
3625   case Intrinsic::nvvm_suld_1d_i32_trap:
3626   case Intrinsic::nvvm_suld_1d_v2i32_trap:
3627   case Intrinsic::nvvm_suld_1d_v4i32_trap:
3628   case Intrinsic::nvvm_suld_1d_array_i32_trap:
3629   case Intrinsic::nvvm_suld_1d_array_v2i32_trap:
3630   case Intrinsic::nvvm_suld_1d_array_v4i32_trap:
3631   case Intrinsic::nvvm_suld_2d_i32_trap:
3632   case Intrinsic::nvvm_suld_2d_v2i32_trap:
3633   case Intrinsic::nvvm_suld_2d_v4i32_trap:
3634   case Intrinsic::nvvm_suld_2d_array_i32_trap:
3635   case Intrinsic::nvvm_suld_2d_array_v2i32_trap:
3636   case Intrinsic::nvvm_suld_2d_array_v4i32_trap:
3637   case Intrinsic::nvvm_suld_3d_i32_trap:
3638   case Intrinsic::nvvm_suld_3d_v2i32_trap:
3639   case Intrinsic::nvvm_suld_3d_v4i32_trap:
3640   case Intrinsic::nvvm_suld_1d_i32_zero:
3641   case Intrinsic::nvvm_suld_1d_v2i32_zero:
3642   case Intrinsic::nvvm_suld_1d_v4i32_zero:
3643   case Intrinsic::nvvm_suld_1d_array_i32_zero:
3644   case Intrinsic::nvvm_suld_1d_array_v2i32_zero:
3645   case Intrinsic::nvvm_suld_1d_array_v4i32_zero:
3646   case Intrinsic::nvvm_suld_2d_i32_zero:
3647   case Intrinsic::nvvm_suld_2d_v2i32_zero:
3648   case Intrinsic::nvvm_suld_2d_v4i32_zero:
3649   case Intrinsic::nvvm_suld_2d_array_i32_zero:
3650   case Intrinsic::nvvm_suld_2d_array_v2i32_zero:
3651   case Intrinsic::nvvm_suld_2d_array_v4i32_zero:
3652   case Intrinsic::nvvm_suld_3d_i32_zero:
3653   case Intrinsic::nvvm_suld_3d_v2i32_zero:
3654   case Intrinsic::nvvm_suld_3d_v4i32_zero: {
3655     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3656     Info.memVT = MVT::i32;
3657     Info.ptrVal = nullptr;
3658     Info.offset = 0;
3659     Info.vol = 0;
3660     Info.readMem = true;
3661     Info.writeMem = false;
3662     Info.align = 16;
3663     return true;
3664   }
3665   case Intrinsic::nvvm_suld_1d_i64_clamp:
3666   case Intrinsic::nvvm_suld_1d_v2i64_clamp:
3667   case Intrinsic::nvvm_suld_1d_array_i64_clamp:
3668   case Intrinsic::nvvm_suld_1d_array_v2i64_clamp:
3669   case Intrinsic::nvvm_suld_2d_i64_clamp:
3670   case Intrinsic::nvvm_suld_2d_v2i64_clamp:
3671   case Intrinsic::nvvm_suld_2d_array_i64_clamp:
3672   case Intrinsic::nvvm_suld_2d_array_v2i64_clamp:
3673   case Intrinsic::nvvm_suld_3d_i64_clamp:
3674   case Intrinsic::nvvm_suld_3d_v2i64_clamp:
3675   case Intrinsic::nvvm_suld_1d_i64_trap:
3676   case Intrinsic::nvvm_suld_1d_v2i64_trap:
3677   case Intrinsic::nvvm_suld_1d_array_i64_trap:
3678   case Intrinsic::nvvm_suld_1d_array_v2i64_trap:
3679   case Intrinsic::nvvm_suld_2d_i64_trap:
3680   case Intrinsic::nvvm_suld_2d_v2i64_trap:
3681   case Intrinsic::nvvm_suld_2d_array_i64_trap:
3682   case Intrinsic::nvvm_suld_2d_array_v2i64_trap:
3683   case Intrinsic::nvvm_suld_3d_i64_trap:
3684   case Intrinsic::nvvm_suld_3d_v2i64_trap:
3685   case Intrinsic::nvvm_suld_1d_i64_zero:
3686   case Intrinsic::nvvm_suld_1d_v2i64_zero:
3687   case Intrinsic::nvvm_suld_1d_array_i64_zero:
3688   case Intrinsic::nvvm_suld_1d_array_v2i64_zero:
3689   case Intrinsic::nvvm_suld_2d_i64_zero:
3690   case Intrinsic::nvvm_suld_2d_v2i64_zero:
3691   case Intrinsic::nvvm_suld_2d_array_i64_zero:
3692   case Intrinsic::nvvm_suld_2d_array_v2i64_zero:
3693   case Intrinsic::nvvm_suld_3d_i64_zero:
3694   case Intrinsic::nvvm_suld_3d_v2i64_zero: {
3695     Info.opc = getOpcForSurfaceInstr(Intrinsic);
3696     Info.memVT = MVT::i64;
3697     Info.ptrVal = nullptr;
3698     Info.offset = 0;
3699     Info.vol = 0;
3700     Info.readMem = true;
3701     Info.writeMem = false;
3702     Info.align = 16;
3703     return true;
3704   }
3705   }
3706   return false;
3707 }
3708 
3709 /// isLegalAddressingMode - Return true if the addressing mode represented
3710 /// by AM is legal for this target, for a load/store of the specified type.
3711 /// Used to guide target specific optimizations, like loop strength reduction
3712 /// (LoopStrengthReduce.cpp) and memory optimization for address mode
3713 /// (CodeGenPrepare.cpp)
3714 bool NVPTXTargetLowering::isLegalAddressingMode(const DataLayout &DL,
3715                                                 const AddrMode &AM, Type *Ty,
3716                                                 unsigned AS) const {
3717 
3718   // AddrMode - This represents an addressing mode of:
3719   //    BaseGV + BaseOffs + BaseReg + Scale*ScaleReg
3720   //
3721   // The legal address modes are
3722   // - [avar]
3723   // - [areg]
3724   // - [areg+immoff]
3725   // - [immAddr]
3726 
3727   if (AM.BaseGV) {
3728     return !AM.BaseOffs && !AM.HasBaseReg && !AM.Scale;
3729   }
3730 
3731   switch (AM.Scale) {
3732   case 0: // "r", "r+i" or "i" is allowed
3733     break;
3734   case 1:
3735     if (AM.HasBaseReg) // "r+r+i" or "r+r" is not allowed.
3736       return false;
3737     // Otherwise we have r+i.
3738     break;
3739   default:
3740     // No scale > 1 is allowed
3741     return false;
3742   }
3743   return true;
3744 }
3745 
3746 //===----------------------------------------------------------------------===//
3747 //                         NVPTX Inline Assembly Support
3748 //===----------------------------------------------------------------------===//
3749 
3750 /// getConstraintType - Given a constraint letter, return the type of
3751 /// constraint it is for this target.
3752 NVPTXTargetLowering::ConstraintType
3753 NVPTXTargetLowering::getConstraintType(StringRef Constraint) const {
3754   if (Constraint.size() == 1) {
3755     switch (Constraint[0]) {
3756     default:
3757       break;
3758     case 'b':
3759     case 'r':
3760     case 'h':
3761     case 'c':
3762     case 'l':
3763     case 'f':
3764     case 'd':
3765     case '0':
3766     case 'N':
3767       return C_RegisterClass;
3768     }
3769   }
3770   return TargetLowering::getConstraintType(Constraint);
3771 }
3772 
3773 std::pair<unsigned, const TargetRegisterClass *>
3774 NVPTXTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
3775                                                   StringRef Constraint,
3776                                                   MVT VT) const {
3777   if (Constraint.size() == 1) {
3778     switch (Constraint[0]) {
3779     case 'b':
3780       return std::make_pair(0U, &NVPTX::Int1RegsRegClass);
3781     case 'c':
3782       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3783     case 'h':
3784       return std::make_pair(0U, &NVPTX::Int16RegsRegClass);
3785     case 'r':
3786       return std::make_pair(0U, &NVPTX::Int32RegsRegClass);
3787     case 'l':
3788     case 'N':
3789       return std::make_pair(0U, &NVPTX::Int64RegsRegClass);
3790     case 'f':
3791       return std::make_pair(0U, &NVPTX::Float32RegsRegClass);
3792     case 'd':
3793       return std::make_pair(0U, &NVPTX::Float64RegsRegClass);
3794     }
3795   }
3796   return TargetLowering::getRegForInlineAsmConstraint(TRI, Constraint, VT);
3797 }
3798 
3799 //===----------------------------------------------------------------------===//
3800 //                         NVPTX DAG Combining
3801 //===----------------------------------------------------------------------===//
3802 
3803 bool NVPTXTargetLowering::allowFMA(MachineFunction &MF,
3804                                    CodeGenOpt::Level OptLevel) const {
3805   const Function *F = MF.getFunction();
3806   const TargetOptions &TO = MF.getTarget().Options;
3807 
3808   // Always honor command-line argument
3809   if (FMAContractLevelOpt.getNumOccurrences() > 0) {
3810     return FMAContractLevelOpt > 0;
3811   } else if (OptLevel == 0) {
3812     // Do not contract if we're not optimizing the code
3813     return false;
3814   } else if (TO.AllowFPOpFusion == FPOpFusion::Fast || TO.UnsafeFPMath) {
3815     // Honor TargetOptions flags that explicitly say fusion is okay
3816     return true;
3817   } else if (F->hasFnAttribute("unsafe-fp-math")) {
3818     // Check for unsafe-fp-math=true coming from Clang
3819     Attribute Attr = F->getFnAttribute("unsafe-fp-math");
3820     StringRef Val = Attr.getValueAsString();
3821     if (Val == "true")
3822       return true;
3823   }
3824 
3825   // We did not have a clear indication that fusion is allowed, so assume not
3826   return false;
3827 }
3828 
3829 /// PerformADDCombineWithOperands - Try DAG combinations for an ADD with
3830 /// operands N0 and N1.  This is a helper for PerformADDCombine that is
3831 /// called with the default operands, and if that fails, with commuted
3832 /// operands.
3833 static SDValue PerformADDCombineWithOperands(SDNode *N, SDValue N0, SDValue N1,
3834                                            TargetLowering::DAGCombinerInfo &DCI,
3835                                              const NVPTXSubtarget &Subtarget,
3836                                              CodeGenOpt::Level OptLevel) {
3837   SelectionDAG  &DAG = DCI.DAG;
3838   // Skip non-integer, non-scalar case
3839   EVT VT=N0.getValueType();
3840   if (VT.isVector())
3841     return SDValue();
3842 
3843   // fold (add (mul a, b), c) -> (mad a, b, c)
3844   //
3845   if (N0.getOpcode() == ISD::MUL) {
3846     assert (VT.isInteger());
3847     // For integer:
3848     // Since integer multiply-add costs the same as integer multiply
3849     // but is more costly than integer add, do the fusion only when
3850     // the mul is only used in the add.
3851     if (OptLevel==CodeGenOpt::None || VT != MVT::i32 ||
3852         !N0.getNode()->hasOneUse())
3853       return SDValue();
3854 
3855     // Do the folding
3856     return DAG.getNode(NVPTXISD::IMAD, SDLoc(N), VT,
3857                        N0.getOperand(0), N0.getOperand(1), N1);
3858   }
3859   else if (N0.getOpcode() == ISD::FMUL) {
3860     if (VT == MVT::f32 || VT == MVT::f64) {
3861       const auto *TLI = static_cast<const NVPTXTargetLowering *>(
3862           &DAG.getTargetLoweringInfo());
3863       if (!TLI->allowFMA(DAG.getMachineFunction(), OptLevel))
3864         return SDValue();
3865 
3866       // For floating point:
3867       // Do the fusion only when the mul has less than 5 uses and all
3868       // are add.
3869       // The heuristic is that if a use is not an add, then that use
3870       // cannot be fused into fma, therefore mul is still needed anyway.
3871       // If there are more than 4 uses, even if they are all add, fusing
3872       // them will increase register pressue.
3873       //
3874       int numUses = 0;
3875       int nonAddCount = 0;
3876       for (SDNode::use_iterator UI = N0.getNode()->use_begin(),
3877            UE = N0.getNode()->use_end();
3878            UI != UE; ++UI) {
3879         numUses++;
3880         SDNode *User = *UI;
3881         if (User->getOpcode() != ISD::FADD)
3882           ++nonAddCount;
3883       }
3884       if (numUses >= 5)
3885         return SDValue();
3886       if (nonAddCount) {
3887         int orderNo = N->getIROrder();
3888         int orderNo2 = N0.getNode()->getIROrder();
3889         // simple heuristics here for considering potential register
3890         // pressure, the logics here is that the differnce are used
3891         // to measure the distance between def and use, the longer distance
3892         // more likely cause register pressure.
3893         if (orderNo - orderNo2 < 500)
3894           return SDValue();
3895 
3896         // Now, check if at least one of the FMUL's operands is live beyond the node N,
3897         // which guarantees that the FMA will not increase register pressure at node N.
3898         bool opIsLive = false;
3899         const SDNode *left = N0.getOperand(0).getNode();
3900         const SDNode *right = N0.getOperand(1).getNode();
3901 
3902         if (isa<ConstantSDNode>(left) || isa<ConstantSDNode>(right))
3903           opIsLive = true;
3904 
3905         if (!opIsLive)
3906           for (SDNode::use_iterator UI = left->use_begin(), UE = left->use_end(); UI != UE; ++UI) {
3907             SDNode *User = *UI;
3908             int orderNo3 = User->getIROrder();
3909             if (orderNo3 > orderNo) {
3910               opIsLive = true;
3911               break;
3912             }
3913           }
3914 
3915         if (!opIsLive)
3916           for (SDNode::use_iterator UI = right->use_begin(), UE = right->use_end(); UI != UE; ++UI) {
3917             SDNode *User = *UI;
3918             int orderNo3 = User->getIROrder();
3919             if (orderNo3 > orderNo) {
3920               opIsLive = true;
3921               break;
3922             }
3923           }
3924 
3925         if (!opIsLive)
3926           return SDValue();
3927       }
3928 
3929       return DAG.getNode(ISD::FMA, SDLoc(N), VT,
3930                          N0.getOperand(0), N0.getOperand(1), N1);
3931     }
3932   }
3933 
3934   return SDValue();
3935 }
3936 
3937 /// PerformADDCombine - Target-specific dag combine xforms for ISD::ADD.
3938 ///
3939 static SDValue PerformADDCombine(SDNode *N,
3940                                  TargetLowering::DAGCombinerInfo &DCI,
3941                                  const NVPTXSubtarget &Subtarget,
3942                                  CodeGenOpt::Level OptLevel) {
3943   SDValue N0 = N->getOperand(0);
3944   SDValue N1 = N->getOperand(1);
3945 
3946   // First try with the default operand order.
3947   if (SDValue Result =
3948           PerformADDCombineWithOperands(N, N0, N1, DCI, Subtarget, OptLevel))
3949     return Result;
3950 
3951   // If that didn't work, try again with the operands commuted.
3952   return PerformADDCombineWithOperands(N, N1, N0, DCI, Subtarget, OptLevel);
3953 }
3954 
3955 static SDValue PerformANDCombine(SDNode *N,
3956                                  TargetLowering::DAGCombinerInfo &DCI) {
3957   // The type legalizer turns a vector load of i8 values into a zextload to i16
3958   // registers, optionally ANY_EXTENDs it (if target type is integer),
3959   // and ANDs off the high 8 bits. Since we turn this load into a
3960   // target-specific DAG node, the DAG combiner fails to eliminate these AND
3961   // nodes. Do that here.
3962   SDValue Val = N->getOperand(0);
3963   SDValue Mask = N->getOperand(1);
3964 
3965   if (isa<ConstantSDNode>(Val)) {
3966     std::swap(Val, Mask);
3967   }
3968 
3969   SDValue AExt;
3970   // Generally, we will see zextload -> IMOV16rr -> ANY_EXTEND -> and
3971   if (Val.getOpcode() == ISD::ANY_EXTEND) {
3972     AExt = Val;
3973     Val = Val->getOperand(0);
3974   }
3975 
3976   if (Val->isMachineOpcode() && Val->getMachineOpcode() == NVPTX::IMOV16rr) {
3977     Val = Val->getOperand(0);
3978   }
3979 
3980   if (Val->getOpcode() == NVPTXISD::LoadV2 ||
3981       Val->getOpcode() == NVPTXISD::LoadV4) {
3982     ConstantSDNode *MaskCnst = dyn_cast<ConstantSDNode>(Mask);
3983     if (!MaskCnst) {
3984       // Not an AND with a constant
3985       return SDValue();
3986     }
3987 
3988     uint64_t MaskVal = MaskCnst->getZExtValue();
3989     if (MaskVal != 0xff) {
3990       // Not an AND that chops off top 8 bits
3991       return SDValue();
3992     }
3993 
3994     MemSDNode *Mem = dyn_cast<MemSDNode>(Val);
3995     if (!Mem) {
3996       // Not a MemSDNode?!?
3997       return SDValue();
3998     }
3999 
4000     EVT MemVT = Mem->getMemoryVT();
4001     if (MemVT != MVT::v2i8 && MemVT != MVT::v4i8) {
4002       // We only handle the i8 case
4003       return SDValue();
4004     }
4005 
4006     unsigned ExtType =
4007       cast<ConstantSDNode>(Val->getOperand(Val->getNumOperands()-1))->
4008         getZExtValue();
4009     if (ExtType == ISD::SEXTLOAD) {
4010       // If for some reason the load is a sextload, the and is needed to zero
4011       // out the high 8 bits
4012       return SDValue();
4013     }
4014 
4015     bool AddTo = false;
4016     if (AExt.getNode() != 0) {
4017       // Re-insert the ext as a zext.
4018       Val = DCI.DAG.getNode(ISD::ZERO_EXTEND, SDLoc(N),
4019                             AExt.getValueType(), Val);
4020       AddTo = true;
4021     }
4022 
4023     // If we get here, the AND is unnecessary.  Just replace it with the load
4024     DCI.CombineTo(N, Val, AddTo);
4025   }
4026 
4027   return SDValue();
4028 }
4029 
4030 static SDValue PerformSELECTCombine(SDNode *N,
4031                                     TargetLowering::DAGCombinerInfo &DCI) {
4032   // Currently this detects patterns for integer min and max and
4033   // lowers them to PTX-specific intrinsics that enable hardware
4034   // support.
4035 
4036   const SDValue Cond = N->getOperand(0);
4037   if (Cond.getOpcode() != ISD::SETCC) return SDValue();
4038 
4039   const SDValue LHS = Cond.getOperand(0);
4040   const SDValue RHS = Cond.getOperand(1);
4041   const SDValue True = N->getOperand(1);
4042   const SDValue False = N->getOperand(2);
4043   if (!(LHS == True && RHS == False) && !(LHS == False && RHS == True))
4044     return SDValue();
4045 
4046   const EVT VT = N->getValueType(0);
4047   if (VT != MVT::i32 && VT != MVT::i64) return SDValue();
4048 
4049   const ISD::CondCode CC = cast<CondCodeSDNode>(Cond.getOperand(2))->get();
4050   SDValue Larger;  // The larger of LHS and RHS when condition is true.
4051   switch (CC) {
4052     case ISD::SETULT:
4053     case ISD::SETULE:
4054     case ISD::SETLT:
4055     case ISD::SETLE:
4056       Larger = RHS;
4057       break;
4058 
4059     case ISD::SETGT:
4060     case ISD::SETGE:
4061     case ISD::SETUGT:
4062     case ISD::SETUGE:
4063       Larger = LHS;
4064       break;
4065 
4066     default:
4067       return SDValue();
4068   }
4069   const bool IsMax = (Larger == True);
4070   const bool IsSigned = ISD::isSignedIntSetCC(CC);
4071 
4072   unsigned IntrinsicId;
4073   if (VT == MVT::i32) {
4074     if (IsSigned)
4075       IntrinsicId = IsMax ? Intrinsic::nvvm_max_i : Intrinsic::nvvm_min_i;
4076     else
4077       IntrinsicId = IsMax ? Intrinsic::nvvm_max_ui : Intrinsic::nvvm_min_ui;
4078   } else {
4079     assert(VT == MVT::i64);
4080     if (IsSigned)
4081       IntrinsicId = IsMax ? Intrinsic::nvvm_max_ll : Intrinsic::nvvm_min_ll;
4082     else
4083       IntrinsicId = IsMax ? Intrinsic::nvvm_max_ull : Intrinsic::nvvm_min_ull;
4084   }
4085 
4086   SDLoc DL(N);
4087   return DCI.DAG.getNode(ISD::INTRINSIC_WO_CHAIN, DL, VT,
4088                          DCI.DAG.getConstant(IntrinsicId, DL, VT), LHS, RHS);
4089 }
4090 
4091 enum OperandSignedness {
4092   Signed = 0,
4093   Unsigned,
4094   Unknown
4095 };
4096 
4097 /// IsMulWideOperandDemotable - Checks if the provided DAG node is an operand
4098 /// that can be demoted to \p OptSize bits without loss of information. The
4099 /// signedness of the operand, if determinable, is placed in \p S.
4100 static bool IsMulWideOperandDemotable(SDValue Op,
4101                                       unsigned OptSize,
4102                                       OperandSignedness &S) {
4103   S = Unknown;
4104 
4105   if (Op.getOpcode() == ISD::SIGN_EXTEND ||
4106       Op.getOpcode() == ISD::SIGN_EXTEND_INREG) {
4107     EVT OrigVT = Op.getOperand(0).getValueType();
4108     if (OrigVT.getSizeInBits() <= OptSize) {
4109       S = Signed;
4110       return true;
4111     }
4112   } else if (Op.getOpcode() == ISD::ZERO_EXTEND) {
4113     EVT OrigVT = Op.getOperand(0).getValueType();
4114     if (OrigVT.getSizeInBits() <= OptSize) {
4115       S = Unsigned;
4116       return true;
4117     }
4118   }
4119 
4120   return false;
4121 }
4122 
4123 /// AreMulWideOperandsDemotable - Checks if the given LHS and RHS operands can
4124 /// be demoted to \p OptSize bits without loss of information. If the operands
4125 /// contain a constant, it should appear as the RHS operand. The signedness of
4126 /// the operands is placed in \p IsSigned.
4127 static bool AreMulWideOperandsDemotable(SDValue LHS, SDValue RHS,
4128                                         unsigned OptSize,
4129                                         bool &IsSigned) {
4130 
4131   OperandSignedness LHSSign;
4132 
4133   // The LHS operand must be a demotable op
4134   if (!IsMulWideOperandDemotable(LHS, OptSize, LHSSign))
4135     return false;
4136 
4137   // We should have been able to determine the signedness from the LHS
4138   if (LHSSign == Unknown)
4139     return false;
4140 
4141   IsSigned = (LHSSign == Signed);
4142 
4143   // The RHS can be a demotable op or a constant
4144   if (ConstantSDNode *CI = dyn_cast<ConstantSDNode>(RHS)) {
4145     APInt Val = CI->getAPIntValue();
4146     if (LHSSign == Unsigned) {
4147       return Val.isIntN(OptSize);
4148     } else {
4149       return Val.isSignedIntN(OptSize);
4150     }
4151   } else {
4152     OperandSignedness RHSSign;
4153     if (!IsMulWideOperandDemotable(RHS, OptSize, RHSSign))
4154       return false;
4155 
4156     return LHSSign == RHSSign;
4157   }
4158 }
4159 
4160 /// TryMULWIDECombine - Attempt to replace a multiply of M bits with a multiply
4161 /// of M/2 bits that produces an M-bit result (i.e. mul.wide). This transform
4162 /// works on both multiply DAG nodes and SHL DAG nodes with a constant shift
4163 /// amount.
4164 static SDValue TryMULWIDECombine(SDNode *N,
4165                                  TargetLowering::DAGCombinerInfo &DCI) {
4166   EVT MulType = N->getValueType(0);
4167   if (MulType != MVT::i32 && MulType != MVT::i64) {
4168     return SDValue();
4169   }
4170 
4171   SDLoc DL(N);
4172   unsigned OptSize = MulType.getSizeInBits() >> 1;
4173   SDValue LHS = N->getOperand(0);
4174   SDValue RHS = N->getOperand(1);
4175 
4176   // Canonicalize the multiply so the constant (if any) is on the right
4177   if (N->getOpcode() == ISD::MUL) {
4178     if (isa<ConstantSDNode>(LHS)) {
4179       std::swap(LHS, RHS);
4180     }
4181   }
4182 
4183   // If we have a SHL, determine the actual multiply amount
4184   if (N->getOpcode() == ISD::SHL) {
4185     ConstantSDNode *ShlRHS = dyn_cast<ConstantSDNode>(RHS);
4186     if (!ShlRHS) {
4187       return SDValue();
4188     }
4189 
4190     APInt ShiftAmt = ShlRHS->getAPIntValue();
4191     unsigned BitWidth = MulType.getSizeInBits();
4192     if (ShiftAmt.sge(0) && ShiftAmt.slt(BitWidth)) {
4193       APInt MulVal = APInt(BitWidth, 1) << ShiftAmt;
4194       RHS = DCI.DAG.getConstant(MulVal, DL, MulType);
4195     } else {
4196       return SDValue();
4197     }
4198   }
4199 
4200   bool Signed;
4201   // Verify that our operands are demotable
4202   if (!AreMulWideOperandsDemotable(LHS, RHS, OptSize, Signed)) {
4203     return SDValue();
4204   }
4205 
4206   EVT DemotedVT;
4207   if (MulType == MVT::i32) {
4208     DemotedVT = MVT::i16;
4209   } else {
4210     DemotedVT = MVT::i32;
4211   }
4212 
4213   // Truncate the operands to the correct size. Note that these are just for
4214   // type consistency and will (likely) be eliminated in later phases.
4215   SDValue TruncLHS =
4216     DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, LHS);
4217   SDValue TruncRHS =
4218     DCI.DAG.getNode(ISD::TRUNCATE, DL, DemotedVT, RHS);
4219 
4220   unsigned Opc;
4221   if (Signed) {
4222     Opc = NVPTXISD::MUL_WIDE_SIGNED;
4223   } else {
4224     Opc = NVPTXISD::MUL_WIDE_UNSIGNED;
4225   }
4226 
4227   return DCI.DAG.getNode(Opc, DL, MulType, TruncLHS, TruncRHS);
4228 }
4229 
4230 /// PerformMULCombine - Runs PTX-specific DAG combine patterns on MUL nodes.
4231 static SDValue PerformMULCombine(SDNode *N,
4232                                  TargetLowering::DAGCombinerInfo &DCI,
4233                                  CodeGenOpt::Level OptLevel) {
4234   if (OptLevel > 0) {
4235     // Try mul.wide combining at OptLevel > 0
4236     if (SDValue Ret = TryMULWIDECombine(N, DCI))
4237       return Ret;
4238   }
4239 
4240   return SDValue();
4241 }
4242 
4243 /// PerformSHLCombine - Runs PTX-specific DAG combine patterns on SHL nodes.
4244 static SDValue PerformSHLCombine(SDNode *N,
4245                                  TargetLowering::DAGCombinerInfo &DCI,
4246                                  CodeGenOpt::Level OptLevel) {
4247   if (OptLevel > 0) {
4248     // Try mul.wide combining at OptLevel > 0
4249     if (SDValue Ret = TryMULWIDECombine(N, DCI))
4250       return Ret;
4251   }
4252 
4253   return SDValue();
4254 }
4255 
4256 SDValue NVPTXTargetLowering::PerformDAGCombine(SDNode *N,
4257                                                DAGCombinerInfo &DCI) const {
4258   CodeGenOpt::Level OptLevel = getTargetMachine().getOptLevel();
4259   switch (N->getOpcode()) {
4260     default: break;
4261     case ISD::ADD:
4262     case ISD::FADD:
4263       return PerformADDCombine(N, DCI, STI, OptLevel);
4264     case ISD::MUL:
4265       return PerformMULCombine(N, DCI, OptLevel);
4266     case ISD::SHL:
4267       return PerformSHLCombine(N, DCI, OptLevel);
4268     case ISD::AND:
4269       return PerformANDCombine(N, DCI);
4270     case ISD::SELECT:
4271       return PerformSELECTCombine(N, DCI);
4272   }
4273   return SDValue();
4274 }
4275 
4276 /// ReplaceVectorLoad - Convert vector loads into multi-output scalar loads.
4277 static void ReplaceLoadVector(SDNode *N, SelectionDAG &DAG,
4278                               SmallVectorImpl<SDValue> &Results) {
4279   EVT ResVT = N->getValueType(0);
4280   SDLoc DL(N);
4281 
4282   assert(ResVT.isVector() && "Vector load must have vector type");
4283 
4284   // We only handle "native" vector sizes for now, e.g. <4 x double> is not
4285   // legal.  We can (and should) split that into 2 loads of <2 x double> here
4286   // but I'm leaving that as a TODO for now.
4287   assert(ResVT.isSimple() && "Can only handle simple types");
4288   switch (ResVT.getSimpleVT().SimpleTy) {
4289   default:
4290     return;
4291   case MVT::v2i8:
4292   case MVT::v2i16:
4293   case MVT::v2i32:
4294   case MVT::v2i64:
4295   case MVT::v2f32:
4296   case MVT::v2f64:
4297   case MVT::v4i8:
4298   case MVT::v4i16:
4299   case MVT::v4i32:
4300   case MVT::v4f32:
4301     // This is a "native" vector type
4302     break;
4303   }
4304 
4305   LoadSDNode *LD = cast<LoadSDNode>(N);
4306 
4307   unsigned Align = LD->getAlignment();
4308   auto &TD = DAG.getDataLayout();
4309   unsigned PrefAlign =
4310       TD.getPrefTypeAlignment(ResVT.getTypeForEVT(*DAG.getContext()));
4311   if (Align < PrefAlign) {
4312     // This load is not sufficiently aligned, so bail out and let this vector
4313     // load be scalarized.  Note that we may still be able to emit smaller
4314     // vector loads.  For example, if we are loading a <4 x float> with an
4315     // alignment of 8, this check will fail but the legalizer will try again
4316     // with 2 x <2 x float>, which will succeed with an alignment of 8.
4317     return;
4318   }
4319 
4320   EVT EltVT = ResVT.getVectorElementType();
4321   unsigned NumElts = ResVT.getVectorNumElements();
4322 
4323   // Since LoadV2 is a target node, we cannot rely on DAG type legalization.
4324   // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
4325   // loaded type to i16 and propagate the "real" type as the memory type.
4326   bool NeedTrunc = false;
4327   if (EltVT.getSizeInBits() < 16) {
4328     EltVT = MVT::i16;
4329     NeedTrunc = true;
4330   }
4331 
4332   unsigned Opcode = 0;
4333   SDVTList LdResVTs;
4334 
4335   switch (NumElts) {
4336   default:
4337     return;
4338   case 2:
4339     Opcode = NVPTXISD::LoadV2;
4340     LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4341     break;
4342   case 4: {
4343     Opcode = NVPTXISD::LoadV4;
4344     EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4345     LdResVTs = DAG.getVTList(ListVTs);
4346     break;
4347   }
4348   }
4349 
4350   // Copy regular operands
4351   SmallVector<SDValue, 8> OtherOps(N->op_begin(), N->op_end());
4352 
4353   // The select routine does not have access to the LoadSDNode instance, so
4354   // pass along the extension information
4355   OtherOps.push_back(DAG.getIntPtrConstant(LD->getExtensionType(), DL));
4356 
4357   SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4358                                           LD->getMemoryVT(),
4359                                           LD->getMemOperand());
4360 
4361   SmallVector<SDValue, 4> ScalarRes;
4362 
4363   for (unsigned i = 0; i < NumElts; ++i) {
4364     SDValue Res = NewLD.getValue(i);
4365     if (NeedTrunc)
4366       Res = DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4367     ScalarRes.push_back(Res);
4368   }
4369 
4370   SDValue LoadChain = NewLD.getValue(NumElts);
4371 
4372   SDValue BuildVec = DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4373 
4374   Results.push_back(BuildVec);
4375   Results.push_back(LoadChain);
4376 }
4377 
4378 static void ReplaceINTRINSIC_W_CHAIN(SDNode *N, SelectionDAG &DAG,
4379                                      SmallVectorImpl<SDValue> &Results) {
4380   SDValue Chain = N->getOperand(0);
4381   SDValue Intrin = N->getOperand(1);
4382   SDLoc DL(N);
4383 
4384   // Get the intrinsic ID
4385   unsigned IntrinNo = cast<ConstantSDNode>(Intrin.getNode())->getZExtValue();
4386   switch (IntrinNo) {
4387   default:
4388     return;
4389   case Intrinsic::nvvm_ldg_global_i:
4390   case Intrinsic::nvvm_ldg_global_f:
4391   case Intrinsic::nvvm_ldg_global_p:
4392   case Intrinsic::nvvm_ldu_global_i:
4393   case Intrinsic::nvvm_ldu_global_f:
4394   case Intrinsic::nvvm_ldu_global_p: {
4395     EVT ResVT = N->getValueType(0);
4396 
4397     if (ResVT.isVector()) {
4398       // Vector LDG/LDU
4399 
4400       unsigned NumElts = ResVT.getVectorNumElements();
4401       EVT EltVT = ResVT.getVectorElementType();
4402 
4403       // Since LDU/LDG are target nodes, we cannot rely on DAG type
4404       // legalization.
4405       // Therefore, we must ensure the type is legal.  For i1 and i8, we set the
4406       // loaded type to i16 and propagate the "real" type as the memory type.
4407       bool NeedTrunc = false;
4408       if (EltVT.getSizeInBits() < 16) {
4409         EltVT = MVT::i16;
4410         NeedTrunc = true;
4411       }
4412 
4413       unsigned Opcode = 0;
4414       SDVTList LdResVTs;
4415 
4416       switch (NumElts) {
4417       default:
4418         return;
4419       case 2:
4420         switch (IntrinNo) {
4421         default:
4422           return;
4423         case Intrinsic::nvvm_ldg_global_i:
4424         case Intrinsic::nvvm_ldg_global_f:
4425         case Intrinsic::nvvm_ldg_global_p:
4426           Opcode = NVPTXISD::LDGV2;
4427           break;
4428         case Intrinsic::nvvm_ldu_global_i:
4429         case Intrinsic::nvvm_ldu_global_f:
4430         case Intrinsic::nvvm_ldu_global_p:
4431           Opcode = NVPTXISD::LDUV2;
4432           break;
4433         }
4434         LdResVTs = DAG.getVTList(EltVT, EltVT, MVT::Other);
4435         break;
4436       case 4: {
4437         switch (IntrinNo) {
4438         default:
4439           return;
4440         case Intrinsic::nvvm_ldg_global_i:
4441         case Intrinsic::nvvm_ldg_global_f:
4442         case Intrinsic::nvvm_ldg_global_p:
4443           Opcode = NVPTXISD::LDGV4;
4444           break;
4445         case Intrinsic::nvvm_ldu_global_i:
4446         case Intrinsic::nvvm_ldu_global_f:
4447         case Intrinsic::nvvm_ldu_global_p:
4448           Opcode = NVPTXISD::LDUV4;
4449           break;
4450         }
4451         EVT ListVTs[] = { EltVT, EltVT, EltVT, EltVT, MVT::Other };
4452         LdResVTs = DAG.getVTList(ListVTs);
4453         break;
4454       }
4455       }
4456 
4457       SmallVector<SDValue, 8> OtherOps;
4458 
4459       // Copy regular operands
4460 
4461       OtherOps.push_back(Chain); // Chain
4462                                  // Skip operand 1 (intrinsic ID)
4463       // Others
4464       OtherOps.append(N->op_begin() + 2, N->op_end());
4465 
4466       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4467 
4468       SDValue NewLD = DAG.getMemIntrinsicNode(Opcode, DL, LdResVTs, OtherOps,
4469                                               MemSD->getMemoryVT(),
4470                                               MemSD->getMemOperand());
4471 
4472       SmallVector<SDValue, 4> ScalarRes;
4473 
4474       for (unsigned i = 0; i < NumElts; ++i) {
4475         SDValue Res = NewLD.getValue(i);
4476         if (NeedTrunc)
4477           Res =
4478               DAG.getNode(ISD::TRUNCATE, DL, ResVT.getVectorElementType(), Res);
4479         ScalarRes.push_back(Res);
4480       }
4481 
4482       SDValue LoadChain = NewLD.getValue(NumElts);
4483 
4484       SDValue BuildVec =
4485           DAG.getNode(ISD::BUILD_VECTOR, DL, ResVT, ScalarRes);
4486 
4487       Results.push_back(BuildVec);
4488       Results.push_back(LoadChain);
4489     } else {
4490       // i8 LDG/LDU
4491       assert(ResVT.isSimple() && ResVT.getSimpleVT().SimpleTy == MVT::i8 &&
4492              "Custom handling of non-i8 ldu/ldg?");
4493 
4494       // Just copy all operands as-is
4495       SmallVector<SDValue, 4> Ops(N->op_begin(), N->op_end());
4496 
4497       // Force output to i16
4498       SDVTList LdResVTs = DAG.getVTList(MVT::i16, MVT::Other);
4499 
4500       MemIntrinsicSDNode *MemSD = cast<MemIntrinsicSDNode>(N);
4501 
4502       // We make sure the memory type is i8, which will be used during isel
4503       // to select the proper instruction.
4504       SDValue NewLD =
4505           DAG.getMemIntrinsicNode(ISD::INTRINSIC_W_CHAIN, DL, LdResVTs, Ops,
4506                                   MVT::i8, MemSD->getMemOperand());
4507 
4508       Results.push_back(DAG.getNode(ISD::TRUNCATE, DL, MVT::i8,
4509                                     NewLD.getValue(0)));
4510       Results.push_back(NewLD.getValue(1));
4511     }
4512   }
4513   }
4514 }
4515 
4516 void NVPTXTargetLowering::ReplaceNodeResults(
4517     SDNode *N, SmallVectorImpl<SDValue> &Results, SelectionDAG &DAG) const {
4518   switch (N->getOpcode()) {
4519   default:
4520     report_fatal_error("Unhandled custom legalization");
4521   case ISD::LOAD:
4522     ReplaceLoadVector(N, DAG, Results);
4523     return;
4524   case ISD::INTRINSIC_W_CHAIN:
4525     ReplaceINTRINSIC_W_CHAIN(N, DAG, Results);
4526     return;
4527   }
4528 }
4529 
4530 // Pin NVPTXSection's and NVPTXTargetObjectFile's vtables to this file.
4531 void NVPTXSection::anchor() {}
4532 
4533 NVPTXTargetObjectFile::~NVPTXTargetObjectFile() {
4534   delete static_cast<NVPTXSection *>(TextSection);
4535   delete static_cast<NVPTXSection *>(DataSection);
4536   delete static_cast<NVPTXSection *>(BSSSection);
4537   delete static_cast<NVPTXSection *>(ReadOnlySection);
4538 
4539   delete static_cast<NVPTXSection *>(StaticCtorSection);
4540   delete static_cast<NVPTXSection *>(StaticDtorSection);
4541   delete static_cast<NVPTXSection *>(LSDASection);
4542   delete static_cast<NVPTXSection *>(EHFrameSection);
4543   delete static_cast<NVPTXSection *>(DwarfAbbrevSection);
4544   delete static_cast<NVPTXSection *>(DwarfInfoSection);
4545   delete static_cast<NVPTXSection *>(DwarfLineSection);
4546   delete static_cast<NVPTXSection *>(DwarfFrameSection);
4547   delete static_cast<NVPTXSection *>(DwarfPubTypesSection);
4548   delete static_cast<const NVPTXSection *>(DwarfDebugInlineSection);
4549   delete static_cast<NVPTXSection *>(DwarfStrSection);
4550   delete static_cast<NVPTXSection *>(DwarfLocSection);
4551   delete static_cast<NVPTXSection *>(DwarfARangesSection);
4552   delete static_cast<NVPTXSection *>(DwarfRangesSection);
4553   delete static_cast<NVPTXSection *>(DwarfMacinfoSection);
4554 }
4555 
4556 MCSection *
4557 NVPTXTargetObjectFile::SelectSectionForGlobal(const GlobalValue *GV,
4558                                               SectionKind Kind, Mangler &Mang,
4559                                               const TargetMachine &TM) const {
4560   return getDataSection();
4561 }
4562