1 //===-- MipsTargetMachine.h - Define TargetMachine for Mips -00--*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file declares the Mips specific subclass of TargetMachine. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #ifndef MIPSTARGETMACHINE_H 15 #define MIPSTARGETMACHINE_H 16 17 #include "MipsSubtarget.h" 18 #include "MipsInstrInfo.h" 19 #include "MipsISelLowering.h" 20 #include "MipsFrameLowering.h" 21 #include "MipsSelectionDAGInfo.h" 22 #include "llvm/Target/TargetMachine.h" 23 #include "llvm/Target/TargetData.h" 24 #include "llvm/Target/TargetFrameLowering.h" 25 #include "MipsJITInfo.h" 26 27 namespace llvm { 28 class formatted_raw_ostream; 29 30 class MipsTargetMachine : public LLVMTargetMachine { 31 MipsSubtarget Subtarget; 32 const TargetData DataLayout; // Calculates type size & alignment 33 MipsInstrInfo InstrInfo; 34 MipsFrameLowering FrameLowering; 35 MipsTargetLowering TLInfo; 36 MipsSelectionDAGInfo TSInfo; 37 MipsJITInfo JITInfo; 38 39 public: 40 MipsTargetMachine(const Target &T, StringRef TT, 41 StringRef CPU, StringRef FS, 42 Reloc::Model RM, CodeModel::Model CM, 43 CodeGenOpt::Level OL, 44 bool isLittle); 45 46 virtual const MipsInstrInfo *getInstrInfo() const 47 { return &InstrInfo; } 48 virtual const TargetFrameLowering *getFrameLowering() const 49 { return &FrameLowering; } 50 virtual const MipsSubtarget *getSubtargetImpl() const 51 { return &Subtarget; } 52 virtual const TargetData *getTargetData() const 53 { return &DataLayout;} 54 virtual MipsJITInfo *getJITInfo() 55 { return &JITInfo; } 56 57 58 virtual const MipsRegisterInfo *getRegisterInfo() const { 59 return &InstrInfo.getRegisterInfo(); 60 } 61 62 virtual const MipsTargetLowering *getTargetLowering() const { 63 return &TLInfo; 64 } 65 66 virtual const MipsSelectionDAGInfo* getSelectionDAGInfo() const { 67 return &TSInfo; 68 } 69 70 // Pass Pipeline Configuration 71 virtual bool addInstSelector(PassManagerBase &PM); 72 virtual bool addPreEmitPass(PassManagerBase &PM); 73 virtual bool addPreRegAlloc(PassManagerBase &PM); 74 virtual bool addPostRegAlloc(PassManagerBase &); 75 virtual bool addCodeEmitter(PassManagerBase &PM, 76 JITCodeEmitter &JCE); 77 78 }; 79 80 /// MipsebTargetMachine - Mips32 big endian target machine. 81 /// 82 class MipsebTargetMachine : public MipsTargetMachine { 83 public: 84 MipsebTargetMachine(const Target &T, StringRef TT, 85 StringRef CPU, StringRef FS, 86 Reloc::Model RM, CodeModel::Model CM, 87 CodeGenOpt::Level OL); 88 }; 89 90 /// MipselTargetMachine - Mips32 little endian target machine. 91 /// 92 class MipselTargetMachine : public MipsTargetMachine { 93 public: 94 MipselTargetMachine(const Target &T, StringRef TT, 95 StringRef CPU, StringRef FS, 96 Reloc::Model RM, CodeModel::Model CM, 97 CodeGenOpt::Level OL); 98 }; 99 100 /// Mips64ebTargetMachine - Mips64 big endian target machine. 101 /// 102 class Mips64ebTargetMachine : public MipsTargetMachine { 103 public: 104 Mips64ebTargetMachine(const Target &T, StringRef TT, 105 StringRef CPU, StringRef FS, 106 Reloc::Model RM, CodeModel::Model CM, 107 CodeGenOpt::Level OL); 108 }; 109 110 /// Mips64elTargetMachine - Mips64 little endian target machine. 111 /// 112 class Mips64elTargetMachine : public MipsTargetMachine { 113 public: 114 Mips64elTargetMachine(const Target &T, StringRef TT, 115 StringRef CPU, StringRef FS, 116 Reloc::Model RM, CodeModel::Model CM, 117 CodeGenOpt::Level OL); 118 }; 119 } // End llvm namespace 120 121 #endif 122