1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsTargetMachine.h" 15 #include "MCTargetDesc/MipsABIInfo.h" 16 #include "MCTargetDesc/MipsMCTargetDesc.h" 17 #include "Mips.h" 18 #include "Mips16ISelDAGToDAG.h" 19 #include "MipsSEISelDAGToDAG.h" 20 #include "MipsSubtarget.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 27 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 30 #include "llvm/CodeGen/BasicTTIImpl.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/CodeGen/Passes.h" 33 #include "llvm/CodeGen/TargetPassConfig.h" 34 #include "llvm/IR/Attributes.h" 35 #include "llvm/IR/Function.h" 36 #include "llvm/Support/CodeGen.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/TargetRegistry.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetOptions.h" 41 #include <string> 42 43 using namespace llvm; 44 45 #define DEBUG_TYPE "mips" 46 47 extern "C" void LLVMInitializeMipsTarget() { 48 // Register the target. 49 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); 50 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); 51 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); 52 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); 53 54 PassRegistry *PR = PassRegistry::getPassRegistry(); 55 initializeGlobalISel(*PR); 56 initializeMipsDelaySlotFillerPass(*PR); 57 initializeMipsBranchExpansionPass(*PR); 58 initializeMicroMipsSizeReducePass(*PR); 59 initializeMipsPreLegalizerCombinerPass(*PR); 60 } 61 62 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 63 const TargetOptions &Options, 64 bool isLittle) { 65 std::string Ret; 66 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); 67 68 // There are both little and big endian mips. 69 if (isLittle) 70 Ret += "e"; 71 else 72 Ret += "E"; 73 74 if (ABI.IsO32()) 75 Ret += "-m:m"; 76 else 77 Ret += "-m:e"; 78 79 // Pointers are 32 bit on some ABIs. 80 if (!ABI.IsN64()) 81 Ret += "-p:32:32"; 82 83 // 8 and 16 bit integers only need to have natural alignment, but try to 84 // align them to 32 bits. 64 bit integers have natural alignment. 85 Ret += "-i8:8:32-i16:16:32-i64:64"; 86 87 // 32 bit registers are always available and the stack is at least 64 bit 88 // aligned. On N64 64 bit registers are also available and the stack is 89 // 128 bit aligned. 90 if (ABI.IsN64() || ABI.IsN32()) 91 Ret += "-n32:64-S128"; 92 else 93 Ret += "-n32-S64"; 94 95 return Ret; 96 } 97 98 static Reloc::Model getEffectiveRelocModel(bool JIT, 99 Optional<Reloc::Model> RM) { 100 if (!RM.hasValue() || JIT) 101 return Reloc::Static; 102 return *RM; 103 } 104 105 // On function prologue, the stack is created by decrementing 106 // its pointer. Once decremented, all references are done with positive 107 // offset from the stack/frame pointer, using StackGrowsUp enables 108 // an easier handling. 109 // Using CodeModel::Large enables different CALL behavior. 110 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, 111 StringRef CPU, StringRef FS, 112 const TargetOptions &Options, 113 Optional<Reloc::Model> RM, 114 Optional<CodeModel::Model> CM, 115 CodeGenOpt::Level OL, bool JIT, 116 bool isLittle) 117 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 118 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), 119 getEffectiveCodeModel(CM, CodeModel::Small), OL), 120 isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()), 121 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), 122 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, 123 Options.StackAlignmentOverride), 124 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", 125 isLittle, *this, Options.StackAlignmentOverride), 126 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", 127 isLittle, *this, Options.StackAlignmentOverride) { 128 Subtarget = &DefaultSubtarget; 129 initAsmInfo(); 130 } 131 132 MipsTargetMachine::~MipsTargetMachine() = default; 133 134 void MipsebTargetMachine::anchor() {} 135 136 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, 137 StringRef CPU, StringRef FS, 138 const TargetOptions &Options, 139 Optional<Reloc::Model> RM, 140 Optional<CodeModel::Model> CM, 141 CodeGenOpt::Level OL, bool JIT) 142 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 143 144 void MipselTargetMachine::anchor() {} 145 146 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, 147 StringRef CPU, StringRef FS, 148 const TargetOptions &Options, 149 Optional<Reloc::Model> RM, 150 Optional<CodeModel::Model> CM, 151 CodeGenOpt::Level OL, bool JIT) 152 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 153 154 const MipsSubtarget * 155 MipsTargetMachine::getSubtargetImpl(const Function &F) const { 156 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 157 Attribute FSAttr = F.getFnAttribute("target-features"); 158 159 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 160 ? CPUAttr.getValueAsString().str() 161 : TargetCPU; 162 std::string FS = !FSAttr.hasAttribute(Attribute::None) 163 ? FSAttr.getValueAsString().str() 164 : TargetFS; 165 bool hasMips16Attr = 166 !F.getFnAttribute("mips16").hasAttribute(Attribute::None); 167 bool hasNoMips16Attr = 168 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None); 169 170 bool HasMicroMipsAttr = 171 !F.getFnAttribute("micromips").hasAttribute(Attribute::None); 172 bool HasNoMicroMipsAttr = 173 !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None); 174 175 // FIXME: This is related to the code below to reset the target options, 176 // we need to know whether or not the soft float flag is set on the 177 // function, so we can enable it as a subtarget feature. 178 bool softFloat = 179 F.hasFnAttribute("use-soft-float") && 180 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 181 182 if (hasMips16Attr) 183 FS += FS.empty() ? "+mips16" : ",+mips16"; 184 else if (hasNoMips16Attr) 185 FS += FS.empty() ? "-mips16" : ",-mips16"; 186 if (HasMicroMipsAttr) 187 FS += FS.empty() ? "+micromips" : ",+micromips"; 188 else if (HasNoMicroMipsAttr) 189 FS += FS.empty() ? "-micromips" : ",-micromips"; 190 if (softFloat) 191 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 192 193 auto &I = SubtargetMap[CPU + FS]; 194 if (!I) { 195 // This needs to be done before we create a new subtarget since any 196 // creation will depend on the TM and the code generation flags on the 197 // function that reside in TargetOptions. 198 resetTargetOptions(F); 199 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this, 200 Options.StackAlignmentOverride); 201 } 202 return I.get(); 203 } 204 205 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { 206 LLVM_DEBUG(dbgs() << "resetSubtarget\n"); 207 208 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(MF->getFunction())); 209 MF->setSubtarget(Subtarget); 210 } 211 212 namespace { 213 214 /// Mips Code Generator Pass Configuration Options. 215 class MipsPassConfig : public TargetPassConfig { 216 public: 217 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) 218 : TargetPassConfig(TM, PM) { 219 // The current implementation of long branch pass requires a scratch 220 // register ($at) to be available before branch instructions. Tail merging 221 // can break this requirement, so disable it when long branch pass is 222 // enabled. 223 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 224 } 225 226 MipsTargetMachine &getMipsTargetMachine() const { 227 return getTM<MipsTargetMachine>(); 228 } 229 230 const MipsSubtarget &getMipsSubtarget() const { 231 return *getMipsTargetMachine().getSubtargetImpl(); 232 } 233 234 void addIRPasses() override; 235 bool addInstSelector() override; 236 void addPreEmitPass() override; 237 void addPreRegAlloc() override; 238 bool addIRTranslator() override; 239 void addPreLegalizeMachineIR() override; 240 bool addLegalizeMachineIR() override; 241 bool addRegBankSelect() override; 242 bool addGlobalInstructionSelect() override; 243 }; 244 245 } // end anonymous namespace 246 247 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 248 return new MipsPassConfig(*this, PM); 249 } 250 251 void MipsPassConfig::addIRPasses() { 252 TargetPassConfig::addIRPasses(); 253 addPass(createAtomicExpandPass()); 254 if (getMipsSubtarget().os16()) 255 addPass(createMipsOs16Pass()); 256 if (getMipsSubtarget().inMips16HardFloat()) 257 addPass(createMips16HardFloatPass()); 258 } 259 // Install an instruction selector pass using 260 // the ISelDag to gen Mips code. 261 bool MipsPassConfig::addInstSelector() { 262 addPass(createMipsModuleISelDagPass()); 263 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); 264 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); 265 return false; 266 } 267 268 void MipsPassConfig::addPreRegAlloc() { 269 addPass(createMipsOptimizePICCallPass()); 270 } 271 272 TargetTransformInfo 273 MipsTargetMachine::getTargetTransformInfo(const Function &F) { 274 if (Subtarget->allowMixed16_32()) { 275 LLVM_DEBUG(errs() << "No Target Transform Info Pass Added\n"); 276 // FIXME: This is no longer necessary as the TTI returned is per-function. 277 return TargetTransformInfo(F.getParent()->getDataLayout()); 278 } 279 280 LLVM_DEBUG(errs() << "Target Transform Info Pass Added\n"); 281 return TargetTransformInfo(BasicTTIImpl(this, F)); 282 } 283 284 // Implemented by targets that want to run passes immediately before 285 // machine code is emitted. return true if -print-machineinstrs should 286 // print out the code after the passes. 287 void MipsPassConfig::addPreEmitPass() { 288 // Expand pseudo instructions that are sensitive to register allocation. 289 addPass(createMipsExpandPseudoPass()); 290 291 // The microMIPS size reduction pass performs instruction reselection for 292 // instructions which can be remapped to a 16 bit instruction. 293 addPass(createMicroMipsSizeReducePass()); 294 295 // The delay slot filler pass can potientially create forbidden slot hazards 296 // for MIPSR6 and therefore it should go before MipsBranchExpansion pass. 297 addPass(createMipsDelaySlotFillerPass()); 298 299 // This pass expands branches and takes care about the forbidden slot hazards. 300 // Expanding branches may potentially create forbidden slot hazards for 301 // MIPSR6, and fixing such hazard may potentially break a branch by extending 302 // its offset out of range. That's why this pass combine these two tasks, and 303 // runs them alternately until one of them finishes without any changes. Only 304 // then we can be sure that all branches are expanded properly and no hazards 305 // exists. 306 // Any new pass should go before this pass. 307 addPass(createMipsBranchExpansion()); 308 309 addPass(createMipsConstantIslandPass()); 310 } 311 312 bool MipsPassConfig::addIRTranslator() { 313 addPass(new IRTranslator()); 314 return false; 315 } 316 317 void MipsPassConfig::addPreLegalizeMachineIR() { 318 addPass(createMipsPreLegalizeCombiner()); 319 } 320 321 bool MipsPassConfig::addLegalizeMachineIR() { 322 addPass(new Legalizer()); 323 return false; 324 } 325 326 bool MipsPassConfig::addRegBankSelect() { 327 addPass(new RegBankSelect()); 328 return false; 329 } 330 331 bool MipsPassConfig::addGlobalInstructionSelect() { 332 addPass(new InstructionSelect()); 333 return false; 334 } 335