1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MCTargetDesc/MipsABIInfo.h" 15 #include "MCTargetDesc/MipsMCTargetDesc.h" 16 #include "Mips.h" 17 #include "Mips16ISelDAGToDAG.h" 18 #include "MipsSEISelDAGToDAG.h" 19 #include "MipsSubtarget.h" 20 #include "MipsTargetObjectFile.h" 21 #include "MipsTargetMachine.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/BasicTTIImpl.h" 27 #include "llvm/CodeGen/MachineFunction.h" 28 #include "llvm/CodeGen/Passes.h" 29 #include "llvm/CodeGen/TargetPassConfig.h" 30 #include "llvm/IR/Attributes.h" 31 #include "llvm/IR/Function.h" 32 #include "llvm/Support/CodeGen.h" 33 #include "llvm/Support/Debug.h" 34 #include "llvm/Support/TargetRegistry.h" 35 #include "llvm/Support/raw_ostream.h" 36 #include "llvm/Target/TargetOptions.h" 37 #include <string> 38 39 using namespace llvm; 40 41 #define DEBUG_TYPE "mips" 42 43 extern "C" void LLVMInitializeMipsTarget() { 44 // Register the target. 45 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); 46 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); 47 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); 48 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); 49 } 50 51 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 52 const TargetOptions &Options, 53 bool isLittle) { 54 std::string Ret; 55 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); 56 57 // There are both little and big endian mips. 58 if (isLittle) 59 Ret += "e"; 60 else 61 Ret += "E"; 62 63 if (ABI.IsO32()) 64 Ret += "-m:m"; 65 else 66 Ret += "-m:e"; 67 68 // Pointers are 32 bit on some ABIs. 69 if (!ABI.IsN64()) 70 Ret += "-p:32:32"; 71 72 // 8 and 16 bit integers only need to have natural alignment, but try to 73 // align them to 32 bits. 64 bit integers have natural alignment. 74 Ret += "-i8:8:32-i16:16:32-i64:64"; 75 76 // 32 bit registers are always available and the stack is at least 64 bit 77 // aligned. On N64 64 bit registers are also available and the stack is 78 // 128 bit aligned. 79 if (ABI.IsN64() || ABI.IsN32()) 80 Ret += "-n32:64-S128"; 81 else 82 Ret += "-n32-S64"; 83 84 return Ret; 85 } 86 87 static Reloc::Model getEffectiveRelocModel(CodeModel::Model CM, 88 Optional<Reloc::Model> RM) { 89 if (!RM.hasValue() || CM == CodeModel::JITDefault) 90 return Reloc::Static; 91 return *RM; 92 } 93 94 // On function prologue, the stack is created by decrementing 95 // its pointer. Once decremented, all references are done with positive 96 // offset from the stack/frame pointer, using StackGrowsUp enables 97 // an easier handling. 98 // Using CodeModel::Large enables different CALL behavior. 99 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, 100 StringRef CPU, StringRef FS, 101 const TargetOptions &Options, 102 Optional<Reloc::Model> RM, 103 CodeModel::Model CM, CodeGenOpt::Level OL, 104 bool isLittle) 105 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 106 CPU, FS, Options, getEffectiveRelocModel(CM, RM), CM, 107 OL), 108 isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()), 109 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), 110 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this), 111 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", 112 isLittle, *this), 113 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", 114 isLittle, *this) { 115 Subtarget = &DefaultSubtarget; 116 initAsmInfo(); 117 } 118 119 MipsTargetMachine::~MipsTargetMachine() = default; 120 121 void MipsebTargetMachine::anchor() {} 122 123 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, 124 StringRef CPU, StringRef FS, 125 const TargetOptions &Options, 126 Optional<Reloc::Model> RM, 127 CodeModel::Model CM, 128 CodeGenOpt::Level OL) 129 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {} 130 131 void MipselTargetMachine::anchor() {} 132 133 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, 134 StringRef CPU, StringRef FS, 135 const TargetOptions &Options, 136 Optional<Reloc::Model> RM, 137 CodeModel::Model CM, 138 CodeGenOpt::Level OL) 139 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {} 140 141 const MipsSubtarget * 142 MipsTargetMachine::getSubtargetImpl(const Function &F) const { 143 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 144 Attribute FSAttr = F.getFnAttribute("target-features"); 145 146 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 147 ? CPUAttr.getValueAsString().str() 148 : TargetCPU; 149 std::string FS = !FSAttr.hasAttribute(Attribute::None) 150 ? FSAttr.getValueAsString().str() 151 : TargetFS; 152 bool hasMips16Attr = 153 !F.getFnAttribute("mips16").hasAttribute(Attribute::None); 154 bool hasNoMips16Attr = 155 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None); 156 157 // FIXME: This is related to the code below to reset the target options, 158 // we need to know whether or not the soft float flag is set on the 159 // function, so we can enable it as a subtarget feature. 160 bool softFloat = 161 F.hasFnAttribute("use-soft-float") && 162 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 163 164 if (hasMips16Attr) 165 FS += FS.empty() ? "+mips16" : ",+mips16"; 166 else if (hasNoMips16Attr) 167 FS += FS.empty() ? "-mips16" : ",-mips16"; 168 if (softFloat) 169 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 170 171 auto &I = SubtargetMap[CPU + FS]; 172 if (!I) { 173 // This needs to be done before we create a new subtarget since any 174 // creation will depend on the TM and the code generation flags on the 175 // function that reside in TargetOptions. 176 resetTargetOptions(F); 177 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, 178 *this); 179 } 180 return I.get(); 181 } 182 183 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { 184 DEBUG(dbgs() << "resetSubtarget\n"); 185 186 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction())); 187 MF->setSubtarget(Subtarget); 188 } 189 190 namespace { 191 192 /// Mips Code Generator Pass Configuration Options. 193 class MipsPassConfig : public TargetPassConfig { 194 public: 195 MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM) 196 : TargetPassConfig(TM, PM) { 197 // The current implementation of long branch pass requires a scratch 198 // register ($at) to be available before branch instructions. Tail merging 199 // can break this requirement, so disable it when long branch pass is 200 // enabled. 201 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 202 } 203 204 MipsTargetMachine &getMipsTargetMachine() const { 205 return getTM<MipsTargetMachine>(); 206 } 207 208 const MipsSubtarget &getMipsSubtarget() const { 209 return *getMipsTargetMachine().getSubtargetImpl(); 210 } 211 212 void addIRPasses() override; 213 bool addInstSelector() override; 214 void addPreEmitPass() override; 215 void addPreRegAlloc() override; 216 void addPreSched2() override; 217 }; 218 219 } // end anonymous namespace 220 221 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 222 return new MipsPassConfig(this, PM); 223 } 224 225 void MipsPassConfig::addIRPasses() { 226 TargetPassConfig::addIRPasses(); 227 addPass(createAtomicExpandPass(&getMipsTargetMachine())); 228 if (getMipsSubtarget().os16()) 229 addPass(createMipsOs16Pass(getMipsTargetMachine())); 230 if (getMipsSubtarget().inMips16HardFloat()) 231 addPass(createMips16HardFloatPass(getMipsTargetMachine())); 232 } 233 // Install an instruction selector pass using 234 // the ISelDag to gen Mips code. 235 bool MipsPassConfig::addInstSelector() { 236 addPass(createMipsModuleISelDagPass(getMipsTargetMachine())); 237 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); 238 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); 239 return false; 240 } 241 242 void MipsPassConfig::addPreRegAlloc() { 243 addPass(createMipsOptimizePICCallPass(getMipsTargetMachine())); 244 } 245 246 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() { 247 return TargetIRAnalysis([this](const Function &F) { 248 if (Subtarget->allowMixed16_32()) { 249 DEBUG(errs() << "No Target Transform Info Pass Added\n"); 250 // FIXME: This is no longer necessary as the TTI returned is per-function. 251 return TargetTransformInfo(F.getParent()->getDataLayout()); 252 } 253 254 DEBUG(errs() << "Target Transform Info Pass Added\n"); 255 return TargetTransformInfo(BasicTTIImpl(this, F)); 256 }); 257 } 258 259 // Implemented by targets that want to run passes immediately before 260 // machine code is emitted. return true if -print-machineinstrs should 261 // print out the code after the passes. 262 void MipsPassConfig::addPreEmitPass() { 263 MipsTargetMachine &TM = getMipsTargetMachine(); 264 265 // The delay slot filler pass can potientially create forbidden slot (FS) 266 // hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any 267 // (new) pass that creates compact branches after the HSP must handle FS 268 // hazards itself or be pipelined before the HSP. 269 addPass(createMipsDelaySlotFillerPass(TM)); 270 addPass(createMipsHazardSchedule()); 271 addPass(createMipsLongBranchPass(TM)); 272 addPass(createMipsConstantIslandPass()); 273 } 274 275 void MipsPassConfig::addPreSched2() { 276 addPass(createMipsExpandPseudoPass()); 277 } 278