1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetMachine.h"
15 #include "Mips.h"
16 #include "MipsFrameLowering.h"
17 #include "MipsInstrInfo.h"
18 #include "llvm/PassManager.h"
19 #include "llvm/CodeGen/Passes.h"
20 #include "llvm/Support/TargetRegistry.h"
21 using namespace llvm;
22 
23 extern "C" void LLVMInitializeMipsTarget() {
24   // Register the target.
25   RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
26   RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
27   RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
28   RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
29 }
30 
31 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
32 // The stack is always 8 byte aligned
33 // On function prologue, the stack is created by decrementing
34 // its pointer. Once decremented, all references are done with positive
35 // offset from the stack/frame pointer, using StackGrowsUp enables
36 // an easier handling.
37 // Using CodeModel::Large enables different CALL behavior.
38 MipsTargetMachine::
39 MipsTargetMachine(const Target &T, StringRef TT,
40                   StringRef CPU, StringRef FS, const TargetOptions &Options,
41                   Reloc::Model RM, CodeModel::Model CM,
42                   CodeGenOpt::Level OL,
43                   bool isLittle)
44   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
45     Subtarget(TT, CPU, FS, isLittle),
46     DataLayout(isLittle ?
47                (Subtarget.isABI_N64() ?
48                 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
49                 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
50                (Subtarget.isABI_N64() ?
51                 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
52                 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
53     InstrInfo(MipsInstrInfo::create(*this)),
54     FrameLowering(MipsFrameLowering::create(*this, Subtarget)),
55     TLInfo(*this), TSInfo(*this), JITInfo() {
56 }
57 
58 void MipsebTargetMachine::anchor() { }
59 
60 MipsebTargetMachine::
61 MipsebTargetMachine(const Target &T, StringRef TT,
62                     StringRef CPU, StringRef FS, const TargetOptions &Options,
63                     Reloc::Model RM, CodeModel::Model CM,
64                     CodeGenOpt::Level OL)
65   : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
66 
67 void MipselTargetMachine::anchor() { }
68 
69 MipselTargetMachine::
70 MipselTargetMachine(const Target &T, StringRef TT,
71                     StringRef CPU, StringRef FS, const TargetOptions &Options,
72                     Reloc::Model RM, CodeModel::Model CM,
73                     CodeGenOpt::Level OL)
74   : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
75 
76 namespace {
77 /// Mips Code Generator Pass Configuration Options.
78 class MipsPassConfig : public TargetPassConfig {
79 public:
80   MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
81     : TargetPassConfig(TM, PM) {}
82 
83   MipsTargetMachine &getMipsTargetMachine() const {
84     return getTM<MipsTargetMachine>();
85   }
86 
87   const MipsSubtarget &getMipsSubtarget() const {
88     return *getMipsTargetMachine().getSubtargetImpl();
89   }
90 
91   virtual bool addInstSelector();
92   virtual bool addPreEmitPass();
93 };
94 } // namespace
95 
96 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
97   return new MipsPassConfig(this, PM);
98 }
99 
100 // Install an instruction selector pass using
101 // the ISelDag to gen Mips code.
102 bool MipsPassConfig::addInstSelector() {
103   addPass(createMipsISelDag(getMipsTargetMachine()));
104   return false;
105 }
106 
107 // Implemented by targets that want to run passes immediately before
108 // machine code is emitted. return true if -print-machineinstrs should
109 // print out the code after the passes.
110 bool MipsPassConfig::addPreEmitPass() {
111   MipsTargetMachine &TM = getMipsTargetMachine();
112   addPass(createMipsDelaySlotFillerPass(TM));
113 
114   // NOTE: long branch has not been implemented for mips16.
115   if (TM.getSubtarget<MipsSubtarget>().hasStandardEncoding())
116     addPass(createMipsLongBranchPass(TM));
117 
118   return true;
119 }
120 
121 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
122                                        JITCodeEmitter &JCE) {
123   // Machine code emitter pass for Mips.
124   PM.add(createMipsJITCodeEmitterPass(*this, JCE));
125   return false;
126 }
127