1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Implements the info about Mips target spec. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsTargetMachine.h" 15 #include "MCTargetDesc/MipsABIInfo.h" 16 #include "MCTargetDesc/MipsMCTargetDesc.h" 17 #include "Mips.h" 18 #include "Mips16ISelDAGToDAG.h" 19 #include "MipsSEISelDAGToDAG.h" 20 #include "MipsSubtarget.h" 21 #include "MipsTargetObjectFile.h" 22 #include "llvm/ADT/Optional.h" 23 #include "llvm/ADT/STLExtras.h" 24 #include "llvm/ADT/StringRef.h" 25 #include "llvm/Analysis/TargetTransformInfo.h" 26 #include "llvm/CodeGen/GlobalISel/IRTranslator.h" 27 #include "llvm/CodeGen/GlobalISel/Legalizer.h" 28 #include "llvm/CodeGen/GlobalISel/RegBankSelect.h" 29 #include "llvm/CodeGen/GlobalISel/InstructionSelect.h" 30 #include "llvm/CodeGen/BasicTTIImpl.h" 31 #include "llvm/CodeGen/MachineFunction.h" 32 #include "llvm/CodeGen/Passes.h" 33 #include "llvm/CodeGen/TargetPassConfig.h" 34 #include "llvm/IR/Attributes.h" 35 #include "llvm/IR/Function.h" 36 #include "llvm/Support/CodeGen.h" 37 #include "llvm/Support/Debug.h" 38 #include "llvm/Support/TargetRegistry.h" 39 #include "llvm/Support/raw_ostream.h" 40 #include "llvm/Target/TargetOptions.h" 41 #include <string> 42 43 using namespace llvm; 44 45 #define DEBUG_TYPE "mips" 46 47 extern "C" void LLVMInitializeMipsTarget() { 48 // Register the target. 49 RegisterTargetMachine<MipsebTargetMachine> X(getTheMipsTarget()); 50 RegisterTargetMachine<MipselTargetMachine> Y(getTheMipselTarget()); 51 RegisterTargetMachine<MipsebTargetMachine> A(getTheMips64Target()); 52 RegisterTargetMachine<MipselTargetMachine> B(getTheMips64elTarget()); 53 54 PassRegistry *PR = PassRegistry::getPassRegistry(); 55 initializeGlobalISel(*PR); 56 } 57 58 static std::string computeDataLayout(const Triple &TT, StringRef CPU, 59 const TargetOptions &Options, 60 bool isLittle) { 61 std::string Ret; 62 MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions); 63 64 // There are both little and big endian mips. 65 if (isLittle) 66 Ret += "e"; 67 else 68 Ret += "E"; 69 70 if (ABI.IsO32()) 71 Ret += "-m:m"; 72 else 73 Ret += "-m:e"; 74 75 // Pointers are 32 bit on some ABIs. 76 if (!ABI.IsN64()) 77 Ret += "-p:32:32"; 78 79 // 8 and 16 bit integers only need to have natural alignment, but try to 80 // align them to 32 bits. 64 bit integers have natural alignment. 81 Ret += "-i8:8:32-i16:16:32-i64:64"; 82 83 // 32 bit registers are always available and the stack is at least 64 bit 84 // aligned. On N64 64 bit registers are also available and the stack is 85 // 128 bit aligned. 86 if (ABI.IsN64() || ABI.IsN32()) 87 Ret += "-n32:64-S128"; 88 else 89 Ret += "-n32-S64"; 90 91 return Ret; 92 } 93 94 static Reloc::Model getEffectiveRelocModel(bool JIT, 95 Optional<Reloc::Model> RM) { 96 if (!RM.hasValue() || JIT) 97 return Reloc::Static; 98 return *RM; 99 } 100 101 static CodeModel::Model getEffectiveCodeModel(Optional<CodeModel::Model> CM) { 102 if (CM) 103 return *CM; 104 return CodeModel::Small; 105 } 106 107 // On function prologue, the stack is created by decrementing 108 // its pointer. Once decremented, all references are done with positive 109 // offset from the stack/frame pointer, using StackGrowsUp enables 110 // an easier handling. 111 // Using CodeModel::Large enables different CALL behavior. 112 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT, 113 StringRef CPU, StringRef FS, 114 const TargetOptions &Options, 115 Optional<Reloc::Model> RM, 116 Optional<CodeModel::Model> CM, 117 CodeGenOpt::Level OL, bool JIT, 118 bool isLittle) 119 : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT, 120 CPU, FS, Options, getEffectiveRelocModel(JIT, RM), 121 getEffectiveCodeModel(CM), OL), 122 isLittle(isLittle), TLOF(llvm::make_unique<MipsTargetObjectFile>()), 123 ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)), 124 Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this, 125 Options.StackAlignmentOverride), 126 NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16", 127 isLittle, *this, Options.StackAlignmentOverride), 128 Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16", 129 isLittle, *this, Options.StackAlignmentOverride) { 130 Subtarget = &DefaultSubtarget; 131 initAsmInfo(); 132 } 133 134 MipsTargetMachine::~MipsTargetMachine() = default; 135 136 void MipsebTargetMachine::anchor() {} 137 138 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT, 139 StringRef CPU, StringRef FS, 140 const TargetOptions &Options, 141 Optional<Reloc::Model> RM, 142 Optional<CodeModel::Model> CM, 143 CodeGenOpt::Level OL, bool JIT) 144 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, false) {} 145 146 void MipselTargetMachine::anchor() {} 147 148 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT, 149 StringRef CPU, StringRef FS, 150 const TargetOptions &Options, 151 Optional<Reloc::Model> RM, 152 Optional<CodeModel::Model> CM, 153 CodeGenOpt::Level OL, bool JIT) 154 : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, JIT, true) {} 155 156 const MipsSubtarget * 157 MipsTargetMachine::getSubtargetImpl(const Function &F) const { 158 Attribute CPUAttr = F.getFnAttribute("target-cpu"); 159 Attribute FSAttr = F.getFnAttribute("target-features"); 160 161 std::string CPU = !CPUAttr.hasAttribute(Attribute::None) 162 ? CPUAttr.getValueAsString().str() 163 : TargetCPU; 164 std::string FS = !FSAttr.hasAttribute(Attribute::None) 165 ? FSAttr.getValueAsString().str() 166 : TargetFS; 167 bool hasMips16Attr = 168 !F.getFnAttribute("mips16").hasAttribute(Attribute::None); 169 bool hasNoMips16Attr = 170 !F.getFnAttribute("nomips16").hasAttribute(Attribute::None); 171 172 bool HasMicroMipsAttr = 173 !F.getFnAttribute("micromips").hasAttribute(Attribute::None); 174 bool HasNoMicroMipsAttr = 175 !F.getFnAttribute("nomicromips").hasAttribute(Attribute::None); 176 177 // FIXME: This is related to the code below to reset the target options, 178 // we need to know whether or not the soft float flag is set on the 179 // function, so we can enable it as a subtarget feature. 180 bool softFloat = 181 F.hasFnAttribute("use-soft-float") && 182 F.getFnAttribute("use-soft-float").getValueAsString() == "true"; 183 184 if (hasMips16Attr) 185 FS += FS.empty() ? "+mips16" : ",+mips16"; 186 else if (hasNoMips16Attr) 187 FS += FS.empty() ? "-mips16" : ",-mips16"; 188 if (HasMicroMipsAttr) 189 FS += FS.empty() ? "+micromips" : ",+micromips"; 190 else if (HasNoMicroMipsAttr) 191 FS += FS.empty() ? "-micromips" : ",-micromips"; 192 if (softFloat) 193 FS += FS.empty() ? "+soft-float" : ",+soft-float"; 194 195 auto &I = SubtargetMap[CPU + FS]; 196 if (!I) { 197 // This needs to be done before we create a new subtarget since any 198 // creation will depend on the TM and the code generation flags on the 199 // function that reside in TargetOptions. 200 resetTargetOptions(F); 201 I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle, *this, 202 Options.StackAlignmentOverride); 203 } 204 return I.get(); 205 } 206 207 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) { 208 DEBUG(dbgs() << "resetSubtarget\n"); 209 210 Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(MF->getFunction())); 211 MF->setSubtarget(Subtarget); 212 } 213 214 namespace { 215 216 /// Mips Code Generator Pass Configuration Options. 217 class MipsPassConfig : public TargetPassConfig { 218 public: 219 MipsPassConfig(MipsTargetMachine &TM, PassManagerBase &PM) 220 : TargetPassConfig(TM, PM) { 221 // The current implementation of long branch pass requires a scratch 222 // register ($at) to be available before branch instructions. Tail merging 223 // can break this requirement, so disable it when long branch pass is 224 // enabled. 225 EnableTailMerge = !getMipsSubtarget().enableLongBranchPass(); 226 } 227 228 MipsTargetMachine &getMipsTargetMachine() const { 229 return getTM<MipsTargetMachine>(); 230 } 231 232 const MipsSubtarget &getMipsSubtarget() const { 233 return *getMipsTargetMachine().getSubtargetImpl(); 234 } 235 236 void addIRPasses() override; 237 bool addInstSelector() override; 238 void addPreEmitPass() override; 239 void addPreRegAlloc() override; 240 bool addIRTranslator() override; 241 bool addLegalizeMachineIR() override; 242 bool addRegBankSelect() override; 243 bool addGlobalInstructionSelect() override; 244 }; 245 246 } // end anonymous namespace 247 248 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) { 249 return new MipsPassConfig(*this, PM); 250 } 251 252 void MipsPassConfig::addIRPasses() { 253 TargetPassConfig::addIRPasses(); 254 addPass(createAtomicExpandPass()); 255 if (getMipsSubtarget().os16()) 256 addPass(createMipsOs16Pass()); 257 if (getMipsSubtarget().inMips16HardFloat()) 258 addPass(createMips16HardFloatPass()); 259 } 260 // Install an instruction selector pass using 261 // the ISelDag to gen Mips code. 262 bool MipsPassConfig::addInstSelector() { 263 addPass(createMipsModuleISelDagPass()); 264 addPass(createMips16ISelDag(getMipsTargetMachine(), getOptLevel())); 265 addPass(createMipsSEISelDag(getMipsTargetMachine(), getOptLevel())); 266 return false; 267 } 268 269 void MipsPassConfig::addPreRegAlloc() { 270 addPass(createMipsOptimizePICCallPass()); 271 } 272 273 TargetTransformInfo 274 MipsTargetMachine::getTargetTransformInfo(const Function &F) { 275 if (Subtarget->allowMixed16_32()) { 276 DEBUG(errs() << "No Target Transform Info Pass Added\n"); 277 // FIXME: This is no longer necessary as the TTI returned is per-function. 278 return TargetTransformInfo(F.getParent()->getDataLayout()); 279 } 280 281 DEBUG(errs() << "Target Transform Info Pass Added\n"); 282 return TargetTransformInfo(BasicTTIImpl(this, F)); 283 } 284 285 // Implemented by targets that want to run passes immediately before 286 // machine code is emitted. return true if -print-machineinstrs should 287 // print out the code after the passes. 288 void MipsPassConfig::addPreEmitPass() { 289 addPass(createMicroMipsSizeReductionPass()); 290 291 // The delay slot filler and the long branch passes can potientially create 292 // forbidden slot/ hazards for MIPSR6 which the hazard schedule pass will 293 // fix. Any new pass must come before the hazard schedule pass. 294 addPass(createMipsDelaySlotFillerPass()); 295 addPass(createMipsLongBranchPass()); 296 addPass(createMipsHazardSchedule()); 297 addPass(createMipsConstantIslandPass()); 298 } 299 300 bool MipsPassConfig::addIRTranslator() { 301 addPass(new IRTranslator()); 302 return false; 303 } 304 305 bool MipsPassConfig::addLegalizeMachineIR() { 306 addPass(new Legalizer()); 307 return false; 308 } 309 310 bool MipsPassConfig::addRegBankSelect() { 311 addPass(new RegBankSelect()); 312 return false; 313 } 314 315 bool MipsPassConfig::addGlobalInstructionSelect() { 316 addPass(new InstructionSelect()); 317 return false; 318 } 319