1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsTargetMachine.h"
15 #include "Mips.h"
16 #include "Mips16FrameLowering.h"
17 #include "Mips16ISelDAGToDAG.h"
18 #include "Mips16ISelLowering.h"
19 #include "Mips16InstrInfo.h"
20 #include "MipsFrameLowering.h"
21 #include "MipsInstrInfo.h"
22 #include "MipsSEFrameLowering.h"
23 #include "MipsSEISelDAGToDAG.h"
24 #include "MipsSEISelLowering.h"
25 #include "MipsSEInstrInfo.h"
26 #include "MipsTargetObjectFile.h"
27 #include "llvm/Analysis/TargetTransformInfo.h"
28 #include "llvm/CodeGen/Passes.h"
29 #include "llvm/CodeGen/TargetPassConfig.h"
30 #include "llvm/IR/LegacyPassManager.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/TargetRegistry.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Transforms/Scalar.h"
35 
36 using namespace llvm;
37 
38 #define DEBUG_TYPE "mips"
39 
40 extern "C" void LLVMInitializeMipsTarget() {
41   // Register the target.
42   RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
43   RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
44   RegisterTargetMachine<MipsebTargetMachine> A(TheMips64Target);
45   RegisterTargetMachine<MipselTargetMachine> B(TheMips64elTarget);
46 }
47 
48 static std::string computeDataLayout(const Triple &TT, StringRef CPU,
49                                      const TargetOptions &Options,
50                                      bool isLittle) {
51   std::string Ret = "";
52   MipsABIInfo ABI = MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions);
53 
54   // There are both little and big endian mips.
55   if (isLittle)
56     Ret += "e";
57   else
58     Ret += "E";
59 
60   Ret += "-m:m";
61 
62   // Pointers are 32 bit on some ABIs.
63   if (!ABI.IsN64())
64     Ret += "-p:32:32";
65 
66   // 8 and 16 bit integers only need to have natural alignment, but try to
67   // align them to 32 bits. 64 bit integers have natural alignment.
68   Ret += "-i8:8:32-i16:16:32-i64:64";
69 
70   // 32 bit registers are always available and the stack is at least 64 bit
71   // aligned. On N64 64 bit registers are also available and the stack is
72   // 128 bit aligned.
73   if (ABI.IsN64() || ABI.IsN32())
74     Ret += "-n32:64-S128";
75   else
76     Ret += "-n32-S64";
77 
78   return Ret;
79 }
80 
81 // On function prologue, the stack is created by decrementing
82 // its pointer. Once decremented, all references are done with positive
83 // offset from the stack/frame pointer, using StackGrowsUp enables
84 // an easier handling.
85 // Using CodeModel::Large enables different CALL behavior.
86 MipsTargetMachine::MipsTargetMachine(const Target &T, const Triple &TT,
87                                      StringRef CPU, StringRef FS,
88                                      const TargetOptions &Options,
89                                      Reloc::Model RM, CodeModel::Model CM,
90                                      CodeGenOpt::Level OL, bool isLittle)
91     : LLVMTargetMachine(T, computeDataLayout(TT, CPU, Options, isLittle), TT,
92                         CPU, FS, Options, RM, CM, OL),
93       isLittle(isLittle), TLOF(make_unique<MipsTargetObjectFile>()),
94       ABI(MipsABIInfo::computeTargetABI(TT, CPU, Options.MCOptions)),
95       Subtarget(nullptr), DefaultSubtarget(TT, CPU, FS, isLittle, *this),
96       NoMips16Subtarget(TT, CPU, FS.empty() ? "-mips16" : FS.str() + ",-mips16",
97                         isLittle, *this),
98       Mips16Subtarget(TT, CPU, FS.empty() ? "+mips16" : FS.str() + ",+mips16",
99                       isLittle, *this) {
100   Subtarget = &DefaultSubtarget;
101   initAsmInfo();
102 }
103 
104 MipsTargetMachine::~MipsTargetMachine() {}
105 
106 void MipsebTargetMachine::anchor() { }
107 
108 MipsebTargetMachine::MipsebTargetMachine(const Target &T, const Triple &TT,
109                                          StringRef CPU, StringRef FS,
110                                          const TargetOptions &Options,
111                                          Reloc::Model RM, CodeModel::Model CM,
112                                          CodeGenOpt::Level OL)
113     : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
114 
115 void MipselTargetMachine::anchor() { }
116 
117 MipselTargetMachine::MipselTargetMachine(const Target &T, const Triple &TT,
118                                          StringRef CPU, StringRef FS,
119                                          const TargetOptions &Options,
120                                          Reloc::Model RM, CodeModel::Model CM,
121                                          CodeGenOpt::Level OL)
122     : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
123 
124 const MipsSubtarget *
125 MipsTargetMachine::getSubtargetImpl(const Function &F) const {
126   Attribute CPUAttr = F.getFnAttribute("target-cpu");
127   Attribute FSAttr = F.getFnAttribute("target-features");
128 
129   std::string CPU = !CPUAttr.hasAttribute(Attribute::None)
130                         ? CPUAttr.getValueAsString().str()
131                         : TargetCPU;
132   std::string FS = !FSAttr.hasAttribute(Attribute::None)
133                        ? FSAttr.getValueAsString().str()
134                        : TargetFS;
135   bool hasMips16Attr =
136       !F.getFnAttribute("mips16").hasAttribute(Attribute::None);
137   bool hasNoMips16Attr =
138       !F.getFnAttribute("nomips16").hasAttribute(Attribute::None);
139 
140   // FIXME: This is related to the code below to reset the target options,
141   // we need to know whether or not the soft float flag is set on the
142   // function, so we can enable it as a subtarget feature.
143   bool softFloat =
144       F.hasFnAttribute("use-soft-float") &&
145       F.getFnAttribute("use-soft-float").getValueAsString() == "true";
146 
147   if (hasMips16Attr)
148     FS += FS.empty() ? "+mips16" : ",+mips16";
149   else if (hasNoMips16Attr)
150     FS += FS.empty() ? "-mips16" : ",-mips16";
151   if (softFloat)
152     FS += FS.empty() ? "+soft-float" : ",+soft-float";
153 
154   auto &I = SubtargetMap[CPU + FS];
155   if (!I) {
156     // This needs to be done before we create a new subtarget since any
157     // creation will depend on the TM and the code generation flags on the
158     // function that reside in TargetOptions.
159     resetTargetOptions(F);
160     I = llvm::make_unique<MipsSubtarget>(TargetTriple, CPU, FS, isLittle,
161                                          *this);
162   }
163   return I.get();
164 }
165 
166 void MipsTargetMachine::resetSubtarget(MachineFunction *MF) {
167   DEBUG(dbgs() << "resetSubtarget\n");
168 
169   Subtarget = const_cast<MipsSubtarget *>(getSubtargetImpl(*MF->getFunction()));
170   MF->setSubtarget(Subtarget);
171   return;
172 }
173 
174 namespace {
175 /// Mips Code Generator Pass Configuration Options.
176 class MipsPassConfig : public TargetPassConfig {
177 public:
178   MipsPassConfig(MipsTargetMachine *TM, PassManagerBase &PM)
179     : TargetPassConfig(TM, PM) {
180     // The current implementation of long branch pass requires a scratch
181     // register ($at) to be available before branch instructions. Tail merging
182     // can break this requirement, so disable it when long branch pass is
183     // enabled.
184     EnableTailMerge = !getMipsSubtarget().enableLongBranchPass();
185   }
186 
187   MipsTargetMachine &getMipsTargetMachine() const {
188     return getTM<MipsTargetMachine>();
189   }
190 
191   const MipsSubtarget &getMipsSubtarget() const {
192     return *getMipsTargetMachine().getSubtargetImpl();
193   }
194 
195   void addIRPasses() override;
196   bool addInstSelector() override;
197   void addMachineSSAOptimization() override;
198   void addPreEmitPass() override;
199 
200   void addPreRegAlloc() override;
201 
202 };
203 } // namespace
204 
205 TargetPassConfig *MipsTargetMachine::createPassConfig(PassManagerBase &PM) {
206   return new MipsPassConfig(this, PM);
207 }
208 
209 void MipsPassConfig::addIRPasses() {
210   TargetPassConfig::addIRPasses();
211   addPass(createAtomicExpandPass(&getMipsTargetMachine()));
212   if (getMipsSubtarget().os16())
213     addPass(createMipsOs16Pass(getMipsTargetMachine()));
214   if (getMipsSubtarget().inMips16HardFloat())
215     addPass(createMips16HardFloatPass(getMipsTargetMachine()));
216 }
217 // Install an instruction selector pass using
218 // the ISelDag to gen Mips code.
219 bool MipsPassConfig::addInstSelector() {
220   addPass(createMipsModuleISelDagPass(getMipsTargetMachine()));
221   addPass(createMips16ISelDag(getMipsTargetMachine()));
222   addPass(createMipsSEISelDag(getMipsTargetMachine()));
223   return false;
224 }
225 
226 void MipsPassConfig::addMachineSSAOptimization() {
227   addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
228   TargetPassConfig::addMachineSSAOptimization();
229 }
230 
231 void MipsPassConfig::addPreRegAlloc() {
232   if (getOptLevel() == CodeGenOpt::None)
233     addPass(createMipsOptimizePICCallPass(getMipsTargetMachine()));
234 }
235 
236 TargetIRAnalysis MipsTargetMachine::getTargetIRAnalysis() {
237   return TargetIRAnalysis([this](const Function &F) {
238     if (Subtarget->allowMixed16_32()) {
239       DEBUG(errs() << "No Target Transform Info Pass Added\n");
240       // FIXME: This is no longer necessary as the TTI returned is per-function.
241       return TargetTransformInfo(F.getParent()->getDataLayout());
242     }
243 
244     DEBUG(errs() << "Target Transform Info Pass Added\n");
245     return TargetTransformInfo(BasicTTIImpl(this, F));
246   });
247 }
248 
249 // Implemented by targets that want to run passes immediately before
250 // machine code is emitted. return true if -print-machineinstrs should
251 // print out the code after the passes.
252 void MipsPassConfig::addPreEmitPass() {
253   MipsTargetMachine &TM = getMipsTargetMachine();
254 
255   // The delay slot filler pass can potientially create forbidden slot (FS)
256   // hazards for MIPSR6 which the hazard schedule pass (HSP) will fix. Any
257   // (new) pass that creates compact branches after the HSP must handle FS
258   // hazards itself or be pipelined before the HSP.
259   addPass(createMipsDelaySlotFillerPass(TM));
260   addPass(createMipsHazardSchedule());
261   addPass(createMipsLongBranchPass(TM));
262   addPass(createMipsConstantIslandPass(TM));
263 }
264