1 //===-- MipsTargetMachine.cpp - Define TargetMachine for Mips -------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Implements the info about Mips target spec.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "Mips.h"
15 #include "MipsTargetMachine.h"
16 #include "llvm/PassManager.h"
17 #include "llvm/Support/TargetRegistry.h"
18 using namespace llvm;
19 
20 extern "C" void LLVMInitializeMipsTarget() {
21   // Register the target.
22   RegisterTargetMachine<MipsebTargetMachine> X(TheMipsTarget);
23   RegisterTargetMachine<MipselTargetMachine> Y(TheMipselTarget);
24   RegisterTargetMachine<Mips64ebTargetMachine> A(TheMips64Target);
25   RegisterTargetMachine<Mips64elTargetMachine> B(TheMips64elTarget);
26 }
27 
28 // DataLayout --> Big-endian, 32-bit pointer/ABI/alignment
29 // The stack is always 8 byte aligned
30 // On function prologue, the stack is created by decrementing
31 // its pointer. Once decremented, all references are done with positive
32 // offset from the stack/frame pointer, using StackGrowsUp enables
33 // an easier handling.
34 // Using CodeModel::Large enables different CALL behavior.
35 MipsTargetMachine::
36 MipsTargetMachine(const Target &T, StringRef TT,
37                   StringRef CPU, StringRef FS, const TargetOptions &Options,
38                   Reloc::Model RM, CodeModel::Model CM,
39                   CodeGenOpt::Level OL,
40                   bool isLittle)
41   : LLVMTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL),
42     Subtarget(TT, CPU, FS, isLittle),
43     DataLayout(isLittle ?
44                (Subtarget.isABI_N64() ?
45                 "e-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
46                 "e-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32") :
47                (Subtarget.isABI_N64() ?
48                 "E-p:64:64:64-i8:8:32-i16:16:32-i64:64:64-f128:128:128-n32" :
49                 "E-p:32:32:32-i8:8:32-i16:16:32-i64:64:64-n32")),
50     InstrInfo(*this),
51     FrameLowering(Subtarget),
52     TLInfo(*this), TSInfo(*this), JITInfo() {
53 }
54 
55 void MipsebTargetMachine::anchor() { }
56 
57 MipsebTargetMachine::
58 MipsebTargetMachine(const Target &T, StringRef TT,
59                     StringRef CPU, StringRef FS, const TargetOptions &Options,
60                     Reloc::Model RM, CodeModel::Model CM,
61                     CodeGenOpt::Level OL)
62   : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
63 
64 void MipselTargetMachine::anchor() { }
65 
66 MipselTargetMachine::
67 MipselTargetMachine(const Target &T, StringRef TT,
68                     StringRef CPU, StringRef FS, const TargetOptions &Options,
69                     Reloc::Model RM, CodeModel::Model CM,
70                     CodeGenOpt::Level OL)
71   : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
72 
73 void Mips64ebTargetMachine::anchor() { }
74 
75 Mips64ebTargetMachine::
76 Mips64ebTargetMachine(const Target &T, StringRef TT,
77                       StringRef CPU, StringRef FS, const TargetOptions &Options,
78                       Reloc::Model RM, CodeModel::Model CM,
79                       CodeGenOpt::Level OL)
80   : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, false) {}
81 
82 void Mips64elTargetMachine::anchor() { }
83 
84 Mips64elTargetMachine::
85 Mips64elTargetMachine(const Target &T, StringRef TT,
86                       StringRef CPU, StringRef FS, const TargetOptions &Options,
87                       Reloc::Model RM, CodeModel::Model CM,
88                       CodeGenOpt::Level OL)
89   : MipsTargetMachine(T, TT, CPU, FS, Options, RM, CM, OL, true) {}
90 
91 // Install an instruction selector pass using
92 // the ISelDag to gen Mips code.
93 bool MipsTargetMachine::
94 addInstSelector(PassManagerBase &PM)
95 {
96   PM.add(createMipsISelDag(*this));
97   return false;
98 }
99 
100 // Implemented by targets that want to run passes immediately before
101 // machine code is emitted. return true if -print-machineinstrs should
102 // print out the code after the passes.
103 bool MipsTargetMachine::
104 addPreEmitPass(PassManagerBase &PM)
105 {
106   PM.add(createMipsDelaySlotFillerPass(*this));
107   return true;
108 }
109 
110 bool MipsTargetMachine::
111 addPreRegAlloc(PassManagerBase &PM) {
112   // Do not restore $gp if target is Mips64.
113   // In N32/64, $gp is a callee-saved register.
114   if (!Subtarget.hasMips64())
115     PM.add(createMipsEmitGPRestorePass(*this));
116   return true;
117 }
118 
119 bool MipsTargetMachine::
120 addPostRegAlloc(PassManagerBase &PM) {
121   PM.add(createMipsExpandPseudoPass(*this));
122   return true;
123 }
124 
125 bool MipsTargetMachine::addCodeEmitter(PassManagerBase &PM,
126                                        JITCodeEmitter &JCE) {
127   // Machine code emitter pass for Mips.
128   PM.add(createMipsJITCodeEmitterPass(*this, JCE));
129   return false;
130 }
131