1 //===-- MipsSubtarget.h - Define Subtarget for the Mips ---------*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file declares the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef MIPSSUBTARGET_H
15 #define MIPSSUBTARGET_H
16 
17 #include "llvm/MC/MCInstrItineraries.h"
18 #include "llvm/Support/ErrorHandling.h"
19 #include "llvm/Target/TargetSubtargetInfo.h"
20 #include <string>
21 
22 #define GET_SUBTARGETINFO_HEADER
23 #include "MipsGenSubtargetInfo.inc"
24 
25 namespace llvm {
26 class StringRef;
27 
28 class MipsTargetMachine;
29 
30 class MipsSubtarget : public MipsGenSubtargetInfo {
31   virtual void anchor();
32 
33 public:
34   // NOTE: O64 will not be supported.
35   enum MipsABIEnum {
36     UnknownABI, O32, N32, N64, EABI
37   };
38 
39 protected:
40 
41   enum MipsArchEnum {
42     Mips32, Mips32r2, Mips64, Mips64r2
43   };
44 
45   // Mips architecture version
46   MipsArchEnum MipsArchVersion;
47 
48   // Mips supported ABIs
49   MipsABIEnum MipsABI;
50 
51   // IsLittle - The target is Little Endian
52   bool IsLittle;
53 
54   // IsSingleFloat - The target only supports single precision float
55   // point operations. This enable the target to use all 32 32-bit
56   // floating point registers instead of only using even ones.
57   bool IsSingleFloat;
58 
59   // IsFP64bit - The target processor has 64-bit floating point registers.
60   bool IsFP64bit;
61 
62   // IsFP64bit - General-purpose registers are 64 bits wide
63   bool IsGP64bit;
64 
65   // HasVFPU - Processor has a vector floating point unit.
66   bool HasVFPU;
67 
68   // isLinux - Target system is Linux. Is false we consider ELFOS for now.
69   bool IsLinux;
70 
71   // UseSmallSection - Small section is used.
72   bool UseSmallSection;
73 
74   /// Features related to the presence of specific instructions.
75 
76   // HasSEInReg - SEB and SEH (signext in register) instructions.
77   bool HasSEInReg;
78 
79   // HasCondMov - Conditional mov (MOVZ, MOVN) instructions.
80   bool HasCondMov;
81 
82   // HasSwap - Byte and half swap instructions.
83   bool HasSwap;
84 
85   // HasBitCount - Count leading '1' and '0' bits.
86   bool HasBitCount;
87 
88   // HasFPIdx -- Floating point indexed load/store instructions.
89   bool HasFPIdx;
90 
91   // InMips16 -- can process Mips16 instructions
92   bool InMips16Mode;
93 
94   // Mips16 hard float
95   bool InMips16HardFloat;
96 
97   // PreviousInMips16 -- the function we just processed was in Mips 16 Mode
98   bool PreviousInMips16Mode;
99 
100   // InMicroMips -- can process MicroMips instructions
101   bool InMicroMipsMode;
102 
103   // HasDSP, HasDSPR2 -- supports DSP ASE.
104   bool HasDSP, HasDSPR2;
105 
106   // Allow mixed Mips16 and Mips32 in one source file
107   bool AllowMixed16_32;
108 
109   // Optimize for space by compiling all functions as Mips 16 unless
110   // it needs floating point. Functions needing floating point are
111   // compiled as Mips32
112   bool Os16;
113 
114   // HasMSA -- supports MSA ASE.
115   bool HasMSA;
116 
117   InstrItineraryData InstrItins;
118 
119   // Relocation Model
120   Reloc::Model RM;
121 
122   // We can override the determination of whether we are in mips16 mode
123   // as from the command line
124   enum {NoOverride, Mips16Override, NoMips16Override} OverrideMode;
125 
126   MipsTargetMachine *TM;
127 
128   Triple TargetTriple;
129 public:
130   virtual bool enablePostRAScheduler(CodeGenOpt::Level OptLevel,
131                                      AntiDepBreakMode& Mode,
132                                      RegClassVector& CriticalPathRCs) const;
133 
134   /// Only O32 and EABI supported right now.
135   bool isABI_EABI() const { return MipsABI == EABI; }
136   bool isABI_N64() const { return MipsABI == N64; }
137   bool isABI_N32() const { return MipsABI == N32; }
138   bool isABI_O32() const { return MipsABI == O32; }
139   unsigned getTargetABI() const { return MipsABI; }
140 
141   /// This constructor initializes the data members to match that
142   /// of the specified triple.
143   MipsSubtarget(const std::string &TT, const std::string &CPU,
144                 const std::string &FS, bool little, Reloc::Model RM,
145                 MipsTargetMachine *TM);
146 
147   /// ParseSubtargetFeatures - Parses features string setting specified
148   /// subtarget options.  Definition of function is auto generated by tblgen.
149   void ParseSubtargetFeatures(StringRef CPU, StringRef FS);
150 
151   bool hasMips32() const { return MipsArchVersion >= Mips32; }
152   bool hasMips32r2() const { return MipsArchVersion == Mips32r2 ||
153                                    MipsArchVersion == Mips64r2; }
154   bool hasMips64() const { return MipsArchVersion >= Mips64; }
155   bool hasMips64r2() const { return MipsArchVersion == Mips64r2; }
156 
157   bool isLittle() const { return IsLittle; }
158   bool isFP64bit() const { return IsFP64bit; }
159   bool isNotFP64bit() const { return !IsFP64bit; }
160   bool isGP64bit() const { return IsGP64bit; }
161   bool isGP32bit() const { return !IsGP64bit; }
162   bool isSingleFloat() const { return IsSingleFloat; }
163   bool isNotSingleFloat() const { return !IsSingleFloat; }
164   bool hasVFPU() const { return HasVFPU; }
165   bool inMips16Mode() const {
166     switch (OverrideMode) {
167     case NoOverride:
168       return InMips16Mode;
169     case Mips16Override:
170       return true;
171     case NoMips16Override:
172       return false;
173     }
174     llvm_unreachable("Unexpected mode");
175   }
176   bool inMips16ModeDefault() const {
177     return InMips16Mode;
178   }
179   bool inMips16HardFloat() const {
180     return inMips16Mode() && InMips16HardFloat;
181   }
182   bool inMicroMipsMode() const { return InMicroMipsMode; }
183   bool hasDSP() const { return HasDSP; }
184   bool hasDSPR2() const { return HasDSPR2; }
185   bool hasMSA() const { return HasMSA; }
186   bool isLinux() const { return IsLinux; }
187   bool useSmallSection() const { return UseSmallSection; }
188 
189   bool hasStandardEncoding() const { return !inMips16Mode(); }
190 
191   bool mipsSEUsesSoftFloat() const;
192 
193   bool enableLongBranchPass() const {
194     return hasStandardEncoding() || allowMixed16_32();
195   }
196 
197   /// Features related to the presence of specific instructions.
198   bool hasSEInReg()   const { return HasSEInReg; }
199   bool hasCondMov()   const { return HasCondMov; }
200   bool hasSwap()      const { return HasSwap; }
201   bool hasBitCount()  const { return HasBitCount; }
202   bool hasFPIdx()     const { return HasFPIdx; }
203   bool hasExtractInsert() const { return !inMips16Mode() && hasMips32r2(); }
204 
205   const InstrItineraryData &getInstrItineraryData() const { return InstrItins; }
206   bool allowMixed16_32() const { return inMips16ModeDefault() |
207                                         AllowMixed16_32;}
208 
209   bool os16() const { return Os16;};
210 
211   bool isTargetNaCl() const { return TargetTriple.isOSNaCl(); }
212   bool isNotTargetNaCl() const { return !TargetTriple.isOSNaCl(); }
213 
214 // for now constant islands are on for the whole compilation unit but we only
215 // really use them if in addition we are in mips16 mode
216 //
217 static bool useConstantIslands();
218 
219   unsigned stackAlignment() const { return hasMips64() ? 16 : 8; }
220 
221   // Grab relocation model
222   Reloc::Model getRelocationModel() const {return RM;}
223 
224   /// \brief Reset the subtarget for the Mips target.
225   void resetSubtarget(MachineFunction *MF);
226 
227 
228 };
229 } // End llvm namespace
230 
231 #endif
232