1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSubtarget.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/IR/Attributes.h"
20 #include "llvm/IR/Function.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/Debug.h"
23 #include "llvm/Support/TargetRegistry.h"
24 #include "llvm/Support/raw_ostream.h"
25 
26 using namespace llvm;
27 
28 #define DEBUG_TYPE "mips-subtarget"
29 
30 #define GET_SUBTARGETINFO_TARGET_DESC
31 #define GET_SUBTARGETINFO_CTOR
32 #include "MipsGenSubtargetInfo.inc"
33 
34 // FIXME: Maybe this should be on by default when Mips16 is specified
35 //
36 static cl::opt<bool>
37     Mixed16_32("mips-mixed-16-32", cl::init(false),
38                cl::desc("Allow for a mixture of Mips16 "
39                         "and Mips32 code in a single output file"),
40                cl::Hidden);
41 
42 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
43                                cl::desc("Compile all functions that don't use "
44                                         "floating point as Mips 16"),
45                                cl::Hidden);
46 
47 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
48                                      cl::desc("Enable mips16 hard float."),
49                                      cl::init(false));
50 
51 static cl::opt<bool>
52     Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
53                           cl::desc("Enable mips16 constant islands."),
54                           cl::init(true));
55 
56 static cl::opt<bool>
57     GPOpt("mgpopt", cl::Hidden,
58           cl::desc("Enable gp-relative addressing of mips small data items"));
59 
60 bool MipsSubtarget::DspWarningPrinted = false;
61 
62 bool MipsSubtarget::MSAWarningPrinted = false;
63 
64 void MipsSubtarget::anchor() {}
65 
66 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
67                              bool little, const MipsTargetMachine &TM,
68                              unsigned StackAlignOverride)
69     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
70       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
71       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
72       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
73       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
74       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
75       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
76       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
77       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
78       HasEVA(false), DisableMadd4(false), HasMT(false),
79       StackAlignOverride(StackAlignOverride), TM(TM), TargetTriple(TT),
80       TSInfo(), InstrInfo(MipsInstrInfo::create(
81                     initializeSubtargetDependencies(CPU, FS, TM))),
82       FrameLowering(MipsFrameLowering::create(*this)),
83       TLInfo(MipsTargetLowering::create(TM, *this)) {
84 
85   if (MipsArchVersion == MipsDefault)
86     MipsArchVersion = Mips32;
87 
88   // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
89   // been tested and currently exist for the integrated assembler only.
90   if (MipsArchVersion == Mips1)
91     report_fatal_error("Code generation for MIPS-I is not implemented", false);
92   if (MipsArchVersion == Mips5)
93     report_fatal_error("Code generation for MIPS-V is not implemented", false);
94 
95   // Check if Architecture and ABI are compatible.
96   assert(((!isGP64bit() && isABI_O32()) ||
97           (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
98          "Invalid  Arch & ABI pair.");
99 
100   if (hasMSA() && !isFP64bit())
101     report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
102                        "See -mattr=+fp64.",
103                        false);
104 
105   if (!isABI_O32() && !useOddSPReg())
106     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
107 
108   if (IsFPXX && (isABI_N32() || isABI_N64()))
109     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
110 
111   if (hasMips64r6() && InMicroMipsMode)
112     report_fatal_error("microMIPS64R6 is not supported", false);
113 
114   if (hasMips32r6()) {
115     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
116 
117     assert(isFP64bit());
118     assert(isNaN2008());
119     if (hasDSP())
120       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
121   }
122 
123   if (NoABICalls && TM.isPositionIndependent())
124     report_fatal_error("position-independent code requires '-mabicalls'");
125 
126   if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
127     NoABICalls = true;
128 
129   // Set UseSmallSection.
130   UseSmallSection = GPOpt;
131   if (!NoABICalls && GPOpt) {
132     errs() << "warning: cannot use small-data accesses for '-mabicalls'"
133            << "\n";
134     UseSmallSection = false;
135   }
136 
137   if (hasDSPR2() && !DspWarningPrinted) {
138     if (hasMips64() && !hasMips64r2()) {
139       errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
140              << "greater\n";
141       DspWarningPrinted = true;
142     } else if (hasMips32() && !hasMips32r2()) {
143       errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
144              << "greater\n";
145       DspWarningPrinted = true;
146     }
147   } else if (hasDSP() && !DspWarningPrinted) {
148     if (hasMips64() && !hasMips64r2()) {
149       errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
150              << "greater\n";
151       DspWarningPrinted = true;
152     } else if (hasMips32() && !hasMips32r2()) {
153       errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
154              << "greater\n";
155       DspWarningPrinted = true;
156     }
157   }
158 
159   if (hasMSA() && !MSAWarningPrinted) {
160     if (hasMips64() && !hasMips64r5()) {
161       errs() << "warning: the 'msa' ASE requires MIPS64 revision 5 or "
162              << "greater\n";
163       MSAWarningPrinted = true;
164     } else if (hasMips32() && !hasMips32r5()) {
165       errs() << "warning: the 'msa' ASE requires MIPS32 revision 5 or "
166              << "greater\n";
167       MSAWarningPrinted = true;
168     }
169   }
170 }
171 
172 bool MipsSubtarget::isPositionIndependent() const {
173   return TM.isPositionIndependent();
174 }
175 
176 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
177 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
178 
179 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
180   CriticalPathRCs.clear();
181   CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
182                                         : &Mips::GPR32RegClass);
183 }
184 
185 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
186   return CodeGenOpt::Aggressive;
187 }
188 
189 MipsSubtarget &
190 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
191                                                const TargetMachine &TM) {
192   std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
193 
194   // Parse features string.
195   ParseSubtargetFeatures(CPUName, FS);
196   // Initialize scheduling itinerary for the specified CPU.
197   InstrItins = getInstrItineraryForCPU(CPUName);
198 
199   if (InMips16Mode && !IsSoftFloat)
200     InMips16HardFloat = true;
201 
202   if (StackAlignOverride)
203     stackAlignment = StackAlignOverride;
204   else if (isABI_N32() || isABI_N64())
205     stackAlignment = 16;
206   else {
207     assert(isABI_O32() && "Unknown ABI for stack alignment!");
208     stackAlignment = 8;
209   }
210 
211   return *this;
212 }
213 
214 bool MipsSubtarget::useConstantIslands() {
215   DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
216   return Mips16ConstantIslands;
217 }
218 
219 Reloc::Model MipsSubtarget::getRelocationModel() const {
220   return TM.getRelocationModel();
221 }
222 
223 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
224 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
225 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
226 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
227