1 //===- MipsSubtarget.cpp - Mips Subtarget Information -----------*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file implements the Mips specific subclass of TargetSubtarget. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSubtarget.h" 15 #include "Mips.h" 16 #include "MipsGenSubtarget.inc" 17 #include "llvm/Module.h" 18 #include "llvm/Support/CommandLine.h" 19 using namespace llvm; 20 21 static cl::opt<bool> 22 NotABICall("disable-mips-abicall", cl::Hidden, 23 cl::desc("Disable code for SVR4-style dynamic objects")); 24 static cl::opt<bool> 25 AbsoluteCall("enable-mips-absolute-call", cl::Hidden, 26 cl::desc("Enable absolute call within abicall")); 27 static cl::opt<unsigned> 28 SSThreshold("mips-ssection-threshold", cl::Hidden, 29 cl::desc("Small data and bss section threshold size (default=8)"), 30 cl::init(8)); 31 32 MipsSubtarget::MipsSubtarget(const TargetMachine &TM, const Module &M, 33 const std::string &FS, bool little) : 34 MipsArchVersion(Mips1), MipsABI(O32), IsLittle(little), IsSingleFloat(false), 35 IsFP64bit(false), IsGP64bit(false), HasVFPU(false), HasABICall(true), 36 HasAbsoluteCall(false), IsLinux(true), HasSEInReg(false), HasCondMov(false), 37 HasMulDivAdd(false), HasMinMax(false), HasSwap(false), HasBitCount(false) 38 { 39 std::string CPU = "mips1"; 40 MipsArchVersion = Mips1; 41 42 // Parse features string. 43 ParseSubtargetFeatures(FS, CPU); 44 const std::string& TT = M.getTargetTriple(); 45 46 // Small section size threshold 47 SSectionThreshold = SSThreshold; 48 49 // Is the target system Linux ? 50 if (TT.find("linux") == std::string::npos) 51 IsLinux = false; 52 53 // When only the target triple is specified and is 54 // a allegrex target, set the features. We also match 55 // big and little endian allegrex cores (dont really 56 // know if a big one exists) 57 if (TT.find("mipsallegrex") != std::string::npos || 58 TT.find("psp") != std::string::npos) { 59 MipsABI = EABI; 60 IsSingleFloat = true; 61 MipsArchVersion = Mips2; 62 HasVFPU = true; // Enables Allegrex Vector FPU (not supported yet) 63 HasSEInReg = true; 64 HasBitCount = true; 65 HasSwap = true; 66 HasCondMov = true; 67 } 68 69 // Abicall is the default for O32 ABI, but is disabled within EABI and in 70 // static code. 71 if (NotABICall || isABI_EABI() || (TM.getRelocationModel() == Reloc::Static)) 72 HasABICall = false; 73 74 // TODO: disable when handling 64 bit symbols in the future. 75 if (HasABICall && AbsoluteCall) 76 HasAbsoluteCall = true; 77 } 78