1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSubtarget.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsCallLowering.h"
20 #include "MipsLegalizerInfo.h"
21 #include "MipsRegisterBankInfo.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "mips-subtarget"
32 
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "MipsGenSubtargetInfo.inc"
36 
37 // FIXME: Maybe this should be on by default when Mips16 is specified
38 //
39 static cl::opt<bool>
40     Mixed16_32("mips-mixed-16-32", cl::init(false),
41                cl::desc("Allow for a mixture of Mips16 "
42                         "and Mips32 code in a single output file"),
43                cl::Hidden);
44 
45 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
46                                cl::desc("Compile all functions that don't use "
47                                         "floating point as Mips 16"),
48                                cl::Hidden);
49 
50 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
51                                      cl::desc("Enable mips16 hard float."),
52                                      cl::init(false));
53 
54 static cl::opt<bool>
55     Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
56                           cl::desc("Enable mips16 constant islands."),
57                           cl::init(true));
58 
59 static cl::opt<bool>
60     GPOpt("mgpopt", cl::Hidden,
61           cl::desc("Enable gp-relative addressing of mips small data items"));
62 
63 bool MipsSubtarget::DspWarningPrinted = false;
64 
65 bool MipsSubtarget::MSAWarningPrinted = false;
66 
67 void MipsSubtarget::anchor() {}
68 
69 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
70                              bool little, const MipsTargetMachine &TM,
71                              unsigned StackAlignOverride)
72     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
73       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
74       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
75       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
76       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
77       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
78       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
79       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
80       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
81       HasEVA(false), DisableMadd4(false), HasMT(false), HasCRC(false),
82       HasVirt(false), HasGINV(false), UseIndirectJumpsHazard(false),
83       StackAlignOverride(StackAlignOverride),
84       TM(TM), TargetTriple(TT), TSInfo(),
85       InstrInfo(
86           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
87       FrameLowering(MipsFrameLowering::create(*this)),
88       TLInfo(MipsTargetLowering::create(TM, *this)) {
89 
90   if (MipsArchVersion == MipsDefault)
91     MipsArchVersion = Mips32;
92 
93   // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
94   // been tested and currently exist for the integrated assembler only.
95   if (MipsArchVersion == Mips1)
96     report_fatal_error("Code generation for MIPS-I is not implemented", false);
97   if (MipsArchVersion == Mips5)
98     report_fatal_error("Code generation for MIPS-V is not implemented", false);
99 
100   // Check if Architecture and ABI are compatible.
101   assert(((!isGP64bit() && isABI_O32()) ||
102           (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
103          "Invalid  Arch & ABI pair.");
104 
105   if (hasMSA() && !isFP64bit())
106     report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
107                        "See -mattr=+fp64.",
108                        false);
109 
110   if (!isABI_O32() && !useOddSPReg())
111     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
112 
113   if (IsFPXX && (isABI_N32() || isABI_N64()))
114     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
115 
116   if (hasMips64r6() && InMicroMipsMode)
117     report_fatal_error("microMIPS64R6 is not supported", false);
118 
119   if (!isABI_O32() && InMicroMipsMode)
120     report_fatal_error("microMIPS64 is not supported.", false);
121 
122   if (UseIndirectJumpsHazard) {
123     if (InMicroMipsMode)
124       report_fatal_error(
125           "cannot combine indirect jumps with hazard barriers and microMIPS");
126     if (!hasMips32r2())
127       report_fatal_error(
128           "indirect jumps with hazard barriers requires MIPS32R2 or later");
129   }
130   if (hasMips32r6()) {
131     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
132 
133     assert(isFP64bit());
134     assert(isNaN2008());
135     if (hasDSP())
136       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
137   }
138 
139   if (NoABICalls && TM.isPositionIndependent())
140     report_fatal_error("position-independent code requires '-mabicalls'");
141 
142   if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
143     NoABICalls = true;
144 
145   // Set UseSmallSection.
146   UseSmallSection = GPOpt;
147   if (!NoABICalls && GPOpt) {
148     errs() << "warning: cannot use small-data accesses for '-mabicalls'"
149            << "\n";
150     UseSmallSection = false;
151   }
152 
153   if (hasDSPR2() && !DspWarningPrinted) {
154     if (hasMips64() && !hasMips64r2()) {
155       errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
156              << "greater\n";
157       DspWarningPrinted = true;
158     } else if (hasMips32() && !hasMips32r2()) {
159       errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
160              << "greater\n";
161       DspWarningPrinted = true;
162     }
163   } else if (hasDSP() && !DspWarningPrinted) {
164     if (hasMips64() && !hasMips64r2()) {
165       errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
166              << "greater\n";
167       DspWarningPrinted = true;
168     } else if (hasMips32() && !hasMips32r2()) {
169       errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
170              << "greater\n";
171       DspWarningPrinted = true;
172     }
173   }
174 
175   if (hasMSA() && !MSAWarningPrinted) {
176     if (hasMips64() && !hasMips64r5()) {
177       errs() << "warning: the 'msa' ASE requires MIPS64 revision 5 or "
178              << "greater\n";
179       MSAWarningPrinted = true;
180     } else if (hasMips32() && !hasMips32r5()) {
181       errs() << "warning: the 'msa' ASE requires MIPS32 revision 5 or "
182              << "greater\n";
183       MSAWarningPrinted = true;
184     }
185   }
186 
187   CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
188   Legalizer.reset(new MipsLegalizerInfo(*this));
189 
190   auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
191   RegBankInfo.reset(RBI);
192   InstSelector.reset(createMipsInstructionSelector(
193       *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI));
194 }
195 
196 bool MipsSubtarget::isPositionIndependent() const {
197   return TM.isPositionIndependent();
198 }
199 
200 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
201 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
202 
203 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
204   CriticalPathRCs.clear();
205   CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
206                                         : &Mips::GPR32RegClass);
207 }
208 
209 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
210   return CodeGenOpt::Aggressive;
211 }
212 
213 MipsSubtarget &
214 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
215                                                const TargetMachine &TM) {
216   std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
217 
218   // Parse features string.
219   ParseSubtargetFeatures(CPUName, FS);
220   // Initialize scheduling itinerary for the specified CPU.
221   InstrItins = getInstrItineraryForCPU(CPUName);
222 
223   if (InMips16Mode && !IsSoftFloat)
224     InMips16HardFloat = true;
225 
226   if (StackAlignOverride)
227     stackAlignment = StackAlignOverride;
228   else if (isABI_N32() || isABI_N64())
229     stackAlignment = 16;
230   else {
231     assert(isABI_O32() && "Unknown ABI for stack alignment!");
232     stackAlignment = 8;
233   }
234 
235   return *this;
236 }
237 
238 bool MipsSubtarget::useConstantIslands() {
239   LLVM_DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands
240                     << "\n");
241   return Mips16ConstantIslands;
242 }
243 
244 Reloc::Model MipsSubtarget::getRelocationModel() const {
245   return TM.getRelocationModel();
246 }
247 
248 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
249 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
250 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
251 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
252 
253 const CallLowering *MipsSubtarget::getCallLowering() const {
254   return CallLoweringInfo.get();
255 }
256 
257 const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
258   return Legalizer.get();
259 }
260 
261 const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
262   return RegBankInfo.get();
263 }
264 
265 const InstructionSelector *MipsSubtarget::getInstructionSelector() const {
266   return InstSelector.get();
267 }
268