1 //===-- MipsSubtarget.cpp - Mips Subtarget Information --------------------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file implements the Mips specific subclass of TargetSubtargetInfo.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSubtarget.h"
15 #include "Mips.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsRegisterInfo.h"
18 #include "MipsTargetMachine.h"
19 #include "MipsCallLowering.h"
20 #include "MipsLegalizerInfo.h"
21 #include "MipsRegisterBankInfo.h"
22 #include "llvm/IR/Attributes.h"
23 #include "llvm/IR/Function.h"
24 #include "llvm/Support/CommandLine.h"
25 #include "llvm/Support/Debug.h"
26 #include "llvm/Support/TargetRegistry.h"
27 #include "llvm/Support/raw_ostream.h"
28 
29 using namespace llvm;
30 
31 #define DEBUG_TYPE "mips-subtarget"
32 
33 #define GET_SUBTARGETINFO_TARGET_DESC
34 #define GET_SUBTARGETINFO_CTOR
35 #include "MipsGenSubtargetInfo.inc"
36 
37 // FIXME: Maybe this should be on by default when Mips16 is specified
38 //
39 static cl::opt<bool>
40     Mixed16_32("mips-mixed-16-32", cl::init(false),
41                cl::desc("Allow for a mixture of Mips16 "
42                         "and Mips32 code in a single output file"),
43                cl::Hidden);
44 
45 static cl::opt<bool> Mips_Os16("mips-os16", cl::init(false),
46                                cl::desc("Compile all functions that don't use "
47                                         "floating point as Mips 16"),
48                                cl::Hidden);
49 
50 static cl::opt<bool> Mips16HardFloat("mips16-hard-float", cl::NotHidden,
51                                      cl::desc("Enable mips16 hard float."),
52                                      cl::init(false));
53 
54 static cl::opt<bool>
55     Mips16ConstantIslands("mips16-constant-islands", cl::NotHidden,
56                           cl::desc("Enable mips16 constant islands."),
57                           cl::init(true));
58 
59 static cl::opt<bool>
60     GPOpt("mgpopt", cl::Hidden,
61           cl::desc("Enable gp-relative addressing of mips small data items"));
62 
63 bool MipsSubtarget::DspWarningPrinted = false;
64 
65 bool MipsSubtarget::MSAWarningPrinted = false;
66 
67 void MipsSubtarget::anchor() {}
68 
69 MipsSubtarget::MipsSubtarget(const Triple &TT, StringRef CPU, StringRef FS,
70                              bool little, const MipsTargetMachine &TM,
71                              unsigned StackAlignOverride)
72     : MipsGenSubtargetInfo(TT, CPU, FS), MipsArchVersion(MipsDefault),
73       IsLittle(little), IsSoftFloat(false), IsSingleFloat(false), IsFPXX(false),
74       NoABICalls(false), IsFP64bit(false), UseOddSPReg(true),
75       IsNaN2008bit(false), IsGP64bit(false), HasVFPU(false), HasCnMips(false),
76       HasMips3_32(false), HasMips3_32r2(false), HasMips4_32(false),
77       HasMips4_32r2(false), HasMips5_32r2(false), InMips16Mode(false),
78       InMips16HardFloat(Mips16HardFloat), InMicroMipsMode(false), HasDSP(false),
79       HasDSPR2(false), HasDSPR3(false), AllowMixed16_32(Mixed16_32 | Mips_Os16),
80       Os16(Mips_Os16), HasMSA(false), UseTCCInDIV(false), HasSym32(false),
81       HasEVA(false), DisableMadd4(false), HasMT(false),
82       UseIndirectJumpsHazard(false), StackAlignOverride(StackAlignOverride),
83       TM(TM), TargetTriple(TT), TSInfo(),
84       InstrInfo(
85           MipsInstrInfo::create(initializeSubtargetDependencies(CPU, FS, TM))),
86       FrameLowering(MipsFrameLowering::create(*this)),
87       TLInfo(MipsTargetLowering::create(TM, *this)) {
88 
89   if (MipsArchVersion == MipsDefault)
90     MipsArchVersion = Mips32;
91 
92   // Don't even attempt to generate code for MIPS-I and MIPS-V. They have not
93   // been tested and currently exist for the integrated assembler only.
94   if (MipsArchVersion == Mips1)
95     report_fatal_error("Code generation for MIPS-I is not implemented", false);
96   if (MipsArchVersion == Mips5)
97     report_fatal_error("Code generation for MIPS-V is not implemented", false);
98 
99   // Check if Architecture and ABI are compatible.
100   assert(((!isGP64bit() && isABI_O32()) ||
101           (isGP64bit() && (isABI_N32() || isABI_N64()))) &&
102          "Invalid  Arch & ABI pair.");
103 
104   if (hasMSA() && !isFP64bit())
105     report_fatal_error("MSA requires a 64-bit FPU register file (FR=1 mode). "
106                        "See -mattr=+fp64.",
107                        false);
108 
109   if (!isABI_O32() && !useOddSPReg())
110     report_fatal_error("-mattr=+nooddspreg requires the O32 ABI.", false);
111 
112   if (IsFPXX && (isABI_N32() || isABI_N64()))
113     report_fatal_error("FPXX is not permitted for the N32/N64 ABI's.", false);
114 
115   if (hasMips64r6() && InMicroMipsMode)
116     report_fatal_error("microMIPS64R6 is not supported", false);
117 
118 
119   if (UseIndirectJumpsHazard) {
120     if (InMicroMipsMode)
121       report_fatal_error(
122           "cannot combine indirect jumps with hazard barriers and microMIPS");
123     if (!hasMips32r2())
124       report_fatal_error(
125           "indirect jumps with hazard barriers requires MIPS32R2 or later");
126   }
127   if (hasMips32r6()) {
128     StringRef ISA = hasMips64r6() ? "MIPS64r6" : "MIPS32r6";
129 
130     assert(isFP64bit());
131     assert(isNaN2008());
132     if (hasDSP())
133       report_fatal_error(ISA + " is not compatible with the DSP ASE", false);
134   }
135 
136   if (NoABICalls && TM.isPositionIndependent())
137     report_fatal_error("position-independent code requires '-mabicalls'");
138 
139   if (isABI_N64() && !TM.isPositionIndependent() && !hasSym32())
140     NoABICalls = true;
141 
142   // Set UseSmallSection.
143   UseSmallSection = GPOpt;
144   if (!NoABICalls && GPOpt) {
145     errs() << "warning: cannot use small-data accesses for '-mabicalls'"
146            << "\n";
147     UseSmallSection = false;
148   }
149 
150   if (hasDSPR2() && !DspWarningPrinted) {
151     if (hasMips64() && !hasMips64r2()) {
152       errs() << "warning: the 'dspr2' ASE requires MIPS64 revision 2 or "
153              << "greater\n";
154       DspWarningPrinted = true;
155     } else if (hasMips32() && !hasMips32r2()) {
156       errs() << "warning: the 'dspr2' ASE requires MIPS32 revision 2 or "
157              << "greater\n";
158       DspWarningPrinted = true;
159     }
160   } else if (hasDSP() && !DspWarningPrinted) {
161     if (hasMips64() && !hasMips64r2()) {
162       errs() << "warning: the 'dsp' ASE requires MIPS64 revision 2 or "
163              << "greater\n";
164       DspWarningPrinted = true;
165     } else if (hasMips32() && !hasMips32r2()) {
166       errs() << "warning: the 'dsp' ASE requires MIPS32 revision 2 or "
167              << "greater\n";
168       DspWarningPrinted = true;
169     }
170   }
171 
172   if (hasMSA() && !MSAWarningPrinted) {
173     if (hasMips64() && !hasMips64r5()) {
174       errs() << "warning: the 'msa' ASE requires MIPS64 revision 5 or "
175              << "greater\n";
176       MSAWarningPrinted = true;
177     } else if (hasMips32() && !hasMips32r5()) {
178       errs() << "warning: the 'msa' ASE requires MIPS32 revision 5 or "
179              << "greater\n";
180       MSAWarningPrinted = true;
181     }
182   }
183 
184   CallLoweringInfo.reset(new MipsCallLowering(*getTargetLowering()));
185   Legalizer.reset(new MipsLegalizerInfo(*this));
186 
187   auto *RBI = new MipsRegisterBankInfo(*getRegisterInfo());
188   RegBankInfo.reset(RBI);
189   InstSelector.reset(createMipsInstructionSelector(
190       *static_cast<const MipsTargetMachine *>(&TM), *this, *RBI));
191 }
192 
193 bool MipsSubtarget::isPositionIndependent() const {
194   return TM.isPositionIndependent();
195 }
196 
197 /// This overrides the PostRAScheduler bit in the SchedModel for any CPU.
198 bool MipsSubtarget::enablePostRAScheduler() const { return true; }
199 
200 void MipsSubtarget::getCriticalPathRCs(RegClassVector &CriticalPathRCs) const {
201   CriticalPathRCs.clear();
202   CriticalPathRCs.push_back(isGP64bit() ? &Mips::GPR64RegClass
203                                         : &Mips::GPR32RegClass);
204 }
205 
206 CodeGenOpt::Level MipsSubtarget::getOptLevelToEnablePostRAScheduler() const {
207   return CodeGenOpt::Aggressive;
208 }
209 
210 MipsSubtarget &
211 MipsSubtarget::initializeSubtargetDependencies(StringRef CPU, StringRef FS,
212                                                const TargetMachine &TM) {
213   std::string CPUName = MIPS_MC::selectMipsCPU(TM.getTargetTriple(), CPU);
214 
215   // Parse features string.
216   ParseSubtargetFeatures(CPUName, FS);
217   // Initialize scheduling itinerary for the specified CPU.
218   InstrItins = getInstrItineraryForCPU(CPUName);
219 
220   if (InMips16Mode && !IsSoftFloat)
221     InMips16HardFloat = true;
222 
223   if (StackAlignOverride)
224     stackAlignment = StackAlignOverride;
225   else if (isABI_N32() || isABI_N64())
226     stackAlignment = 16;
227   else {
228     assert(isABI_O32() && "Unknown ABI for stack alignment!");
229     stackAlignment = 8;
230   }
231 
232   return *this;
233 }
234 
235 bool MipsSubtarget::useConstantIslands() {
236   DEBUG(dbgs() << "use constant islands " << Mips16ConstantIslands << "\n");
237   return Mips16ConstantIslands;
238 }
239 
240 Reloc::Model MipsSubtarget::getRelocationModel() const {
241   return TM.getRelocationModel();
242 }
243 
244 bool MipsSubtarget::isABI_N64() const { return getABI().IsN64(); }
245 bool MipsSubtarget::isABI_N32() const { return getABI().IsN32(); }
246 bool MipsSubtarget::isABI_O32() const { return getABI().IsO32(); }
247 const MipsABIInfo &MipsSubtarget::getABI() const { return TM.getABI(); }
248 
249 const CallLowering *MipsSubtarget::getCallLowering() const {
250   return CallLoweringInfo.get();
251 }
252 
253 const LegalizerInfo *MipsSubtarget::getLegalizerInfo() const {
254   return Legalizer.get();
255 }
256 
257 const RegisterBankInfo *MipsSubtarget::getRegBankInfo() const {
258   return RegBankInfo.get();
259 }
260 
261 const InstructionSelector *MipsSubtarget::getInstructionSelector() const {
262   return InstSelector.get();
263 }
264