1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsSERegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 
40 using namespace llvm;
41 
42 MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST)
43   : MipsRegisterInfo(ST) {}
44 
45 bool MipsSERegisterInfo::
46 requiresRegisterScavenging(const MachineFunction &MF) const {
47   return true;
48 }
49 
50 bool MipsSERegisterInfo::
51 requiresFrameIndexScavenging(const MachineFunction &MF) const {
52   return true;
53 }
54 
55 const TargetRegisterClass *
56 MipsSERegisterInfo::intRegClass(unsigned Size) const {
57   if (Size == 4)
58     return &Mips::GPR32RegClass;
59 
60   assert(Size == 8);
61   return &Mips::GPR64RegClass;
62 }
63 
64 /// Get the size of the offset supported by the given load/store.
65 /// The result includes the effects of any scale factors applied to the
66 /// instruction immediate.
67 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
68   switch (Opcode) {
69   case Mips::LD_B:
70   case Mips::ST_B:
71     return 10;
72   case Mips::LD_H:
73   case Mips::ST_H:
74     return 10 + 1 /* scale factor */;
75   case Mips::LD_W:
76   case Mips::ST_W:
77     return 10 + 2 /* scale factor */;
78   case Mips::LD_D:
79   case Mips::ST_D:
80     return 10 + 3 /* scale factor */;
81   default:
82     return 16;
83   }
84 }
85 
86 /// Get the scale factor applied to the immediate in the given load/store.
87 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
88   switch (Opcode) {
89   case Mips::LD_H:
90   case Mips::ST_H:
91     return 2;
92   case Mips::LD_W:
93   case Mips::ST_W:
94     return 4;
95   case Mips::LD_D:
96   case Mips::ST_D:
97     return 8;
98   default:
99     return 1;
100   }
101 }
102 
103 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
104                                      unsigned OpNo, int FrameIndex,
105                                      uint64_t StackSize,
106                                      int64_t SPOffset) const {
107   MachineInstr &MI = *II;
108   MachineFunction &MF = *MI.getParent()->getParent();
109   MachineFrameInfo *MFI = MF.getFrameInfo();
110   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
111 
112   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
113   int MinCSFI = 0;
114   int MaxCSFI = -1;
115 
116   if (CSI.size()) {
117     MinCSFI = CSI[0].getFrameIdx();
118     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
119   }
120 
121   bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
122 
123   // The following stack frame objects are always referenced relative to $sp:
124   //  1. Outgoing arguments.
125   //  2. Pointer to dynamically allocated stack space.
126   //  3. Locations for callee-saved registers.
127   //  4. Locations for eh data registers.
128   // Everything else is referenced relative to whatever register
129   // getFrameRegister() returns.
130   unsigned FrameReg;
131 
132   if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
133     FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
134   else
135     FrameReg = getFrameRegister(MF);
136 
137   // Calculate final offset.
138   // - There is no need to change the offset if the frame object is one of the
139   //   following: an outgoing argument, pointer to a dynamically allocated
140   //   stack space or a $gp restore location,
141   // - If the frame object is any of the following, its offset must be adjusted
142   //   by adding the size of the stack:
143   //   incoming argument, callee-saved register location or local variable.
144   bool IsKill = false;
145   int64_t Offset;
146 
147   Offset = SPOffset + (int64_t)StackSize;
148   Offset += MI.getOperand(OpNo + 1).getImm();
149 
150   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
151 
152   if (!MI.isDebugValue()) {
153     // Make sure Offset fits within the field available.
154     // For MSA instructions, this is a 10-bit signed immediate (scaled by
155     // element size), otherwise it is a 16-bit signed immediate.
156     unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
157     unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
158 
159     if (OffsetBitSize < 16 && isInt<16>(Offset) &&
160         (!isIntN(OffsetBitSize, Offset) ||
161          OffsetToAlignment(Offset, OffsetAlign) != 0)) {
162       // If we have an offset that needs to fit into a signed n-bit immediate
163       // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
164       MachineBasicBlock &MBB = *MI.getParent();
165       DebugLoc DL = II->getDebugLoc();
166       unsigned ADDiu = Subtarget.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
167       const TargetRegisterClass *RC =
168           Subtarget.isABI_N64() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
169       MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
170       unsigned Reg = RegInfo.createVirtualRegister(RC);
171       const MipsSEInstrInfo &TII =
172           *static_cast<const MipsSEInstrInfo *>(
173                MBB.getParent()->getTarget().getInstrInfo());
174       BuildMI(MBB, II, DL, TII.get(ADDiu), Reg).addReg(FrameReg).addImm(Offset);
175 
176       FrameReg = Reg;
177       Offset = 0;
178       IsKill = true;
179     } else if (!isInt<16>(Offset)) {
180       // Otherwise split the offset into 16-bit pieces and add it in multiple
181       // instructions.
182       MachineBasicBlock &MBB = *MI.getParent();
183       DebugLoc DL = II->getDebugLoc();
184       unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
185       unsigned NewImm = 0;
186       const MipsSEInstrInfo &TII =
187           *static_cast<const MipsSEInstrInfo *>(
188                MBB.getParent()->getTarget().getInstrInfo());
189       unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
190                                        OffsetBitSize == 16 ? &NewImm : NULL);
191       BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
192         .addReg(Reg, RegState::Kill);
193 
194       FrameReg = Reg;
195       Offset = SignExtend64<16>(NewImm);
196       IsKill = true;
197     }
198   }
199 
200   MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
201   MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
202 }
203