1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsSERegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "MipsTargetMachine.h"
22 #include "llvm/ADT/BitVector.h"
23 #include "llvm/ADT/STLExtras.h"
24 #include "llvm/CodeGen/MachineFrameInfo.h"
25 #include "llvm/CodeGen/MachineFunction.h"
26 #include "llvm/CodeGen/MachineInstrBuilder.h"
27 #include "llvm/CodeGen/MachineRegisterInfo.h"
28 #include "llvm/IR/Constants.h"
29 #include "llvm/IR/DebugInfo.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 
41 using namespace llvm;
42 
43 #define DEBUG_TYPE "mips-reg-info"
44 
45 MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
46 
47 bool MipsSERegisterInfo::
48 requiresRegisterScavenging(const MachineFunction &MF) const {
49   return true;
50 }
51 
52 bool MipsSERegisterInfo::
53 requiresFrameIndexScavenging(const MachineFunction &MF) const {
54   return true;
55 }
56 
57 const TargetRegisterClass *
58 MipsSERegisterInfo::intRegClass(unsigned Size) const {
59   if (Size == 4)
60     return &Mips::GPR32RegClass;
61 
62   assert(Size == 8);
63   return &Mips::GPR64RegClass;
64 }
65 
66 /// Get the size of the offset supported by the given load/store.
67 /// The result includes the effects of any scale factors applied to the
68 /// instruction immediate.
69 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
70   switch (Opcode) {
71   case Mips::LD_B:
72   case Mips::ST_B:
73     return 10;
74   case Mips::LD_H:
75   case Mips::ST_H:
76     return 10 + 1 /* scale factor */;
77   case Mips::LD_W:
78   case Mips::ST_W:
79     return 10 + 2 /* scale factor */;
80   case Mips::LD_D:
81   case Mips::ST_D:
82     return 10 + 3 /* scale factor */;
83   default:
84     return 16;
85   }
86 }
87 
88 /// Get the scale factor applied to the immediate in the given load/store.
89 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
90   switch (Opcode) {
91   case Mips::LD_H:
92   case Mips::ST_H:
93     return 2;
94   case Mips::LD_W:
95   case Mips::ST_W:
96     return 4;
97   case Mips::LD_D:
98   case Mips::ST_D:
99     return 8;
100   default:
101     return 1;
102   }
103 }
104 
105 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
106                                      unsigned OpNo, int FrameIndex,
107                                      uint64_t StackSize,
108                                      int64_t SPOffset) const {
109   MachineInstr &MI = *II;
110   MachineFunction &MF = *MI.getParent()->getParent();
111   MachineFrameInfo *MFI = MF.getFrameInfo();
112   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
113 
114   MipsABIInfo ABI =
115       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
116   const MipsRegisterInfo *RegInfo =
117     static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
118 
119   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
120   int MinCSFI = 0;
121   int MaxCSFI = -1;
122 
123   if (CSI.size()) {
124     MinCSFI = CSI[0].getFrameIdx();
125     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
126   }
127 
128   bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
129 
130   // The following stack frame objects are always referenced relative to $sp:
131   //  1. Outgoing arguments.
132   //  2. Pointer to dynamically allocated stack space.
133   //  3. Locations for callee-saved registers.
134   //  4. Locations for eh data registers.
135   // Everything else is referenced relative to whatever register
136   // getFrameRegister() returns.
137   unsigned FrameReg;
138 
139   if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
140     FrameReg = ABI.GetStackPtr();
141   else if (RegInfo->needsStackRealignment(MF)) {
142     if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex))
143       FrameReg = ABI.GetBasePtr();
144     else if (MFI->isFixedObjectIndex(FrameIndex))
145       FrameReg = getFrameRegister(MF);
146     else
147       FrameReg = ABI.GetStackPtr();
148   } else
149     FrameReg = getFrameRegister(MF);
150 
151   // Calculate final offset.
152   // - There is no need to change the offset if the frame object is one of the
153   //   following: an outgoing argument, pointer to a dynamically allocated
154   //   stack space or a $gp restore location,
155   // - If the frame object is any of the following, its offset must be adjusted
156   //   by adding the size of the stack:
157   //   incoming argument, callee-saved register location or local variable.
158   bool IsKill = false;
159   int64_t Offset;
160 
161   Offset = SPOffset + (int64_t)StackSize;
162   Offset += MI.getOperand(OpNo + 1).getImm();
163 
164   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
165 
166   if (!MI.isDebugValue()) {
167     // Make sure Offset fits within the field available.
168     // For MSA instructions, this is a 10-bit signed immediate (scaled by
169     // element size), otherwise it is a 16-bit signed immediate.
170     unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
171     unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
172 
173     if (OffsetBitSize < 16 && isInt<16>(Offset) &&
174         (!isIntN(OffsetBitSize, Offset) ||
175          OffsetToAlignment(Offset, OffsetAlign) != 0)) {
176       // If we have an offset that needs to fit into a signed n-bit immediate
177       // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
178       MachineBasicBlock &MBB = *MI.getParent();
179       DebugLoc DL = II->getDebugLoc();
180       const TargetRegisterClass *PtrRC =
181           ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
182       MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
183       unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
184       const MipsSEInstrInfo &TII =
185           *static_cast<const MipsSEInstrInfo *>(
186               MBB.getParent()->getSubtarget().getInstrInfo());
187       BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
188           .addReg(FrameReg)
189           .addImm(Offset);
190 
191       FrameReg = Reg;
192       Offset = 0;
193       IsKill = true;
194     } else if (!isInt<16>(Offset)) {
195       // Otherwise split the offset into 16-bit pieces and add it in multiple
196       // instructions.
197       MachineBasicBlock &MBB = *MI.getParent();
198       DebugLoc DL = II->getDebugLoc();
199       unsigned NewImm = 0;
200       const MipsSEInstrInfo &TII =
201           *static_cast<const MipsSEInstrInfo *>(
202               MBB.getParent()->getSubtarget().getInstrInfo());
203       unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
204                                        OffsetBitSize == 16 ? &NewImm : nullptr);
205       BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
206         .addReg(Reg, RegState::Kill);
207 
208       FrameReg = Reg;
209       Offset = SignExtend64<16>(NewImm);
210       IsKill = true;
211     }
212   }
213 
214   MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
215   MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
216 }
217