1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsSERegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsSEInstrInfo.h"
19 #include "MipsSubtarget.h"
20 #include "MipsTargetMachine.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/IR/Constants.h"
28 #include "llvm/IR/DebugInfo.h"
29 #include "llvm/IR/Function.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/CommandLine.h"
32 #include "llvm/Support/Debug.h"
33 #include "llvm/Support/ErrorHandling.h"
34 #include "llvm/Support/raw_ostream.h"
35 #include "llvm/Target/TargetFrameLowering.h"
36 #include "llvm/Target/TargetInstrInfo.h"
37 #include "llvm/Target/TargetMachine.h"
38 #include "llvm/Target/TargetOptions.h"
39 
40 using namespace llvm;
41 
42 #define DEBUG_TYPE "mips-reg-info"
43 
44 MipsSERegisterInfo::MipsSERegisterInfo() : MipsRegisterInfo() {}
45 
46 bool MipsSERegisterInfo::
47 requiresRegisterScavenging(const MachineFunction &MF) const {
48   return true;
49 }
50 
51 bool MipsSERegisterInfo::
52 requiresFrameIndexScavenging(const MachineFunction &MF) const {
53   return true;
54 }
55 
56 const TargetRegisterClass *
57 MipsSERegisterInfo::intRegClass(unsigned Size) const {
58   if (Size == 4)
59     return &Mips::GPR32RegClass;
60 
61   assert(Size == 8);
62   return &Mips::GPR64RegClass;
63 }
64 
65 /// Get the size of the offset supported by the given load/store.
66 /// The result includes the effects of any scale factors applied to the
67 /// instruction immediate.
68 static inline unsigned getLoadStoreOffsetSizeInBits(const unsigned Opcode) {
69   switch (Opcode) {
70   case Mips::LD_B:
71   case Mips::ST_B:
72     return 10;
73   case Mips::LD_H:
74   case Mips::ST_H:
75     return 10 + 1 /* scale factor */;
76   case Mips::LD_W:
77   case Mips::ST_W:
78     return 10 + 2 /* scale factor */;
79   case Mips::LD_D:
80   case Mips::ST_D:
81     return 10 + 3 /* scale factor */;
82   default:
83     return 16;
84   }
85 }
86 
87 /// Get the scale factor applied to the immediate in the given load/store.
88 static inline unsigned getLoadStoreOffsetAlign(const unsigned Opcode) {
89   switch (Opcode) {
90   case Mips::LD_H:
91   case Mips::ST_H:
92     return 2;
93   case Mips::LD_W:
94   case Mips::ST_W:
95     return 4;
96   case Mips::LD_D:
97   case Mips::ST_D:
98     return 8;
99   default:
100     return 1;
101   }
102 }
103 
104 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
105                                      unsigned OpNo, int FrameIndex,
106                                      uint64_t StackSize,
107                                      int64_t SPOffset) const {
108   MachineInstr &MI = *II;
109   MachineFunction &MF = *MI.getParent()->getParent();
110   MachineFrameInfo *MFI = MF.getFrameInfo();
111   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
112 
113   MipsABIInfo ABI =
114       static_cast<const MipsTargetMachine &>(MF.getTarget()).getABI();
115   const MipsRegisterInfo *RegInfo =
116     static_cast<const MipsRegisterInfo *>(MF.getSubtarget().getRegisterInfo());
117 
118   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
119   int MinCSFI = 0;
120   int MaxCSFI = -1;
121 
122   if (CSI.size()) {
123     MinCSFI = CSI[0].getFrameIdx();
124     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
125   }
126 
127   bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
128   bool IsISRRegFI = MipsFI->isISRRegFI(FrameIndex);
129   // The following stack frame objects are always referenced relative to $sp:
130   //  1. Outgoing arguments.
131   //  2. Pointer to dynamically allocated stack space.
132   //  3. Locations for callee-saved registers.
133   //  4. Locations for eh data registers.
134   //  5. Locations for ISR saved Coprocessor 0 registers 12 & 14.
135   // Everything else is referenced relative to whatever register
136   // getFrameRegister() returns.
137   unsigned FrameReg;
138 
139   if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI ||
140       IsISRRegFI)
141     FrameReg = ABI.GetStackPtr();
142   else if (RegInfo->needsStackRealignment(MF)) {
143     if (MFI->hasVarSizedObjects() && !MFI->isFixedObjectIndex(FrameIndex))
144       FrameReg = ABI.GetBasePtr();
145     else if (MFI->isFixedObjectIndex(FrameIndex))
146       FrameReg = getFrameRegister(MF);
147     else
148       FrameReg = ABI.GetStackPtr();
149   } else
150     FrameReg = getFrameRegister(MF);
151 
152   // Calculate final offset.
153   // - There is no need to change the offset if the frame object is one of the
154   //   following: an outgoing argument, pointer to a dynamically allocated
155   //   stack space or a $gp restore location,
156   // - If the frame object is any of the following, its offset must be adjusted
157   //   by adding the size of the stack:
158   //   incoming argument, callee-saved register location or local variable.
159   bool IsKill = false;
160   int64_t Offset;
161 
162   Offset = SPOffset + (int64_t)StackSize;
163   Offset += MI.getOperand(OpNo + 1).getImm();
164 
165   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
166 
167   if (!MI.isDebugValue()) {
168     // Make sure Offset fits within the field available.
169     // For MSA instructions, this is a 10-bit signed immediate (scaled by
170     // element size), otherwise it is a 16-bit signed immediate.
171     unsigned OffsetBitSize = getLoadStoreOffsetSizeInBits(MI.getOpcode());
172     unsigned OffsetAlign = getLoadStoreOffsetAlign(MI.getOpcode());
173 
174     if (OffsetBitSize < 16 && isInt<16>(Offset) &&
175         (!isIntN(OffsetBitSize, Offset) ||
176          OffsetToAlignment(Offset, OffsetAlign) != 0)) {
177       // If we have an offset that needs to fit into a signed n-bit immediate
178       // (where n < 16) and doesn't, but does fit into 16-bits then use an ADDiu
179       MachineBasicBlock &MBB = *MI.getParent();
180       DebugLoc DL = II->getDebugLoc();
181       const TargetRegisterClass *PtrRC =
182           ABI.ArePtrs64bit() ? &Mips::GPR64RegClass : &Mips::GPR32RegClass;
183       MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
184       unsigned Reg = RegInfo.createVirtualRegister(PtrRC);
185       const MipsSEInstrInfo &TII =
186           *static_cast<const MipsSEInstrInfo *>(
187               MBB.getParent()->getSubtarget().getInstrInfo());
188       BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAddiuOp()), Reg)
189           .addReg(FrameReg)
190           .addImm(Offset);
191 
192       FrameReg = Reg;
193       Offset = 0;
194       IsKill = true;
195     } else if (!isInt<16>(Offset)) {
196       // Otherwise split the offset into 16-bit pieces and add it in multiple
197       // instructions.
198       MachineBasicBlock &MBB = *MI.getParent();
199       DebugLoc DL = II->getDebugLoc();
200       unsigned NewImm = 0;
201       const MipsSEInstrInfo &TII =
202           *static_cast<const MipsSEInstrInfo *>(
203               MBB.getParent()->getSubtarget().getInstrInfo());
204       unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL,
205                                        OffsetBitSize == 16 ? &NewImm : nullptr);
206       BuildMI(MBB, II, DL, TII.get(ABI.GetPtrAdduOp()), Reg).addReg(FrameReg)
207         .addReg(Reg, RegState::Kill);
208 
209       FrameReg = Reg;
210       Offset = SignExtend64<16>(NewImm);
211       IsKill = true;
212     }
213   }
214 
215   MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
216   MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
217 }
218