1 //===-- MipsSERegisterInfo.cpp - MIPS32/64 Register Information -== -------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the MIPS32/64 implementation of the TargetRegisterInfo
11 // class.
12 //
13 //===----------------------------------------------------------------------===//
14 
15 #include "MipsSERegisterInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsSEInstrInfo.h"
20 #include "MipsSubtarget.h"
21 #include "llvm/ADT/BitVector.h"
22 #include "llvm/ADT/STLExtras.h"
23 #include "llvm/CodeGen/MachineFrameInfo.h"
24 #include "llvm/CodeGen/MachineFunction.h"
25 #include "llvm/CodeGen/MachineInstrBuilder.h"
26 #include "llvm/CodeGen/MachineRegisterInfo.h"
27 #include "llvm/CodeGen/ValueTypes.h"
28 #include "llvm/DebugInfo.h"
29 #include "llvm/IR/Constants.h"
30 #include "llvm/IR/Function.h"
31 #include "llvm/IR/Type.h"
32 #include "llvm/Support/CommandLine.h"
33 #include "llvm/Support/Debug.h"
34 #include "llvm/Support/ErrorHandling.h"
35 #include "llvm/Support/raw_ostream.h"
36 #include "llvm/Target/TargetFrameLowering.h"
37 #include "llvm/Target/TargetInstrInfo.h"
38 #include "llvm/Target/TargetMachine.h"
39 #include "llvm/Target/TargetOptions.h"
40 
41 using namespace llvm;
42 
43 MipsSERegisterInfo::MipsSERegisterInfo(const MipsSubtarget &ST,
44                                        const MipsSEInstrInfo &I)
45   : MipsRegisterInfo(ST), TII(I) {}
46 
47 bool MipsSERegisterInfo::
48 requiresRegisterScavenging(const MachineFunction &MF) const {
49   return true;
50 }
51 
52 bool MipsSERegisterInfo::
53 requiresFrameIndexScavenging(const MachineFunction &MF) const {
54   return true;
55 }
56 
57 const TargetRegisterClass *
58 MipsSERegisterInfo::intRegClass(unsigned Size) const {
59   if (Size == 4)
60     return &Mips::CPURegsRegClass;
61 
62   assert(Size == 8);
63   return &Mips::CPU64RegsRegClass;
64 }
65 
66 void MipsSERegisterInfo::eliminateFI(MachineBasicBlock::iterator II,
67                                      unsigned OpNo, int FrameIndex,
68                                      uint64_t StackSize,
69                                      int64_t SPOffset) const {
70   MachineInstr &MI = *II;
71   MachineFunction &MF = *MI.getParent()->getParent();
72   MachineFrameInfo *MFI = MF.getFrameInfo();
73   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
74 
75   const std::vector<CalleeSavedInfo> &CSI = MFI->getCalleeSavedInfo();
76   int MinCSFI = 0;
77   int MaxCSFI = -1;
78 
79   if (CSI.size()) {
80     MinCSFI = CSI[0].getFrameIdx();
81     MaxCSFI = CSI[CSI.size() - 1].getFrameIdx();
82   }
83 
84   bool EhDataRegFI = MipsFI->isEhDataRegFI(FrameIndex);
85 
86   // The following stack frame objects are always referenced relative to $sp:
87   //  1. Outgoing arguments.
88   //  2. Pointer to dynamically allocated stack space.
89   //  3. Locations for callee-saved registers.
90   //  4. Locations for eh data registers.
91   // Everything else is referenced relative to whatever register
92   // getFrameRegister() returns.
93   unsigned FrameReg;
94 
95   if ((FrameIndex >= MinCSFI && FrameIndex <= MaxCSFI) || EhDataRegFI)
96     FrameReg = Subtarget.isABI_N64() ? Mips::SP_64 : Mips::SP;
97   else
98     FrameReg = getFrameRegister(MF);
99 
100   // Calculate final offset.
101   // - There is no need to change the offset if the frame object is one of the
102   //   following: an outgoing argument, pointer to a dynamically allocated
103   //   stack space or a $gp restore location,
104   // - If the frame object is any of the following, its offset must be adjusted
105   //   by adding the size of the stack:
106   //   incoming argument, callee-saved register location or local variable.
107   bool IsKill = false;
108   int64_t Offset;
109 
110   Offset = SPOffset + (int64_t)StackSize;
111   Offset += MI.getOperand(OpNo + 1).getImm();
112 
113   DEBUG(errs() << "Offset     : " << Offset << "\n" << "<--------->\n");
114 
115   // If MI is not a debug value, make sure Offset fits in the 16-bit immediate
116   // field.
117   if (!MI.isDebugValue() && !isInt<16>(Offset)) {
118     MachineBasicBlock &MBB = *MI.getParent();
119     DebugLoc DL = II->getDebugLoc();
120     unsigned ADDu = Subtarget.isABI_N64() ? Mips::DADDu : Mips::ADDu;
121     unsigned NewImm;
122 
123     unsigned Reg = TII.loadImmediate(Offset, MBB, II, DL, &NewImm);
124     BuildMI(MBB, II, DL, TII.get(ADDu), Reg).addReg(FrameReg)
125       .addReg(Reg, RegState::Kill);
126 
127     FrameReg = Reg;
128     Offset = SignExtend64<16>(NewImm);
129     IsKill = true;
130   }
131 
132   MI.getOperand(OpNo).ChangeToRegister(FrameReg, false, false, IsKill);
133   MI.getOperand(OpNo + 1).ChangeToImmediate(Offset);
134 }
135