1 //===-- MipsSEInstrInfo.h - Mips32/64 Instruction Information ---*- C++ -*-===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #ifndef LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
15 #define LLVM_LIB_TARGET_MIPS_MIPSSEINSTRINFO_H
16 
17 #include "MipsInstrInfo.h"
18 #include "MipsSERegisterInfo.h"
19 
20 namespace llvm {
21 
22 class MipsSEInstrInfo : public MipsInstrInfo {
23   const MipsSERegisterInfo RI;
24 
25 public:
26   explicit MipsSEInstrInfo(const MipsSubtarget &STI);
27 
28   const MipsRegisterInfo &getRegisterInfo() const override;
29 
30   /// isLoadFromStackSlot - If the specified machine instruction is a direct
31   /// load from a stack slot, return the virtual or physical register number of
32   /// the destination along with the FrameIndex of the loaded stack slot.  If
33   /// not, return 0.  This predicate must return 0 if the instruction has
34   /// any side effects other than loading from the stack slot.
35   unsigned isLoadFromStackSlot(const MachineInstr &MI,
36                                int &FrameIndex) const override;
37 
38   /// isStoreToStackSlot - If the specified machine instruction is a direct
39   /// store to a stack slot, return the virtual or physical register number of
40   /// the source reg along with the FrameIndex of the loaded stack slot.  If
41   /// not, return 0.  This predicate must return 0 if the instruction has
42   /// any side effects other than storing to the stack slot.
43   unsigned isStoreToStackSlot(const MachineInstr &MI,
44                               int &FrameIndex) const override;
45 
46   void copyPhysReg(MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
47                    const DebugLoc &DL, unsigned DestReg, unsigned SrcReg,
48                    bool KillSrc) const override;
49 
50   void storeRegToStack(MachineBasicBlock &MBB,
51                        MachineBasicBlock::iterator MI,
52                        unsigned SrcReg, bool isKill, int FrameIndex,
53                        const TargetRegisterClass *RC,
54                        const TargetRegisterInfo *TRI,
55                        int64_t Offset) const override;
56 
57   void loadRegFromStack(MachineBasicBlock &MBB,
58                         MachineBasicBlock::iterator MI,
59                         unsigned DestReg, int FrameIndex,
60                         const TargetRegisterClass *RC,
61                         const TargetRegisterInfo *TRI,
62                         int64_t Offset) const override;
63 
64   bool expandPostRAPseudo(MachineInstr &MI) const override;
65 
66   unsigned getOppositeBranchOpc(unsigned Opc) const override;
67 
68   /// Adjust SP by Amount bytes.
69   void adjustStackPtr(unsigned SP, int64_t Amount, MachineBasicBlock &MBB,
70                       MachineBasicBlock::iterator I) const override;
71 
72   /// Emit a series of instructions to load an immediate. If NewImm is a
73   /// non-NULL parameter, the last instruction is not emitted, but instead
74   /// its immediate operand is returned in NewImm.
75   unsigned loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
76                          MachineBasicBlock::iterator II, const DebugLoc &DL,
77                          unsigned *NewImm) const;
78 
79 protected:
80   /// If the specific machine instruction is a instruction that moves/copies
81   /// value from one register to another register return true along with
82   /// @Source machine operand and @Destination machine operand.
83   bool isCopyInstrImpl(const MachineInstr &MI, const MachineOperand *&Source,
84                        const MachineOperand *&Destination) const override;
85 
86 private:
87   unsigned getAnalyzableBrOpc(unsigned Opc) const override;
88 
89   void expandRetRA(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
90 
91   void expandERet(MachineBasicBlock &MBB, MachineBasicBlock::iterator I) const;
92 
93   std::pair<bool, bool> compareOpndSize(unsigned Opc,
94                                         const MachineFunction &MF) const;
95 
96   void expandPseudoMFHiLo(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
97                           unsigned NewOpc) const;
98 
99   void expandPseudoMTLoHi(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
100                           unsigned LoOpc, unsigned HiOpc,
101                           bool HasExplicitDef) const;
102 
103   /// Expand pseudo Int-to-FP conversion instructions.
104   ///
105   /// For example, the following pseudo instruction
106   ///  PseudoCVT_D32_W D2, A5
107   /// gets expanded into these two instructions:
108   ///  MTC1 F4, A5
109   ///  CVT_D32_W D2, F4
110   ///
111   /// We do this expansion post-RA to avoid inserting a floating point copy
112   /// instruction between MTC1 and CVT_D32_W.
113   void expandCvtFPInt(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
114                       unsigned CvtOpc, unsigned MovOpc, bool IsI64) const;
115 
116   void expandExtractElementF64(MachineBasicBlock &MBB,
117                                MachineBasicBlock::iterator I, bool isMicroMips,
118                                bool FP64) const;
119   void expandBuildPairF64(MachineBasicBlock &MBB,
120                           MachineBasicBlock::iterator I, bool isMicroMips,
121                           bool FP64) const;
122   void expandEhReturn(MachineBasicBlock &MBB,
123                       MachineBasicBlock::iterator I) const;
124 };
125 
126 }
127 
128 #endif
129