1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSEInstrInfo.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MipsAnalyzeImmediate.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 using namespace llvm; 27 28 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) 29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), 30 RI() {} 31 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34 } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 42 int &FrameIndex) const { 43 unsigned Opc = MI.getOpcode(); 44 45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 47 if ((MI.getOperand(1).isFI()) && // is a stack slot 48 (MI.getOperand(2).isImm()) && // the imm is zero 49 (isZeroImm(MI.getOperand(2)))) { 50 FrameIndex = MI.getOperand(1).getIndex(); 51 return MI.getOperand(0).getReg(); 52 } 53 } 54 55 return 0; 56 } 57 58 /// isStoreToStackSlot - If the specified machine instruction is a direct 59 /// store to a stack slot, return the virtual or physical register number of 60 /// the source reg along with the FrameIndex of the loaded stack slot. If 61 /// not, return 0. This predicate must return 0 if the instruction has 62 /// any side effects other than storing to the stack slot. 63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 64 int &FrameIndex) const { 65 unsigned Opc = MI.getOpcode(); 66 67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { 69 if ((MI.getOperand(1).isFI()) && // is a stack slot 70 (MI.getOperand(2).isImm()) && // the imm is zero 71 (isZeroImm(MI.getOperand(2)))) { 72 FrameIndex = MI.getOperand(1).getIndex(); 73 return MI.getOperand(0).getReg(); 74 } 75 } 76 return 0; 77 } 78 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator I, 81 const DebugLoc &DL, unsigned DestReg, 82 unsigned SrcReg, bool KillSrc) const { 83 unsigned Opc = 0, ZeroReg = 0; 84 bool isMicroMips = Subtarget.inMicroMipsMode(); 85 86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 87 if (Mips::GPR32RegClass.contains(SrcReg)) { 88 if (isMicroMips) 89 Opc = Mips::MOVE16_MM; 90 else 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 92 } else if (Mips::CCRRegClass.contains(SrcReg)) 93 Opc = Mips::CFC1; 94 else if (Mips::FGR32RegClass.contains(SrcReg)) 95 Opc = Mips::MFC1; 96 else if (Mips::HI32RegClass.contains(SrcReg)) { 97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 98 SrcReg = 0; 99 } else if (Mips::LO32RegClass.contains(SrcReg)) { 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 101 SrcReg = 0; 102 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) 103 Opc = Mips::MFHI_DSP; 104 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 105 Opc = Mips::MFLO_DSP; 106 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 109 return; 110 } 111 else if (Mips::MSACtrlRegClass.contains(SrcReg)) 112 Opc = Mips::CFCMSA; 113 } 114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 115 if (Mips::CCRRegClass.contains(DestReg)) 116 Opc = Mips::CTC1; 117 else if (Mips::FGR32RegClass.contains(DestReg)) 118 Opc = Mips::MTC1; 119 else if (Mips::HI32RegClass.contains(DestReg)) 120 Opc = Mips::MTHI, DestReg = 0; 121 else if (Mips::LO32RegClass.contains(DestReg)) 122 Opc = Mips::MTLO, DestReg = 0; 123 else if (Mips::HI32DSPRegClass.contains(DestReg)) 124 Opc = Mips::MTHI_DSP; 125 else if (Mips::LO32DSPRegClass.contains(DestReg)) 126 Opc = Mips::MTLO_DSP; 127 else if (Mips::DSPCCRegClass.contains(DestReg)) { 128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 130 .addReg(DestReg, RegState::ImplicitDefine); 131 return; 132 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { 133 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) 134 .addReg(DestReg) 135 .addReg(SrcReg, getKillRegState(KillSrc)); 136 return; 137 } 138 } 139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 140 Opc = Mips::FMOV_S; 141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 142 Opc = Mips::FMOV_D32; 143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 144 Opc = Mips::FMOV_D64; 145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 146 if (Mips::GPR64RegClass.contains(SrcReg)) 147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 148 else if (Mips::HI64RegClass.contains(SrcReg)) 149 Opc = Mips::MFHI64, SrcReg = 0; 150 else if (Mips::LO64RegClass.contains(SrcReg)) 151 Opc = Mips::MFLO64, SrcReg = 0; 152 else if (Mips::FGR64RegClass.contains(SrcReg)) 153 Opc = Mips::DMFC1; 154 } 155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 156 if (Mips::HI64RegClass.contains(DestReg)) 157 Opc = Mips::MTHI64, DestReg = 0; 158 else if (Mips::LO64RegClass.contains(DestReg)) 159 Opc = Mips::MTLO64, DestReg = 0; 160 else if (Mips::FGR64RegClass.contains(DestReg)) 161 Opc = Mips::DMTC1; 162 } 163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 164 if (Mips::MSA128BRegClass.contains(SrcReg)) 165 Opc = Mips::MOVE_V; 166 } 167 168 assert(Opc && "Cannot copy registers"); 169 170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 171 172 if (DestReg) 173 MIB.addReg(DestReg, RegState::Define); 174 175 if (SrcReg) 176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 177 178 if (ZeroReg) 179 MIB.addReg(ZeroReg); 180 } 181 182 void MipsSEInstrInfo:: 183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 184 unsigned SrcReg, bool isKill, int FI, 185 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 186 int64_t Offset) const { 187 DebugLoc DL; 188 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 189 190 unsigned Opc = 0; 191 192 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 193 Opc = Mips::SW; 194 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 195 Opc = Mips::SD; 196 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 197 Opc = Mips::STORE_ACC64; 198 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 199 Opc = Mips::STORE_ACC64DSP; 200 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 201 Opc = Mips::STORE_ACC128; 202 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 203 Opc = Mips::STORE_CCOND_DSP; 204 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 205 Opc = Mips::SWC1; 206 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 207 Opc = Mips::SDC1; 208 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 209 Opc = Mips::SDC164; 210 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 211 Opc = Mips::ST_B; 212 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 213 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 214 Opc = Mips::ST_H; 215 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 216 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 217 Opc = Mips::ST_W; 218 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 219 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 220 Opc = Mips::ST_D; 221 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 222 Opc = Mips::SW; 223 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 224 Opc = Mips::SD; 225 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 226 Opc = Mips::SW; 227 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 228 Opc = Mips::SD; 229 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 230 Opc = Mips::SWDSP; 231 232 // Hi, Lo are normally caller save but they are callee save 233 // for interrupt handling. 234 const Function &Func = MBB.getParent()->getFunction(); 235 if (Func.hasFnAttribute("interrupt")) { 236 if (Mips::HI32RegClass.hasSubClassEq(RC)) { 237 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); 238 SrcReg = Mips::K0; 239 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { 240 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); 241 SrcReg = Mips::K0_64; 242 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { 243 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); 244 SrcReg = Mips::K0; 245 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { 246 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); 247 SrcReg = Mips::K0_64; 248 } 249 } 250 251 assert(Opc && "Register class not handled!"); 252 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 253 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 254 } 255 256 void MipsSEInstrInfo:: 257 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 258 unsigned DestReg, int FI, const TargetRegisterClass *RC, 259 const TargetRegisterInfo *TRI, int64_t Offset) const { 260 DebugLoc DL; 261 if (I != MBB.end()) DL = I->getDebugLoc(); 262 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 263 unsigned Opc = 0; 264 265 const Function &Func = MBB.getParent()->getFunction(); 266 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && 267 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || 268 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); 269 270 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 271 Opc = Mips::LW; 272 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 273 Opc = Mips::LD; 274 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 275 Opc = Mips::LOAD_ACC64; 276 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 277 Opc = Mips::LOAD_ACC64DSP; 278 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 279 Opc = Mips::LOAD_ACC128; 280 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 281 Opc = Mips::LOAD_CCOND_DSP; 282 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 283 Opc = Mips::LWC1; 284 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 285 Opc = Mips::LDC1; 286 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 287 Opc = Mips::LDC164; 288 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 289 Opc = Mips::LD_B; 290 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 291 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 292 Opc = Mips::LD_H; 293 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 294 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 295 Opc = Mips::LD_W; 296 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 297 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 298 Opc = Mips::LD_D; 299 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 300 Opc = Mips::LW; 301 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 302 Opc = Mips::LD; 303 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 304 Opc = Mips::LW; 305 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 306 Opc = Mips::LD; 307 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 308 Opc = Mips::LWDSP; 309 310 assert(Opc && "Register class not handled!"); 311 312 if (!ReqIndirectLoad) 313 BuildMI(MBB, I, DL, get(Opc), DestReg) 314 .addFrameIndex(FI) 315 .addImm(Offset) 316 .addMemOperand(MMO); 317 else { 318 // Load HI/LO through K0. Notably the DestReg is encoded into the 319 // instruction itself. 320 unsigned Reg = Mips::K0; 321 unsigned LdOp = Mips::MTLO; 322 if (DestReg == Mips::HI0) 323 LdOp = Mips::MTHI; 324 325 if (Subtarget.getABI().ArePtrs64bit()) { 326 Reg = Mips::K0_64; 327 if (DestReg == Mips::HI0_64) 328 LdOp = Mips::MTHI64; 329 else 330 LdOp = Mips::MTLO64; 331 } 332 333 BuildMI(MBB, I, DL, get(Opc), Reg) 334 .addFrameIndex(FI) 335 .addImm(Offset) 336 .addMemOperand(MMO); 337 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); 338 } 339 } 340 341 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 342 MachineBasicBlock &MBB = *MI.getParent(); 343 bool isMicroMips = Subtarget.inMicroMipsMode(); 344 unsigned Opc; 345 346 switch (MI.getDesc().getOpcode()) { 347 default: 348 return false; 349 case Mips::RetRA: 350 expandRetRA(MBB, MI); 351 break; 352 case Mips::ERet: 353 expandERet(MBB, MI); 354 break; 355 case Mips::PseudoMFHI: 356 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 357 expandPseudoMFHiLo(MBB, MI, Opc); 358 break; 359 case Mips::PseudoMFLO: 360 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 361 expandPseudoMFHiLo(MBB, MI, Opc); 362 break; 363 case Mips::PseudoMFHI64: 364 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); 365 break; 366 case Mips::PseudoMFLO64: 367 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); 368 break; 369 case Mips::PseudoMTLOHI: 370 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); 371 break; 372 case Mips::PseudoMTLOHI64: 373 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); 374 break; 375 case Mips::PseudoMTLOHI_DSP: 376 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); 377 break; 378 case Mips::PseudoCVT_S_W: 379 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); 380 break; 381 case Mips::PseudoCVT_D32_W: 382 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; 383 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); 384 break; 385 case Mips::PseudoCVT_S_L: 386 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); 387 break; 388 case Mips::PseudoCVT_D64_W: 389 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; 390 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); 391 break; 392 case Mips::PseudoCVT_D64_L: 393 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); 394 break; 395 case Mips::BuildPairF64: 396 expandBuildPairF64(MBB, MI, isMicroMips, false); 397 break; 398 case Mips::BuildPairF64_64: 399 expandBuildPairF64(MBB, MI, isMicroMips, true); 400 break; 401 case Mips::ExtractElementF64: 402 expandExtractElementF64(MBB, MI, isMicroMips, false); 403 break; 404 case Mips::ExtractElementF64_64: 405 expandExtractElementF64(MBB, MI, isMicroMips, true); 406 break; 407 case Mips::MIPSeh_return32: 408 case Mips::MIPSeh_return64: 409 expandEhReturn(MBB, MI); 410 break; 411 } 412 413 MBB.erase(MI); 414 return true; 415 } 416 417 /// getOppositeBranchOpc - Return the inverse of the specified 418 /// opcode, e.g. turning BEQ to BNE. 419 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { 420 switch (Opc) { 421 default: llvm_unreachable("Illegal opcode!"); 422 case Mips::BEQ: return Mips::BNE; 423 case Mips::BEQ_MM: return Mips::BNE_MM; 424 case Mips::BNE: return Mips::BEQ; 425 case Mips::BNE_MM: return Mips::BEQ_MM; 426 case Mips::BGTZ: return Mips::BLEZ; 427 case Mips::BGEZ: return Mips::BLTZ; 428 case Mips::BLTZ: return Mips::BGEZ; 429 case Mips::BLEZ: return Mips::BGTZ; 430 case Mips::BEQ64: return Mips::BNE64; 431 case Mips::BNE64: return Mips::BEQ64; 432 case Mips::BGTZ64: return Mips::BLEZ64; 433 case Mips::BGEZ64: return Mips::BLTZ64; 434 case Mips::BLTZ64: return Mips::BGEZ64; 435 case Mips::BLEZ64: return Mips::BGTZ64; 436 case Mips::BC1T: return Mips::BC1F; 437 case Mips::BC1F: return Mips::BC1T; 438 case Mips::BEQZC_MM: return Mips::BNEZC_MM; 439 case Mips::BNEZC_MM: return Mips::BEQZC_MM; 440 case Mips::BEQZC: return Mips::BNEZC; 441 case Mips::BNEZC: return Mips::BEQZC; 442 case Mips::BEQC: return Mips::BNEC; 443 case Mips::BNEC: return Mips::BEQC; 444 case Mips::BGTZC: return Mips::BLEZC; 445 case Mips::BGEZC: return Mips::BLTZC; 446 case Mips::BLTZC: return Mips::BGEZC; 447 case Mips::BLEZC: return Mips::BGTZC; 448 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; 449 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; 450 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; 451 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; 452 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; 453 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; 454 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; 455 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; 456 case Mips::BEQZC64: return Mips::BNEZC64; 457 case Mips::BNEZC64: return Mips::BEQZC64; 458 case Mips::BEQC64: return Mips::BNEC64; 459 case Mips::BNEC64: return Mips::BEQC64; 460 case Mips::BGEC64: return Mips::BLTC64; 461 case Mips::BGEUC64: return Mips::BLTUC64; 462 case Mips::BLTC64: return Mips::BGEC64; 463 case Mips::BLTUC64: return Mips::BGEUC64; 464 case Mips::BGTZC64: return Mips::BLEZC64; 465 case Mips::BGEZC64: return Mips::BLTZC64; 466 case Mips::BLTZC64: return Mips::BGEZC64; 467 case Mips::BLEZC64: return Mips::BGTZC64; 468 case Mips::BBIT0: return Mips::BBIT1; 469 case Mips::BBIT1: return Mips::BBIT0; 470 case Mips::BBIT032: return Mips::BBIT132; 471 case Mips::BBIT132: return Mips::BBIT032; 472 } 473 } 474 475 /// Adjust SP by Amount bytes. 476 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 477 MachineBasicBlock &MBB, 478 MachineBasicBlock::iterator I) const { 479 MipsABIInfo ABI = Subtarget.getABI(); 480 DebugLoc DL; 481 unsigned ADDiu = ABI.GetPtrAddiuOp(); 482 483 if (Amount == 0) 484 return; 485 486 if (isInt<16>(Amount)) { 487 // addi sp, sp, amount 488 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 489 } else { 490 // For numbers which are not 16bit integers we synthesize Amount inline 491 // then add or subtract it from sp. 492 unsigned Opc = ABI.GetPtrAdduOp(); 493 if (Amount < 0) { 494 Opc = ABI.GetPtrSubuOp(); 495 Amount = -Amount; 496 } 497 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); 498 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 499 } 500 } 501 502 /// This function generates the sequence of instructions needed to get the 503 /// result of adding register REG and immediate IMM. 504 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 505 MachineBasicBlock::iterator II, 506 const DebugLoc &DL, 507 unsigned *NewImm) const { 508 MipsAnalyzeImmediate AnalyzeImm; 509 const MipsSubtarget &STI = Subtarget; 510 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 511 unsigned Size = STI.isABI_N64() ? 64 : 32; 512 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 513 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 514 const TargetRegisterClass *RC = STI.isABI_N64() ? 515 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 516 bool LastInstrIsADDiu = NewImm; 517 518 const MipsAnalyzeImmediate::InstSeq &Seq = 519 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 520 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 521 522 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 523 524 // The first instruction can be a LUi, which is different from other 525 // instructions (ADDiu, ORI and SLL) in that it does not have a register 526 // operand. 527 unsigned Reg = RegInfo.createVirtualRegister(RC); 528 529 if (Inst->Opc == LUi) 530 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 531 else 532 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 533 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 534 535 // Build the remaining instructions in Seq. 536 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 537 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 538 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 539 540 if (LastInstrIsADDiu) 541 *NewImm = Inst->ImmOpnd; 542 543 return Reg; 544 } 545 546 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 547 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || 548 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || 549 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || 550 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || 551 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || 552 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || 553 Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || 554 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || 555 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || 556 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || 557 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || 558 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || 559 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || 560 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || 561 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || 562 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || 563 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || 564 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || 565 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || 566 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || 567 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || 568 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || 569 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || 570 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; 571 } 572 573 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, 574 MachineBasicBlock::iterator I) const { 575 576 MachineInstrBuilder MIB; 577 if (Subtarget.isGP64bit()) 578 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) 579 .addReg(Mips::RA_64, RegState::Undef); 580 else 581 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)) 582 .addReg(Mips::RA, RegState::Undef); 583 584 // Retain any imp-use flags. 585 for (auto & MO : I->operands()) { 586 if (MO.isImplicit()) 587 MIB.add(MO); 588 } 589 } 590 591 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB, 592 MachineBasicBlock::iterator I) const { 593 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); 594 } 595 596 std::pair<bool, bool> 597 MipsSEInstrInfo::compareOpndSize(unsigned Opc, 598 const MachineFunction &MF) const { 599 const MCInstrDesc &Desc = get(Opc); 600 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 601 const MipsRegisterInfo *RI = &getRegisterInfo(); 602 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); 603 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); 604 605 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize); 606 } 607 608 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB, 609 MachineBasicBlock::iterator I, 610 unsigned NewOpc) const { 611 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg()); 612 } 613 614 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB, 615 MachineBasicBlock::iterator I, 616 unsigned LoOpc, 617 unsigned HiOpc, 618 bool HasExplicitDef) const { 619 // Expand 620 // lo_hi pseudomtlohi $gpr0, $gpr1 621 // to these two instructions: 622 // mtlo $gpr0 623 // mthi $gpr1 624 625 DebugLoc DL = I->getDebugLoc(); 626 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); 627 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); 628 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); 629 630 // Add lo/hi registers if the mtlo/hi instructions created have explicit 631 // def registers. 632 if (HasExplicitDef) { 633 unsigned DstReg = I->getOperand(0).getReg(); 634 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 635 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 636 LoInst.addReg(DstLo, RegState::Define); 637 HiInst.addReg(DstHi, RegState::Define); 638 } 639 640 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); 641 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); 642 } 643 644 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, 645 MachineBasicBlock::iterator I, 646 unsigned CvtOpc, unsigned MovOpc, 647 bool IsI64) const { 648 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); 649 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 650 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 651 unsigned KillSrc = getKillRegState(Src.isKill()); 652 DebugLoc DL = I->getDebugLoc(); 653 bool DstIsLarger, SrcIsLarger; 654 655 std::tie(DstIsLarger, SrcIsLarger) = 656 compareOpndSize(CvtOpc, *MBB.getParent()); 657 658 if (DstIsLarger) 659 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 660 661 if (SrcIsLarger) 662 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 663 664 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); 665 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 666 } 667 668 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, 669 MachineBasicBlock::iterator I, 670 bool isMicroMips, 671 bool FP64) const { 672 unsigned DstReg = I->getOperand(0).getReg(); 673 unsigned SrcReg = I->getOperand(1).getReg(); 674 unsigned N = I->getOperand(2).getImm(); 675 DebugLoc dl = I->getDebugLoc(); 676 677 assert(N < 2 && "Invalid immediate"); 678 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; 679 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 680 681 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 682 // in MipsSEFrameLowering.cpp. 683 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 684 685 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 686 // in MipsSEFrameLowering.cpp. 687 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 688 689 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { 690 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we 691 // claim to read the whole 64-bits as part of a white lie used to 692 // temporarily work around a widespread bug in the -mfp64 support. 693 // The problem is that none of the 32-bit fpu ops mention the fact 694 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 695 // requires a major overhaul of the FPU implementation which can't 696 // be done right now due to time constraints. 697 // MFHC1 is one of two instructions that are affected since they are 698 // the only instructions that don't read the lower 32-bits. 699 // We therefore pretend that it reads the bottom 32-bits to 700 // artificially create a dependency and prevent the scheduler 701 // changing the behaviour of the code. 702 BuildMI(MBB, I, dl, 703 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) 704 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), 705 DstReg) 706 .addReg(SrcReg); 707 } else 708 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); 709 } 710 711 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, 712 MachineBasicBlock::iterator I, 713 bool isMicroMips, bool FP64) const { 714 unsigned DstReg = I->getOperand(0).getReg(); 715 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 716 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 717 DebugLoc dl = I->getDebugLoc(); 718 const TargetRegisterInfo &TRI = getRegisterInfo(); 719 720 // When mthc1 is available, use: 721 // mtc1 Lo, $fp 722 // mthc1 Hi, $fp 723 // 724 // Otherwise, for O32 FPXX ABI: 725 // spill + reload via ldc1 726 // This case is handled by the frame lowering code. 727 // 728 // Otherwise, for FP32: 729 // mtc1 Lo, $fp 730 // mtc1 Hi, $fp + 1 731 // 732 // The case where dmtc1 is available doesn't need to be handled here 733 // because it never creates a BuildPairF64 node. 734 735 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 736 // in MipsSEFrameLowering.cpp. 737 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 738 739 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 740 // in MipsSEFrameLowering.cpp. 741 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 742 743 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 744 .addReg(LoReg); 745 746 if (Subtarget.hasMTHC1()) { 747 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work 748 // around a widespread bug in the -mfp64 support. 749 // The problem is that none of the 32-bit fpu ops mention the fact 750 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 751 // requires a major overhaul of the FPU implementation which can't 752 // be done right now due to time constraints. 753 // MTHC1 is one of two instructions that are affected since they are 754 // the only instructions that don't read the lower 32-bits. 755 // We therefore pretend that it reads the bottom 32-bits to 756 // artificially create a dependency and prevent the scheduler 757 // changing the behaviour of the code. 758 BuildMI(MBB, I, dl, 759 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) 760 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), 761 DstReg) 762 .addReg(DstReg) 763 .addReg(HiReg); 764 } else if (Subtarget.isABI_FPXX()) 765 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); 766 else 767 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) 768 .addReg(HiReg); 769 } 770 771 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, 772 MachineBasicBlock::iterator I) const { 773 // This pseudo instruction is generated as part of the lowering of 774 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 775 // indirect jump to TargetReg 776 MipsABIInfo ABI = Subtarget.getABI(); 777 unsigned ADDU = ABI.GetPtrAdduOp(); 778 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; 779 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; 780 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; 781 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 782 unsigned OffsetReg = I->getOperand(0).getReg(); 783 unsigned TargetReg = I->getOperand(1).getReg(); 784 785 // addu $ra, $v0, $zero 786 // addu $sp, $sp, $v1 787 // jr $ra (via RetRA) 788 const TargetMachine &TM = MBB.getParent()->getTarget(); 789 if (TM.isPositionIndependent()) 790 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) 791 .addReg(TargetReg) 792 .addReg(ZERO); 793 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA) 794 .addReg(TargetReg) 795 .addReg(ZERO); 796 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); 797 expandRetRA(MBB, I); 798 } 799 800 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { 801 return new MipsSEInstrInfo(STI); 802 } 803