1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/CommandLine.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/TargetRegistry.h"
24 
25 using namespace llvm;
26 
27 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
28   : MipsInstrInfo(tm,
29                   tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
30     RI(*tm.getSubtargetImpl()),
31     IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
32 
33 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
34   return RI;
35 }
36 
37 /// isLoadFromStackSlot - If the specified machine instruction is a direct
38 /// load from a stack slot, return the virtual or physical register number of
39 /// the destination along with the FrameIndex of the loaded stack slot.  If
40 /// not, return 0.  This predicate must return 0 if the instruction has
41 /// any side effects other than loading from the stack slot.
42 unsigned MipsSEInstrInfo::
43 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
44 {
45   unsigned Opc = MI->getOpcode();
46 
47   if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
48       (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
49     if ((MI->getOperand(1).isFI()) && // is a stack slot
50         (MI->getOperand(2).isImm()) &&  // the imm is zero
51         (isZeroImm(MI->getOperand(2)))) {
52       FrameIndex = MI->getOperand(1).getIndex();
53       return MI->getOperand(0).getReg();
54     }
55   }
56 
57   return 0;
58 }
59 
60 /// isStoreToStackSlot - If the specified machine instruction is a direct
61 /// store to a stack slot, return the virtual or physical register number of
62 /// the source reg along with the FrameIndex of the loaded stack slot.  If
63 /// not, return 0.  This predicate must return 0 if the instruction has
64 /// any side effects other than storing to the stack slot.
65 unsigned MipsSEInstrInfo::
66 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
67 {
68   unsigned Opc = MI->getOpcode();
69 
70   if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
71       (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
72     if ((MI->getOperand(1).isFI()) && // is a stack slot
73         (MI->getOperand(2).isImm()) &&  // the imm is zero
74         (isZeroImm(MI->getOperand(2)))) {
75       FrameIndex = MI->getOperand(1).getIndex();
76       return MI->getOperand(0).getReg();
77     }
78   }
79   return 0;
80 }
81 
82 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
83                                   MachineBasicBlock::iterator I, DebugLoc DL,
84                                   unsigned DestReg, unsigned SrcReg,
85                                   bool KillSrc) const {
86   unsigned Opc = 0, ZeroReg = 0;
87 
88   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
89     if (Mips::GPR32RegClass.contains(SrcReg))
90       Opc = Mips::ADDu, ZeroReg = Mips::ZERO;
91     else if (Mips::CCRRegClass.contains(SrcReg))
92       Opc = Mips::CFC1;
93     else if (Mips::FGR32RegClass.contains(SrcReg))
94       Opc = Mips::MFC1;
95     else if (Mips::HI32RegClass.contains(SrcReg))
96       Opc = Mips::MFHI, SrcReg = 0;
97     else if (Mips::LO32RegClass.contains(SrcReg))
98       Opc = Mips::MFLO, SrcReg = 0;
99     else if (Mips::HI32DSPRegClass.contains(SrcReg))
100       Opc = Mips::MFHI_DSP;
101     else if (Mips::LO32DSPRegClass.contains(SrcReg))
102       Opc = Mips::MFLO_DSP;
103     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
104       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
105         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
106       return;
107     }
108     else if (Mips::MSACtrlRegClass.contains(SrcReg))
109       Opc = Mips::CFCMSA;
110   }
111   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
112     if (Mips::CCRRegClass.contains(DestReg))
113       Opc = Mips::CTC1;
114     else if (Mips::FGR32RegClass.contains(DestReg))
115       Opc = Mips::MTC1;
116     else if (Mips::HI32RegClass.contains(DestReg))
117       Opc = Mips::MTHI, DestReg = 0;
118     else if (Mips::LO32RegClass.contains(DestReg))
119       Opc = Mips::MTLO, DestReg = 0;
120     else if (Mips::HI32DSPRegClass.contains(DestReg))
121       Opc = Mips::MTHI_DSP;
122     else if (Mips::LO32DSPRegClass.contains(DestReg))
123       Opc = Mips::MTLO_DSP;
124     else if (Mips::DSPCCRegClass.contains(DestReg)) {
125       BuildMI(MBB, I, DL, get(Mips::WRDSP))
126         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
127         .addReg(DestReg, RegState::ImplicitDefine);
128       return;
129     }
130     else if (Mips::MSACtrlRegClass.contains(DestReg))
131       Opc = Mips::CTCMSA;
132   }
133   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
134     Opc = Mips::FMOV_S;
135   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
136     Opc = Mips::FMOV_D32;
137   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
138     Opc = Mips::FMOV_D64;
139   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
140     if (Mips::GPR64RegClass.contains(SrcReg))
141       Opc = Mips::DADDu, ZeroReg = Mips::ZERO_64;
142     else if (Mips::HI64RegClass.contains(SrcReg))
143       Opc = Mips::MFHI64, SrcReg = 0;
144     else if (Mips::LO64RegClass.contains(SrcReg))
145       Opc = Mips::MFLO64, SrcReg = 0;
146     else if (Mips::FGR64RegClass.contains(SrcReg))
147       Opc = Mips::DMFC1;
148   }
149   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
150     if (Mips::HI64RegClass.contains(DestReg))
151       Opc = Mips::MTHI64, DestReg = 0;
152     else if (Mips::LO64RegClass.contains(DestReg))
153       Opc = Mips::MTLO64, DestReg = 0;
154     else if (Mips::FGR64RegClass.contains(DestReg))
155       Opc = Mips::DMTC1;
156   }
157   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
158     if (Mips::MSA128BRegClass.contains(SrcReg))
159       Opc = Mips::MOVE_V;
160   }
161 
162   assert(Opc && "Cannot copy registers");
163 
164   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
165 
166   if (DestReg)
167     MIB.addReg(DestReg, RegState::Define);
168 
169   if (SrcReg)
170     MIB.addReg(SrcReg, getKillRegState(KillSrc));
171 
172   if (ZeroReg)
173     MIB.addReg(ZeroReg);
174 }
175 
176 void MipsSEInstrInfo::
177 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
178                 unsigned SrcReg, bool isKill, int FI,
179                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
180                 int64_t Offset) const {
181   DebugLoc DL;
182   if (I != MBB.end()) DL = I->getDebugLoc();
183   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
184 
185   unsigned Opc = 0;
186 
187   if (Mips::GPR32RegClass.hasSubClassEq(RC))
188     Opc = Mips::SW;
189   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
190     Opc = Mips::SD;
191   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
192     Opc = Mips::STORE_ACC64;
193   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
194     Opc = Mips::STORE_ACC64DSP;
195   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
196     Opc = Mips::STORE_ACC128;
197   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
198     Opc = Mips::STORE_CCOND_DSP;
199   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
200     Opc = Mips::SWC1;
201   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
202     Opc = Mips::SDC1;
203   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
204     Opc = Mips::SDC164;
205   else if (RC->hasType(MVT::v16i8))
206     Opc = Mips::ST_B;
207   else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
208     Opc = Mips::ST_H;
209   else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
210     Opc = Mips::ST_W;
211   else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
212     Opc = Mips::ST_D;
213 
214   assert(Opc && "Register class not handled!");
215   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
216     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
217 }
218 
219 void MipsSEInstrInfo::
220 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
221                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
222                  const TargetRegisterInfo *TRI, int64_t Offset) const {
223   DebugLoc DL;
224   if (I != MBB.end()) DL = I->getDebugLoc();
225   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
226   unsigned Opc = 0;
227 
228   if (Mips::GPR32RegClass.hasSubClassEq(RC))
229     Opc = Mips::LW;
230   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
231     Opc = Mips::LD;
232   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
233     Opc = Mips::LOAD_ACC64;
234   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
235     Opc = Mips::LOAD_ACC64DSP;
236   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
237     Opc = Mips::LOAD_ACC128;
238   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
239     Opc = Mips::LOAD_CCOND_DSP;
240   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
241     Opc = Mips::LWC1;
242   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
243     Opc = Mips::LDC1;
244   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
245     Opc = Mips::LDC164;
246   else if (RC->hasType(MVT::v16i8))
247     Opc = Mips::LD_B;
248   else if (RC->hasType(MVT::v8i16) || RC->hasType(MVT::v8f16))
249     Opc = Mips::LD_H;
250   else if (RC->hasType(MVT::v4i32) || RC->hasType(MVT::v4f32))
251     Opc = Mips::LD_W;
252   else if (RC->hasType(MVT::v2i64) || RC->hasType(MVT::v2f64))
253     Opc = Mips::LD_D;
254 
255   assert(Opc && "Register class not handled!");
256   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
257     .addMemOperand(MMO);
258 }
259 
260 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
261   MachineBasicBlock &MBB = *MI->getParent();
262 
263   switch(MI->getDesc().getOpcode()) {
264   default:
265     return false;
266   case Mips::RetRA:
267     expandRetRA(MBB, MI, Mips::RET);
268     break;
269   case Mips::PseudoMFHI:
270     expandPseudoMFHiLo(MBB, MI, Mips::MFHI);
271     break;
272   case Mips::PseudoMFLO:
273     expandPseudoMFHiLo(MBB, MI, Mips::MFLO);
274     break;
275   case Mips::PseudoMFHI64:
276     expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
277     break;
278   case Mips::PseudoMFLO64:
279     expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
280     break;
281   case Mips::PseudoCVT_S_W:
282     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
283     break;
284   case Mips::PseudoCVT_D32_W:
285     expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
286     break;
287   case Mips::PseudoCVT_S_L:
288     expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
289     break;
290   case Mips::PseudoCVT_D64_W:
291     expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
292     break;
293   case Mips::PseudoCVT_D64_L:
294     expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
295     break;
296   case Mips::BuildPairF64:
297     expandBuildPairF64(MBB, MI, false);
298     break;
299   case Mips::BuildPairF64_64:
300     expandBuildPairF64(MBB, MI, true);
301     break;
302   case Mips::ExtractElementF64:
303     expandExtractElementF64(MBB, MI, false);
304     break;
305   case Mips::ExtractElementF64_64:
306     expandExtractElementF64(MBB, MI, true);
307     break;
308   case Mips::MIPSeh_return32:
309   case Mips::MIPSeh_return64:
310     expandEhReturn(MBB, MI);
311     break;
312   }
313 
314   MBB.erase(MI);
315   return true;
316 }
317 
318 /// getOppositeBranchOpc - Return the inverse of the specified
319 /// opcode, e.g. turning BEQ to BNE.
320 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
321   switch (Opc) {
322   default:           llvm_unreachable("Illegal opcode!");
323   case Mips::BEQ:    return Mips::BNE;
324   case Mips::BNE:    return Mips::BEQ;
325   case Mips::BGTZ:   return Mips::BLEZ;
326   case Mips::BGEZ:   return Mips::BLTZ;
327   case Mips::BLTZ:   return Mips::BGEZ;
328   case Mips::BLEZ:   return Mips::BGTZ;
329   case Mips::BEQ64:  return Mips::BNE64;
330   case Mips::BNE64:  return Mips::BEQ64;
331   case Mips::BGTZ64: return Mips::BLEZ64;
332   case Mips::BGEZ64: return Mips::BLTZ64;
333   case Mips::BLTZ64: return Mips::BGEZ64;
334   case Mips::BLEZ64: return Mips::BGTZ64;
335   case Mips::BC1T:   return Mips::BC1F;
336   case Mips::BC1F:   return Mips::BC1T;
337   }
338 }
339 
340 /// Adjust SP by Amount bytes.
341 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
342                                      MachineBasicBlock &MBB,
343                                      MachineBasicBlock::iterator I) const {
344   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
345   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
346   unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
347   unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
348 
349   if (isInt<16>(Amount))// addi sp, sp, amount
350     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
351   else { // Expand immediate that doesn't fit in 16-bit.
352     unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
353     BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
354   }
355 }
356 
357 /// This function generates the sequence of instructions needed to get the
358 /// result of adding register REG and immediate IMM.
359 unsigned
360 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
361                                MachineBasicBlock::iterator II, DebugLoc DL,
362                                unsigned *NewImm) const {
363   MipsAnalyzeImmediate AnalyzeImm;
364   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
365   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
366   unsigned Size = STI.isABI_N64() ? 64 : 32;
367   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
368   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
369   const TargetRegisterClass *RC = STI.isABI_N64() ?
370     &Mips::GPR64RegClass : &Mips::GPR32RegClass;
371   bool LastInstrIsADDiu = NewImm;
372 
373   const MipsAnalyzeImmediate::InstSeq &Seq =
374     AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
375   MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
376 
377   assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
378 
379   // The first instruction can be a LUi, which is different from other
380   // instructions (ADDiu, ORI and SLL) in that it does not have a register
381   // operand.
382   unsigned Reg = RegInfo.createVirtualRegister(RC);
383 
384   if (Inst->Opc == LUi)
385     BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
386   else
387     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
388       .addImm(SignExtend64<16>(Inst->ImmOpnd));
389 
390   // Build the remaining instructions in Seq.
391   for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
392     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
393       .addImm(SignExtend64<16>(Inst->ImmOpnd));
394 
395   if (LastInstrIsADDiu)
396     *NewImm = Inst->ImmOpnd;
397 
398   return Reg;
399 }
400 
401 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
402   return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
403           Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
404           Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
405           Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
406           Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
407           Opc == Mips::J) ?
408          Opc : 0;
409 }
410 
411 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
412                                 MachineBasicBlock::iterator I,
413                                 unsigned Opc) const {
414   BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
415 }
416 
417 std::pair<bool, bool>
418 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
419                                  const MachineFunction &MF) const {
420   const MCInstrDesc &Desc = get(Opc);
421   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
422   const MipsRegisterInfo *RI = &getRegisterInfo();
423   unsigned DstRegSize = getRegClass(Desc, 0, RI, MF)->getSize();
424   unsigned SrcRegSize = getRegClass(Desc, 1, RI, MF)->getSize();
425 
426   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
427 }
428 
429 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
430                                          MachineBasicBlock::iterator I,
431                                          unsigned NewOpc) const {
432   BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
433 }
434 
435 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
436                                      MachineBasicBlock::iterator I,
437                                      unsigned CvtOpc, unsigned MovOpc,
438                                      bool IsI64) const {
439   const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
440   const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
441   unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
442   unsigned KillSrc =  getKillRegState(Src.isKill());
443   DebugLoc DL = I->getDebugLoc();
444   bool DstIsLarger, SrcIsLarger;
445 
446   tie(DstIsLarger, SrcIsLarger) = compareOpndSize(CvtOpc, *MBB.getParent());
447 
448   if (DstIsLarger)
449     TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
450 
451   if (SrcIsLarger)
452     DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
453 
454   BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
455   BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
456 }
457 
458 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
459                                               MachineBasicBlock::iterator I,
460                                               bool FP64) const {
461   unsigned DstReg = I->getOperand(0).getReg();
462   unsigned SrcReg = I->getOperand(1).getReg();
463   unsigned N = I->getOperand(2).getImm();
464   DebugLoc dl = I->getDebugLoc();
465 
466   assert(N < 2 && "Invalid immediate");
467   unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
468   unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
469 
470   if (SubIdx == Mips::sub_hi && FP64)
471     BuildMI(MBB, I, dl, get(Mips::MFHC1), DstReg).addReg(SubReg);
472   else
473     BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
474 }
475 
476 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
477                                          MachineBasicBlock::iterator I,
478                                          bool FP64) const {
479   unsigned DstReg = I->getOperand(0).getReg();
480   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
481   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
482   DebugLoc dl = I->getDebugLoc();
483   const TargetRegisterInfo &TRI = getRegisterInfo();
484 
485   // mtc1 Lo, $fp
486   // mtc1 Hi, $fp + 1
487   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
488     .addReg(LoReg);
489 
490   if (FP64)
491     BuildMI(MBB, I, dl, get(Mips::MTHC1), TRI.getSubReg(DstReg, Mips::sub_hi))
492       .addReg(HiReg);
493   else
494     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
495       .addReg(HiReg);
496 }
497 
498 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
499                                      MachineBasicBlock::iterator I) const {
500   // This pseudo instruction is generated as part of the lowering of
501   // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
502   // indirect jump to TargetReg
503   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
504   unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
505   unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
506   unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
507   unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
508   unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
509   unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
510   unsigned OffsetReg = I->getOperand(0).getReg();
511   unsigned TargetReg = I->getOperand(1).getReg();
512 
513   // addu $ra, $v0, $zero
514   // addu $sp, $sp, $v1
515   // jr   $ra
516   if (TM.getRelocationModel() == Reloc::PIC_)
517     BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), T9)
518         .addReg(TargetReg).addReg(ZERO);
519   BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), RA)
520       .addReg(TargetReg).addReg(ZERO);
521   BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
522       .addReg(SP).addReg(OffsetReg);
523   BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
524 }
525 
526 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
527   return new MipsSEInstrInfo(TM);
528 }
529