1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSEInstrInfo.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MipsAnalyzeImmediate.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 using namespace llvm; 27 28 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) 29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), 30 RI() {} 31 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34 } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 42 int &FrameIndex) const { 43 unsigned Opc = MI.getOpcode(); 44 45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 47 if ((MI.getOperand(1).isFI()) && // is a stack slot 48 (MI.getOperand(2).isImm()) && // the imm is zero 49 (isZeroImm(MI.getOperand(2)))) { 50 FrameIndex = MI.getOperand(1).getIndex(); 51 return MI.getOperand(0).getReg(); 52 } 53 } 54 55 return 0; 56 } 57 58 /// isStoreToStackSlot - If the specified machine instruction is a direct 59 /// store to a stack slot, return the virtual or physical register number of 60 /// the source reg along with the FrameIndex of the loaded stack slot. If 61 /// not, return 0. This predicate must return 0 if the instruction has 62 /// any side effects other than storing to the stack slot. 63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 64 int &FrameIndex) const { 65 unsigned Opc = MI.getOpcode(); 66 67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { 69 if ((MI.getOperand(1).isFI()) && // is a stack slot 70 (MI.getOperand(2).isImm()) && // the imm is zero 71 (isZeroImm(MI.getOperand(2)))) { 72 FrameIndex = MI.getOperand(1).getIndex(); 73 return MI.getOperand(0).getReg(); 74 } 75 } 76 return 0; 77 } 78 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator I, 81 const DebugLoc &DL, unsigned DestReg, 82 unsigned SrcReg, bool KillSrc) const { 83 unsigned Opc = 0, ZeroReg = 0; 84 bool isMicroMips = Subtarget.inMicroMipsMode(); 85 86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 87 if (Mips::GPR32RegClass.contains(SrcReg)) { 88 if (isMicroMips) 89 Opc = Mips::MOVE16_MM; 90 else 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 92 } else if (Mips::CCRRegClass.contains(SrcReg)) 93 Opc = Mips::CFC1; 94 else if (Mips::FGR32RegClass.contains(SrcReg)) 95 Opc = Mips::MFC1; 96 else if (Mips::HI32RegClass.contains(SrcReg)) { 97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 98 SrcReg = 0; 99 } else if (Mips::LO32RegClass.contains(SrcReg)) { 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 101 SrcReg = 0; 102 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) 103 Opc = Mips::MFHI_DSP; 104 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 105 Opc = Mips::MFLO_DSP; 106 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 109 return; 110 } 111 else if (Mips::MSACtrlRegClass.contains(SrcReg)) 112 Opc = Mips::CFCMSA; 113 } 114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 115 if (Mips::CCRRegClass.contains(DestReg)) 116 Opc = Mips::CTC1; 117 else if (Mips::FGR32RegClass.contains(DestReg)) 118 Opc = Mips::MTC1; 119 else if (Mips::HI32RegClass.contains(DestReg)) 120 Opc = Mips::MTHI, DestReg = 0; 121 else if (Mips::LO32RegClass.contains(DestReg)) 122 Opc = Mips::MTLO, DestReg = 0; 123 else if (Mips::HI32DSPRegClass.contains(DestReg)) 124 Opc = Mips::MTHI_DSP; 125 else if (Mips::LO32DSPRegClass.contains(DestReg)) 126 Opc = Mips::MTLO_DSP; 127 else if (Mips::DSPCCRegClass.contains(DestReg)) { 128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 130 .addReg(DestReg, RegState::ImplicitDefine); 131 return; 132 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { 133 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) 134 .addReg(DestReg) 135 .addReg(SrcReg, getKillRegState(KillSrc)); 136 return; 137 } 138 } 139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 140 Opc = Mips::FMOV_S; 141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 142 Opc = Mips::FMOV_D32; 143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 144 Opc = Mips::FMOV_D64; 145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 146 if (Mips::GPR64RegClass.contains(SrcReg)) 147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 148 else if (Mips::HI64RegClass.contains(SrcReg)) 149 Opc = Mips::MFHI64, SrcReg = 0; 150 else if (Mips::LO64RegClass.contains(SrcReg)) 151 Opc = Mips::MFLO64, SrcReg = 0; 152 else if (Mips::FGR64RegClass.contains(SrcReg)) 153 Opc = Mips::DMFC1; 154 } 155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 156 if (Mips::HI64RegClass.contains(DestReg)) 157 Opc = Mips::MTHI64, DestReg = 0; 158 else if (Mips::LO64RegClass.contains(DestReg)) 159 Opc = Mips::MTLO64, DestReg = 0; 160 else if (Mips::FGR64RegClass.contains(DestReg)) 161 Opc = Mips::DMTC1; 162 } 163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 164 if (Mips::MSA128BRegClass.contains(SrcReg)) 165 Opc = Mips::MOVE_V; 166 } 167 168 assert(Opc && "Cannot copy registers"); 169 170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 171 172 if (DestReg) 173 MIB.addReg(DestReg, RegState::Define); 174 175 if (SrcReg) 176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 177 178 if (ZeroReg) 179 MIB.addReg(ZeroReg); 180 } 181 182 static bool isORCopyInst(const MachineInstr &MI) { 183 switch (MI.getOpcode()) { 184 default: 185 break; 186 case Mips::OR_MM: 187 case Mips::OR: 188 if (MI.getOperand(2).getReg() == Mips::ZERO) 189 return true; 190 break; 191 case Mips::OR64: 192 if (MI.getOperand(2).getReg() == Mips::ZERO_64) 193 return true; 194 break; 195 } 196 return false; 197 } 198 199 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true 200 /// if it is WRDSP instruction. 201 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) { 202 switch (MI.getOpcode()) { 203 default: 204 return false; 205 case Mips::WRDSP: 206 case Mips::WRDSP_MM: 207 isWrite = true; 208 break; 209 case Mips::RDDSP: 210 case Mips::RDDSP_MM: 211 isWrite = false; 212 break; 213 } 214 return true; 215 } 216 217 /// We check for the common case of 'or', as it's MIPS' preferred instruction 218 /// for GPRs but we have to check the operands to ensure that is the case. 219 /// Other move instructions for MIPS are directly identifiable. 220 bool MipsSEInstrInfo::isCopyInstr(const MachineInstr &MI, 221 const MachineOperand *&Src, 222 const MachineOperand *&Dest) const { 223 bool isDSPControlWrite = false; 224 // Condition is made to match the creation of WRDSP/RDDSP copy instruction 225 // from copyPhysReg function. 226 if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) { 227 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4)) 228 return false; 229 else if (isDSPControlWrite) { 230 Src = &MI.getOperand(0); 231 Dest = &MI.getOperand(2); 232 } else { 233 Dest = &MI.getOperand(0); 234 Src = &MI.getOperand(2); 235 } 236 return true; 237 } else if (MI.isMoveReg() || isORCopyInst(MI)) { 238 Dest = &MI.getOperand(0); 239 Src = &MI.getOperand(1); 240 return true; 241 } 242 return false; 243 } 244 245 void MipsSEInstrInfo:: 246 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 247 unsigned SrcReg, bool isKill, int FI, 248 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 249 int64_t Offset) const { 250 DebugLoc DL; 251 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 252 253 unsigned Opc = 0; 254 255 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 256 Opc = Mips::SW; 257 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 258 Opc = Mips::SD; 259 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 260 Opc = Mips::STORE_ACC64; 261 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 262 Opc = Mips::STORE_ACC64DSP; 263 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 264 Opc = Mips::STORE_ACC128; 265 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 266 Opc = Mips::STORE_CCOND_DSP; 267 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 268 Opc = Mips::SWC1; 269 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 270 Opc = Mips::SDC1; 271 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 272 Opc = Mips::SDC164; 273 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 274 Opc = Mips::ST_B; 275 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 276 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 277 Opc = Mips::ST_H; 278 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 279 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 280 Opc = Mips::ST_W; 281 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 282 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 283 Opc = Mips::ST_D; 284 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 285 Opc = Mips::SW; 286 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 287 Opc = Mips::SD; 288 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 289 Opc = Mips::SW; 290 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 291 Opc = Mips::SD; 292 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 293 Opc = Mips::SWDSP; 294 295 // Hi, Lo are normally caller save but they are callee save 296 // for interrupt handling. 297 const Function &Func = MBB.getParent()->getFunction(); 298 if (Func.hasFnAttribute("interrupt")) { 299 if (Mips::HI32RegClass.hasSubClassEq(RC)) { 300 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); 301 SrcReg = Mips::K0; 302 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { 303 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); 304 SrcReg = Mips::K0_64; 305 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { 306 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); 307 SrcReg = Mips::K0; 308 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { 309 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); 310 SrcReg = Mips::K0_64; 311 } 312 } 313 314 assert(Opc && "Register class not handled!"); 315 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 316 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 317 } 318 319 void MipsSEInstrInfo:: 320 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 321 unsigned DestReg, int FI, const TargetRegisterClass *RC, 322 const TargetRegisterInfo *TRI, int64_t Offset) const { 323 DebugLoc DL; 324 if (I != MBB.end()) DL = I->getDebugLoc(); 325 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 326 unsigned Opc = 0; 327 328 const Function &Func = MBB.getParent()->getFunction(); 329 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && 330 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || 331 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); 332 333 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 334 Opc = Mips::LW; 335 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 336 Opc = Mips::LD; 337 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 338 Opc = Mips::LOAD_ACC64; 339 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 340 Opc = Mips::LOAD_ACC64DSP; 341 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 342 Opc = Mips::LOAD_ACC128; 343 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 344 Opc = Mips::LOAD_CCOND_DSP; 345 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 346 Opc = Mips::LWC1; 347 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 348 Opc = Mips::LDC1; 349 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 350 Opc = Mips::LDC164; 351 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 352 Opc = Mips::LD_B; 353 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 354 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 355 Opc = Mips::LD_H; 356 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 357 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 358 Opc = Mips::LD_W; 359 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 360 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 361 Opc = Mips::LD_D; 362 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 363 Opc = Mips::LW; 364 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 365 Opc = Mips::LD; 366 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 367 Opc = Mips::LW; 368 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 369 Opc = Mips::LD; 370 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 371 Opc = Mips::LWDSP; 372 373 assert(Opc && "Register class not handled!"); 374 375 if (!ReqIndirectLoad) 376 BuildMI(MBB, I, DL, get(Opc), DestReg) 377 .addFrameIndex(FI) 378 .addImm(Offset) 379 .addMemOperand(MMO); 380 else { 381 // Load HI/LO through K0. Notably the DestReg is encoded into the 382 // instruction itself. 383 unsigned Reg = Mips::K0; 384 unsigned LdOp = Mips::MTLO; 385 if (DestReg == Mips::HI0) 386 LdOp = Mips::MTHI; 387 388 if (Subtarget.getABI().ArePtrs64bit()) { 389 Reg = Mips::K0_64; 390 if (DestReg == Mips::HI0_64) 391 LdOp = Mips::MTHI64; 392 else 393 LdOp = Mips::MTLO64; 394 } 395 396 BuildMI(MBB, I, DL, get(Opc), Reg) 397 .addFrameIndex(FI) 398 .addImm(Offset) 399 .addMemOperand(MMO); 400 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); 401 } 402 } 403 404 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 405 MachineBasicBlock &MBB = *MI.getParent(); 406 bool isMicroMips = Subtarget.inMicroMipsMode(); 407 unsigned Opc; 408 409 switch (MI.getDesc().getOpcode()) { 410 default: 411 return false; 412 case Mips::RetRA: 413 expandRetRA(MBB, MI); 414 break; 415 case Mips::ERet: 416 expandERet(MBB, MI); 417 break; 418 case Mips::PseudoMFHI: 419 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 420 expandPseudoMFHiLo(MBB, MI, Opc); 421 break; 422 case Mips::PseudoMFLO: 423 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 424 expandPseudoMFHiLo(MBB, MI, Opc); 425 break; 426 case Mips::PseudoMFHI64: 427 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); 428 break; 429 case Mips::PseudoMFLO64: 430 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); 431 break; 432 case Mips::PseudoMTLOHI: 433 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); 434 break; 435 case Mips::PseudoMTLOHI64: 436 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); 437 break; 438 case Mips::PseudoMTLOHI_DSP: 439 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); 440 break; 441 case Mips::PseudoCVT_S_W: 442 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); 443 break; 444 case Mips::PseudoCVT_D32_W: 445 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; 446 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); 447 break; 448 case Mips::PseudoCVT_S_L: 449 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); 450 break; 451 case Mips::PseudoCVT_D64_W: 452 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; 453 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); 454 break; 455 case Mips::PseudoCVT_D64_L: 456 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); 457 break; 458 case Mips::BuildPairF64: 459 expandBuildPairF64(MBB, MI, isMicroMips, false); 460 break; 461 case Mips::BuildPairF64_64: 462 expandBuildPairF64(MBB, MI, isMicroMips, true); 463 break; 464 case Mips::ExtractElementF64: 465 expandExtractElementF64(MBB, MI, isMicroMips, false); 466 break; 467 case Mips::ExtractElementF64_64: 468 expandExtractElementF64(MBB, MI, isMicroMips, true); 469 break; 470 case Mips::MIPSeh_return32: 471 case Mips::MIPSeh_return64: 472 expandEhReturn(MBB, MI); 473 break; 474 } 475 476 MBB.erase(MI); 477 return true; 478 } 479 480 /// getOppositeBranchOpc - Return the inverse of the specified 481 /// opcode, e.g. turning BEQ to BNE. 482 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { 483 switch (Opc) { 484 default: llvm_unreachable("Illegal opcode!"); 485 case Mips::BEQ: return Mips::BNE; 486 case Mips::BEQ_MM: return Mips::BNE_MM; 487 case Mips::BNE: return Mips::BEQ; 488 case Mips::BNE_MM: return Mips::BEQ_MM; 489 case Mips::BGTZ: return Mips::BLEZ; 490 case Mips::BGEZ: return Mips::BLTZ; 491 case Mips::BLTZ: return Mips::BGEZ; 492 case Mips::BLEZ: return Mips::BGTZ; 493 case Mips::BGTZ_MM: return Mips::BLEZ_MM; 494 case Mips::BGEZ_MM: return Mips::BLTZ_MM; 495 case Mips::BLTZ_MM: return Mips::BGEZ_MM; 496 case Mips::BLEZ_MM: return Mips::BGTZ_MM; 497 case Mips::BEQ64: return Mips::BNE64; 498 case Mips::BNE64: return Mips::BEQ64; 499 case Mips::BGTZ64: return Mips::BLEZ64; 500 case Mips::BGEZ64: return Mips::BLTZ64; 501 case Mips::BLTZ64: return Mips::BGEZ64; 502 case Mips::BLEZ64: return Mips::BGTZ64; 503 case Mips::BC1T: return Mips::BC1F; 504 case Mips::BC1F: return Mips::BC1T; 505 case Mips::BC1T_MM: return Mips::BC1F_MM; 506 case Mips::BC1F_MM: return Mips::BC1T_MM; 507 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM; 508 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM; 509 case Mips::BEQZC_MM: return Mips::BNEZC_MM; 510 case Mips::BNEZC_MM: return Mips::BEQZC_MM; 511 case Mips::BEQZC: return Mips::BNEZC; 512 case Mips::BNEZC: return Mips::BEQZC; 513 case Mips::BLEZC: return Mips::BGTZC; 514 case Mips::BGEZC: return Mips::BLTZC; 515 case Mips::BGEC: return Mips::BLTC; 516 case Mips::BGTZC: return Mips::BLEZC; 517 case Mips::BLTZC: return Mips::BGEZC; 518 case Mips::BLTC: return Mips::BGEC; 519 case Mips::BGEUC: return Mips::BLTUC; 520 case Mips::BLTUC: return Mips::BGEUC; 521 case Mips::BEQC: return Mips::BNEC; 522 case Mips::BNEC: return Mips::BEQC; 523 case Mips::BC1EQZ: return Mips::BC1NEZ; 524 case Mips::BC1NEZ: return Mips::BC1EQZ; 525 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; 526 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; 527 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; 528 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; 529 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6; 530 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; 531 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; 532 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6; 533 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6; 534 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6; 535 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; 536 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; 537 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6; 538 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6; 539 case Mips::BEQZC64: return Mips::BNEZC64; 540 case Mips::BNEZC64: return Mips::BEQZC64; 541 case Mips::BEQC64: return Mips::BNEC64; 542 case Mips::BNEC64: return Mips::BEQC64; 543 case Mips::BGEC64: return Mips::BLTC64; 544 case Mips::BGEUC64: return Mips::BLTUC64; 545 case Mips::BLTC64: return Mips::BGEC64; 546 case Mips::BLTUC64: return Mips::BGEUC64; 547 case Mips::BGTZC64: return Mips::BLEZC64; 548 case Mips::BGEZC64: return Mips::BLTZC64; 549 case Mips::BLTZC64: return Mips::BGEZC64; 550 case Mips::BLEZC64: return Mips::BGTZC64; 551 case Mips::BBIT0: return Mips::BBIT1; 552 case Mips::BBIT1: return Mips::BBIT0; 553 case Mips::BBIT032: return Mips::BBIT132; 554 case Mips::BBIT132: return Mips::BBIT032; 555 case Mips::BZ_B: return Mips::BNZ_B; 556 case Mips::BZ_H: return Mips::BNZ_H; 557 case Mips::BZ_W: return Mips::BNZ_W; 558 case Mips::BZ_D: return Mips::BNZ_D; 559 case Mips::BZ_V: return Mips::BNZ_V; 560 case Mips::BNZ_B: return Mips::BZ_B; 561 case Mips::BNZ_H: return Mips::BZ_H; 562 case Mips::BNZ_W: return Mips::BZ_W; 563 case Mips::BNZ_D: return Mips::BZ_D; 564 case Mips::BNZ_V: return Mips::BZ_V; 565 } 566 } 567 568 /// Adjust SP by Amount bytes. 569 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 570 MachineBasicBlock &MBB, 571 MachineBasicBlock::iterator I) const { 572 MipsABIInfo ABI = Subtarget.getABI(); 573 DebugLoc DL; 574 unsigned ADDiu = ABI.GetPtrAddiuOp(); 575 576 if (Amount == 0) 577 return; 578 579 if (isInt<16>(Amount)) { 580 // addi sp, sp, amount 581 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 582 } else { 583 // For numbers which are not 16bit integers we synthesize Amount inline 584 // then add or subtract it from sp. 585 unsigned Opc = ABI.GetPtrAdduOp(); 586 if (Amount < 0) { 587 Opc = ABI.GetPtrSubuOp(); 588 Amount = -Amount; 589 } 590 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); 591 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 592 } 593 } 594 595 /// This function generates the sequence of instructions needed to get the 596 /// result of adding register REG and immediate IMM. 597 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 598 MachineBasicBlock::iterator II, 599 const DebugLoc &DL, 600 unsigned *NewImm) const { 601 MipsAnalyzeImmediate AnalyzeImm; 602 const MipsSubtarget &STI = Subtarget; 603 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 604 unsigned Size = STI.isABI_N64() ? 64 : 32; 605 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 606 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 607 const TargetRegisterClass *RC = STI.isABI_N64() ? 608 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 609 bool LastInstrIsADDiu = NewImm; 610 611 const MipsAnalyzeImmediate::InstSeq &Seq = 612 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 613 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 614 615 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 616 617 // The first instruction can be a LUi, which is different from other 618 // instructions (ADDiu, ORI and SLL) in that it does not have a register 619 // operand. 620 unsigned Reg = RegInfo.createVirtualRegister(RC); 621 622 if (Inst->Opc == LUi) 623 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 624 else 625 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 626 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 627 628 // Build the remaining instructions in Seq. 629 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 630 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 631 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 632 633 if (LastInstrIsADDiu) 634 *NewImm = Inst->ImmOpnd; 635 636 return Reg; 637 } 638 639 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 640 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || 641 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || 642 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || 643 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || 644 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || 645 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || 646 Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || 647 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || 648 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || 649 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || 650 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || 651 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || 652 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || 653 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || 654 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || 655 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || 656 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || 657 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || 658 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || 659 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || 660 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || 661 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || 662 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || 663 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; 664 } 665 666 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, 667 MachineBasicBlock::iterator I) const { 668 669 MachineInstrBuilder MIB; 670 if (Subtarget.isGP64bit()) 671 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) 672 .addReg(Mips::RA_64, RegState::Undef); 673 else 674 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)) 675 .addReg(Mips::RA, RegState::Undef); 676 677 // Retain any imp-use flags. 678 for (auto & MO : I->operands()) { 679 if (MO.isImplicit()) 680 MIB.add(MO); 681 } 682 } 683 684 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB, 685 MachineBasicBlock::iterator I) const { 686 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); 687 } 688 689 std::pair<bool, bool> 690 MipsSEInstrInfo::compareOpndSize(unsigned Opc, 691 const MachineFunction &MF) const { 692 const MCInstrDesc &Desc = get(Opc); 693 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 694 const MipsRegisterInfo *RI = &getRegisterInfo(); 695 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); 696 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); 697 698 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize); 699 } 700 701 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB, 702 MachineBasicBlock::iterator I, 703 unsigned NewOpc) const { 704 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg()); 705 } 706 707 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB, 708 MachineBasicBlock::iterator I, 709 unsigned LoOpc, 710 unsigned HiOpc, 711 bool HasExplicitDef) const { 712 // Expand 713 // lo_hi pseudomtlohi $gpr0, $gpr1 714 // to these two instructions: 715 // mtlo $gpr0 716 // mthi $gpr1 717 718 DebugLoc DL = I->getDebugLoc(); 719 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); 720 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); 721 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); 722 723 // Add lo/hi registers if the mtlo/hi instructions created have explicit 724 // def registers. 725 if (HasExplicitDef) { 726 unsigned DstReg = I->getOperand(0).getReg(); 727 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 728 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 729 LoInst.addReg(DstLo, RegState::Define); 730 HiInst.addReg(DstHi, RegState::Define); 731 } 732 733 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); 734 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); 735 } 736 737 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, 738 MachineBasicBlock::iterator I, 739 unsigned CvtOpc, unsigned MovOpc, 740 bool IsI64) const { 741 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); 742 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 743 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 744 unsigned KillSrc = getKillRegState(Src.isKill()); 745 DebugLoc DL = I->getDebugLoc(); 746 bool DstIsLarger, SrcIsLarger; 747 748 std::tie(DstIsLarger, SrcIsLarger) = 749 compareOpndSize(CvtOpc, *MBB.getParent()); 750 751 if (DstIsLarger) 752 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 753 754 if (SrcIsLarger) 755 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 756 757 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); 758 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 759 } 760 761 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, 762 MachineBasicBlock::iterator I, 763 bool isMicroMips, 764 bool FP64) const { 765 unsigned DstReg = I->getOperand(0).getReg(); 766 unsigned SrcReg = I->getOperand(1).getReg(); 767 unsigned N = I->getOperand(2).getImm(); 768 DebugLoc dl = I->getDebugLoc(); 769 770 assert(N < 2 && "Invalid immediate"); 771 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; 772 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 773 774 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 775 // in MipsSEFrameLowering.cpp. 776 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 777 778 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 779 // in MipsSEFrameLowering.cpp. 780 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 781 782 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { 783 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we 784 // claim to read the whole 64-bits as part of a white lie used to 785 // temporarily work around a widespread bug in the -mfp64 support. 786 // The problem is that none of the 32-bit fpu ops mention the fact 787 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 788 // requires a major overhaul of the FPU implementation which can't 789 // be done right now due to time constraints. 790 // MFHC1 is one of two instructions that are affected since they are 791 // the only instructions that don't read the lower 32-bits. 792 // We therefore pretend that it reads the bottom 32-bits to 793 // artificially create a dependency and prevent the scheduler 794 // changing the behaviour of the code. 795 BuildMI(MBB, I, dl, 796 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) 797 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), 798 DstReg) 799 .addReg(SrcReg); 800 } else 801 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); 802 } 803 804 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, 805 MachineBasicBlock::iterator I, 806 bool isMicroMips, bool FP64) const { 807 unsigned DstReg = I->getOperand(0).getReg(); 808 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 809 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 810 DebugLoc dl = I->getDebugLoc(); 811 const TargetRegisterInfo &TRI = getRegisterInfo(); 812 813 // When mthc1 is available, use: 814 // mtc1 Lo, $fp 815 // mthc1 Hi, $fp 816 // 817 // Otherwise, for O32 FPXX ABI: 818 // spill + reload via ldc1 819 // This case is handled by the frame lowering code. 820 // 821 // Otherwise, for FP32: 822 // mtc1 Lo, $fp 823 // mtc1 Hi, $fp + 1 824 // 825 // The case where dmtc1 is available doesn't need to be handled here 826 // because it never creates a BuildPairF64 node. 827 828 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 829 // in MipsSEFrameLowering.cpp. 830 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 831 832 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 833 // in MipsSEFrameLowering.cpp. 834 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 835 836 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 837 .addReg(LoReg); 838 839 if (Subtarget.hasMTHC1()) { 840 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work 841 // around a widespread bug in the -mfp64 support. 842 // The problem is that none of the 32-bit fpu ops mention the fact 843 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 844 // requires a major overhaul of the FPU implementation which can't 845 // be done right now due to time constraints. 846 // MTHC1 is one of two instructions that are affected since they are 847 // the only instructions that don't read the lower 32-bits. 848 // We therefore pretend that it reads the bottom 32-bits to 849 // artificially create a dependency and prevent the scheduler 850 // changing the behaviour of the code. 851 BuildMI(MBB, I, dl, 852 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) 853 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), 854 DstReg) 855 .addReg(DstReg) 856 .addReg(HiReg); 857 } else if (Subtarget.isABI_FPXX()) 858 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); 859 else 860 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) 861 .addReg(HiReg); 862 } 863 864 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, 865 MachineBasicBlock::iterator I) const { 866 // This pseudo instruction is generated as part of the lowering of 867 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 868 // indirect jump to TargetReg 869 MipsABIInfo ABI = Subtarget.getABI(); 870 unsigned ADDU = ABI.GetPtrAdduOp(); 871 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; 872 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; 873 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; 874 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 875 unsigned OffsetReg = I->getOperand(0).getReg(); 876 unsigned TargetReg = I->getOperand(1).getReg(); 877 878 // addu $ra, $v0, $zero 879 // addu $sp, $sp, $v1 880 // jr $ra (via RetRA) 881 const TargetMachine &TM = MBB.getParent()->getTarget(); 882 if (TM.isPositionIndependent()) 883 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) 884 .addReg(TargetReg) 885 .addReg(ZERO); 886 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA) 887 .addReg(TargetReg) 888 .addReg(ZERO); 889 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); 890 expandRetRA(MBB, I); 891 } 892 893 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { 894 return new MipsSEInstrInfo(STI); 895 } 896