1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 11 // 12 //===----------------------------------------------------------------------===// 13 14 #include "MipsSEInstrInfo.h" 15 #include "InstPrinter/MipsInstPrinter.h" 16 #include "MipsAnalyzeImmediate.h" 17 #include "MipsMachineFunction.h" 18 #include "MipsTargetMachine.h" 19 #include "llvm/ADT/STLExtras.h" 20 #include "llvm/CodeGen/MachineInstrBuilder.h" 21 #include "llvm/CodeGen/MachineRegisterInfo.h" 22 #include "llvm/Support/ErrorHandling.h" 23 #include "llvm/Support/MathExtras.h" 24 #include "llvm/Support/TargetRegistry.h" 25 26 using namespace llvm; 27 28 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) 29 : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J), 30 RI() {} 31 32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 33 return RI; 34 } 35 36 /// isLoadFromStackSlot - If the specified machine instruction is a direct 37 /// load from a stack slot, return the virtual or physical register number of 38 /// the destination along with the FrameIndex of the loaded stack slot. If 39 /// not, return 0. This predicate must return 0 if the instruction has 40 /// any side effects other than loading from the stack slot. 41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 42 int &FrameIndex) const { 43 unsigned Opc = MI.getOpcode(); 44 45 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 46 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 47 if ((MI.getOperand(1).isFI()) && // is a stack slot 48 (MI.getOperand(2).isImm()) && // the imm is zero 49 (isZeroImm(MI.getOperand(2)))) { 50 FrameIndex = MI.getOperand(1).getIndex(); 51 return MI.getOperand(0).getReg(); 52 } 53 } 54 55 return 0; 56 } 57 58 /// isStoreToStackSlot - If the specified machine instruction is a direct 59 /// store to a stack slot, return the virtual or physical register number of 60 /// the source reg along with the FrameIndex of the loaded stack slot. If 61 /// not, return 0. This predicate must return 0 if the instruction has 62 /// any side effects other than storing to the stack slot. 63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 64 int &FrameIndex) const { 65 unsigned Opc = MI.getOpcode(); 66 67 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 68 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { 69 if ((MI.getOperand(1).isFI()) && // is a stack slot 70 (MI.getOperand(2).isImm()) && // the imm is zero 71 (isZeroImm(MI.getOperand(2)))) { 72 FrameIndex = MI.getOperand(1).getIndex(); 73 return MI.getOperand(0).getReg(); 74 } 75 } 76 return 0; 77 } 78 79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 80 MachineBasicBlock::iterator I, 81 const DebugLoc &DL, unsigned DestReg, 82 unsigned SrcReg, bool KillSrc) const { 83 unsigned Opc = 0, ZeroReg = 0; 84 bool isMicroMips = Subtarget.inMicroMipsMode(); 85 86 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 87 if (Mips::GPR32RegClass.contains(SrcReg)) { 88 if (isMicroMips) 89 Opc = Mips::MOVE16_MM; 90 else 91 Opc = Mips::OR, ZeroReg = Mips::ZERO; 92 } else if (Mips::CCRRegClass.contains(SrcReg)) 93 Opc = Mips::CFC1; 94 else if (Mips::FGR32RegClass.contains(SrcReg)) 95 Opc = Mips::MFC1; 96 else if (Mips::HI32RegClass.contains(SrcReg)) { 97 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 98 SrcReg = 0; 99 } else if (Mips::LO32RegClass.contains(SrcReg)) { 100 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 101 SrcReg = 0; 102 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) 103 Opc = Mips::MFHI_DSP; 104 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 105 Opc = Mips::MFLO_DSP; 106 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 107 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 108 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 109 return; 110 } 111 else if (Mips::MSACtrlRegClass.contains(SrcReg)) 112 Opc = Mips::CFCMSA; 113 } 114 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 115 if (Mips::CCRRegClass.contains(DestReg)) 116 Opc = Mips::CTC1; 117 else if (Mips::FGR32RegClass.contains(DestReg)) 118 Opc = Mips::MTC1; 119 else if (Mips::HI32RegClass.contains(DestReg)) 120 Opc = Mips::MTHI, DestReg = 0; 121 else if (Mips::LO32RegClass.contains(DestReg)) 122 Opc = Mips::MTLO, DestReg = 0; 123 else if (Mips::HI32DSPRegClass.contains(DestReg)) 124 Opc = Mips::MTHI_DSP; 125 else if (Mips::LO32DSPRegClass.contains(DestReg)) 126 Opc = Mips::MTLO_DSP; 127 else if (Mips::DSPCCRegClass.contains(DestReg)) { 128 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 129 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 130 .addReg(DestReg, RegState::ImplicitDefine); 131 return; 132 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { 133 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) 134 .addReg(DestReg) 135 .addReg(SrcReg, getKillRegState(KillSrc)); 136 return; 137 } 138 } 139 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 140 Opc = Mips::FMOV_S; 141 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 142 Opc = Mips::FMOV_D32; 143 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 144 Opc = Mips::FMOV_D64; 145 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 146 if (Mips::GPR64RegClass.contains(SrcReg)) 147 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 148 else if (Mips::HI64RegClass.contains(SrcReg)) 149 Opc = Mips::MFHI64, SrcReg = 0; 150 else if (Mips::LO64RegClass.contains(SrcReg)) 151 Opc = Mips::MFLO64, SrcReg = 0; 152 else if (Mips::FGR64RegClass.contains(SrcReg)) 153 Opc = Mips::DMFC1; 154 } 155 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 156 if (Mips::HI64RegClass.contains(DestReg)) 157 Opc = Mips::MTHI64, DestReg = 0; 158 else if (Mips::LO64RegClass.contains(DestReg)) 159 Opc = Mips::MTLO64, DestReg = 0; 160 else if (Mips::FGR64RegClass.contains(DestReg)) 161 Opc = Mips::DMTC1; 162 } 163 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 164 if (Mips::MSA128BRegClass.contains(SrcReg)) 165 Opc = Mips::MOVE_V; 166 } 167 168 assert(Opc && "Cannot copy registers"); 169 170 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 171 172 if (DestReg) 173 MIB.addReg(DestReg, RegState::Define); 174 175 if (SrcReg) 176 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 177 178 if (ZeroReg) 179 MIB.addReg(ZeroReg); 180 } 181 182 static bool isORCopyInst(const MachineInstr &MI) { 183 switch (MI.getOpcode()) { 184 case Mips::OR_MM: 185 case Mips::OR: 186 if (MI.getOperand(2).getReg() == Mips::ZERO) 187 return true; 188 case Mips::OR64: 189 if (MI.getOperand(2).getReg() == Mips::ZERO_64) 190 return true; 191 default: 192 return false; 193 } 194 } 195 196 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true 197 /// if it is WRDSP instruction. 198 static bool isReadOrWritToDSPReg(const MachineInstr &MI, bool &isWrite) { 199 switch (MI.getOpcode()) { 200 case Mips::WRDSP: 201 case Mips::WRDSP_MM: 202 isWrite = true; 203 case Mips::RDDSP: 204 case Mips::RDDSP_MM: 205 return true; 206 default: 207 return false; 208 } 209 } 210 211 /// We check for the common case of 'or', as it's MIPS' preferred instruction 212 /// for GPRs but we have to check the operands to ensure that is the case. 213 /// Other move instructions for MIPS are directly identifiable. 214 bool MipsSEInstrInfo::isCopyInstr(const MachineInstr &MI, MachineOperand &Src, 215 MachineOperand &Dest) const { 216 bool isDSPControlWrite = false; 217 // Condition is made to match the creation of WRDSP/RDDSP copy instruction 218 // from copyPhysReg function. 219 if (isReadOrWritToDSPReg(MI, isDSPControlWrite)) { 220 if (!MI.getOperand(1).isImm() || !(MI.getOperand(1).getImm() == (1<<4))) 221 return false; 222 else if (isDSPControlWrite) { 223 Src = MI.getOperand(0); 224 Dest = MI.getOperand(2); 225 } else { 226 Dest = MI.getOperand(0); 227 Src = MI.getOperand(2); 228 } 229 return true; 230 } else if (MI.isMoveReg() || isORCopyInst(MI)) { 231 Dest = MI.getOperand(0); 232 Src = MI.getOperand(1); 233 return true; 234 } 235 return false; 236 } 237 238 void MipsSEInstrInfo:: 239 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 240 unsigned SrcReg, bool isKill, int FI, 241 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 242 int64_t Offset) const { 243 DebugLoc DL; 244 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 245 246 unsigned Opc = 0; 247 248 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 249 Opc = Mips::SW; 250 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 251 Opc = Mips::SD; 252 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 253 Opc = Mips::STORE_ACC64; 254 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 255 Opc = Mips::STORE_ACC64DSP; 256 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 257 Opc = Mips::STORE_ACC128; 258 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 259 Opc = Mips::STORE_CCOND_DSP; 260 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 261 Opc = Mips::SWC1; 262 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 263 Opc = Mips::SDC1; 264 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 265 Opc = Mips::SDC164; 266 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 267 Opc = Mips::ST_B; 268 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 269 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 270 Opc = Mips::ST_H; 271 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 272 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 273 Opc = Mips::ST_W; 274 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 275 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 276 Opc = Mips::ST_D; 277 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 278 Opc = Mips::SW; 279 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 280 Opc = Mips::SD; 281 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 282 Opc = Mips::SW; 283 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 284 Opc = Mips::SD; 285 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 286 Opc = Mips::SWDSP; 287 288 // Hi, Lo are normally caller save but they are callee save 289 // for interrupt handling. 290 const Function &Func = MBB.getParent()->getFunction(); 291 if (Func.hasFnAttribute("interrupt")) { 292 if (Mips::HI32RegClass.hasSubClassEq(RC)) { 293 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); 294 SrcReg = Mips::K0; 295 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { 296 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); 297 SrcReg = Mips::K0_64; 298 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { 299 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); 300 SrcReg = Mips::K0; 301 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { 302 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); 303 SrcReg = Mips::K0_64; 304 } 305 } 306 307 assert(Opc && "Register class not handled!"); 308 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 309 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 310 } 311 312 void MipsSEInstrInfo:: 313 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 314 unsigned DestReg, int FI, const TargetRegisterClass *RC, 315 const TargetRegisterInfo *TRI, int64_t Offset) const { 316 DebugLoc DL; 317 if (I != MBB.end()) DL = I->getDebugLoc(); 318 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 319 unsigned Opc = 0; 320 321 const Function &Func = MBB.getParent()->getFunction(); 322 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && 323 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || 324 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); 325 326 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 327 Opc = Mips::LW; 328 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 329 Opc = Mips::LD; 330 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 331 Opc = Mips::LOAD_ACC64; 332 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 333 Opc = Mips::LOAD_ACC64DSP; 334 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 335 Opc = Mips::LOAD_ACC128; 336 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 337 Opc = Mips::LOAD_CCOND_DSP; 338 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 339 Opc = Mips::LWC1; 340 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 341 Opc = Mips::LDC1; 342 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 343 Opc = Mips::LDC164; 344 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 345 Opc = Mips::LD_B; 346 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 347 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 348 Opc = Mips::LD_H; 349 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 350 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 351 Opc = Mips::LD_W; 352 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 353 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 354 Opc = Mips::LD_D; 355 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 356 Opc = Mips::LW; 357 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 358 Opc = Mips::LD; 359 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 360 Opc = Mips::LW; 361 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 362 Opc = Mips::LD; 363 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 364 Opc = Mips::LWDSP; 365 366 assert(Opc && "Register class not handled!"); 367 368 if (!ReqIndirectLoad) 369 BuildMI(MBB, I, DL, get(Opc), DestReg) 370 .addFrameIndex(FI) 371 .addImm(Offset) 372 .addMemOperand(MMO); 373 else { 374 // Load HI/LO through K0. Notably the DestReg is encoded into the 375 // instruction itself. 376 unsigned Reg = Mips::K0; 377 unsigned LdOp = Mips::MTLO; 378 if (DestReg == Mips::HI0) 379 LdOp = Mips::MTHI; 380 381 if (Subtarget.getABI().ArePtrs64bit()) { 382 Reg = Mips::K0_64; 383 if (DestReg == Mips::HI0_64) 384 LdOp = Mips::MTHI64; 385 else 386 LdOp = Mips::MTLO64; 387 } 388 389 BuildMI(MBB, I, DL, get(Opc), Reg) 390 .addFrameIndex(FI) 391 .addImm(Offset) 392 .addMemOperand(MMO); 393 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); 394 } 395 } 396 397 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 398 MachineBasicBlock &MBB = *MI.getParent(); 399 bool isMicroMips = Subtarget.inMicroMipsMode(); 400 unsigned Opc; 401 402 switch (MI.getDesc().getOpcode()) { 403 default: 404 return false; 405 case Mips::RetRA: 406 expandRetRA(MBB, MI); 407 break; 408 case Mips::ERet: 409 expandERet(MBB, MI); 410 break; 411 case Mips::PseudoMFHI: 412 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 413 expandPseudoMFHiLo(MBB, MI, Opc); 414 break; 415 case Mips::PseudoMFLO: 416 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 417 expandPseudoMFHiLo(MBB, MI, Opc); 418 break; 419 case Mips::PseudoMFHI64: 420 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); 421 break; 422 case Mips::PseudoMFLO64: 423 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); 424 break; 425 case Mips::PseudoMTLOHI: 426 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); 427 break; 428 case Mips::PseudoMTLOHI64: 429 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); 430 break; 431 case Mips::PseudoMTLOHI_DSP: 432 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); 433 break; 434 case Mips::PseudoCVT_S_W: 435 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); 436 break; 437 case Mips::PseudoCVT_D32_W: 438 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; 439 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); 440 break; 441 case Mips::PseudoCVT_S_L: 442 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); 443 break; 444 case Mips::PseudoCVT_D64_W: 445 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; 446 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); 447 break; 448 case Mips::PseudoCVT_D64_L: 449 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); 450 break; 451 case Mips::BuildPairF64: 452 expandBuildPairF64(MBB, MI, isMicroMips, false); 453 break; 454 case Mips::BuildPairF64_64: 455 expandBuildPairF64(MBB, MI, isMicroMips, true); 456 break; 457 case Mips::ExtractElementF64: 458 expandExtractElementF64(MBB, MI, isMicroMips, false); 459 break; 460 case Mips::ExtractElementF64_64: 461 expandExtractElementF64(MBB, MI, isMicroMips, true); 462 break; 463 case Mips::MIPSeh_return32: 464 case Mips::MIPSeh_return64: 465 expandEhReturn(MBB, MI); 466 break; 467 } 468 469 MBB.erase(MI); 470 return true; 471 } 472 473 /// getOppositeBranchOpc - Return the inverse of the specified 474 /// opcode, e.g. turning BEQ to BNE. 475 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { 476 switch (Opc) { 477 default: llvm_unreachable("Illegal opcode!"); 478 case Mips::BEQ: return Mips::BNE; 479 case Mips::BEQ_MM: return Mips::BNE_MM; 480 case Mips::BNE: return Mips::BEQ; 481 case Mips::BNE_MM: return Mips::BEQ_MM; 482 case Mips::BGTZ: return Mips::BLEZ; 483 case Mips::BGEZ: return Mips::BLTZ; 484 case Mips::BLTZ: return Mips::BGEZ; 485 case Mips::BLEZ: return Mips::BGTZ; 486 case Mips::BGTZ_MM: return Mips::BLEZ_MM; 487 case Mips::BGEZ_MM: return Mips::BLTZ_MM; 488 case Mips::BLTZ_MM: return Mips::BGEZ_MM; 489 case Mips::BLEZ_MM: return Mips::BGTZ_MM; 490 case Mips::BEQ64: return Mips::BNE64; 491 case Mips::BNE64: return Mips::BEQ64; 492 case Mips::BGTZ64: return Mips::BLEZ64; 493 case Mips::BGEZ64: return Mips::BLTZ64; 494 case Mips::BLTZ64: return Mips::BGEZ64; 495 case Mips::BLEZ64: return Mips::BGTZ64; 496 case Mips::BC1T: return Mips::BC1F; 497 case Mips::BC1F: return Mips::BC1T; 498 case Mips::BC1T_MM: return Mips::BC1F_MM; 499 case Mips::BC1F_MM: return Mips::BC1T_MM; 500 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM; 501 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM; 502 case Mips::BEQZC_MM: return Mips::BNEZC_MM; 503 case Mips::BNEZC_MM: return Mips::BEQZC_MM; 504 case Mips::BEQZC: return Mips::BNEZC; 505 case Mips::BNEZC: return Mips::BEQZC; 506 case Mips::BLEZC: return Mips::BGTZC; 507 case Mips::BGEZC: return Mips::BLTZC; 508 case Mips::BGEC: return Mips::BLTC; 509 case Mips::BGTZC: return Mips::BLEZC; 510 case Mips::BLTZC: return Mips::BGEZC; 511 case Mips::BLTC: return Mips::BGEC; 512 case Mips::BGEUC: return Mips::BLTUC; 513 case Mips::BLTUC: return Mips::BGEUC; 514 case Mips::BEQC: return Mips::BNEC; 515 case Mips::BNEC: return Mips::BEQC; 516 case Mips::BC1EQZ: return Mips::BC1NEZ; 517 case Mips::BC1NEZ: return Mips::BC1EQZ; 518 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; 519 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; 520 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; 521 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; 522 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6; 523 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; 524 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; 525 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6; 526 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6; 527 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6; 528 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; 529 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; 530 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6; 531 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6; 532 case Mips::BEQZC64: return Mips::BNEZC64; 533 case Mips::BNEZC64: return Mips::BEQZC64; 534 case Mips::BEQC64: return Mips::BNEC64; 535 case Mips::BNEC64: return Mips::BEQC64; 536 case Mips::BGEC64: return Mips::BLTC64; 537 case Mips::BGEUC64: return Mips::BLTUC64; 538 case Mips::BLTC64: return Mips::BGEC64; 539 case Mips::BLTUC64: return Mips::BGEUC64; 540 case Mips::BGTZC64: return Mips::BLEZC64; 541 case Mips::BGEZC64: return Mips::BLTZC64; 542 case Mips::BLTZC64: return Mips::BGEZC64; 543 case Mips::BLEZC64: return Mips::BGTZC64; 544 case Mips::BBIT0: return Mips::BBIT1; 545 case Mips::BBIT1: return Mips::BBIT0; 546 case Mips::BBIT032: return Mips::BBIT132; 547 case Mips::BBIT132: return Mips::BBIT032; 548 case Mips::BZ_B: return Mips::BNZ_B; 549 case Mips::BZ_H: return Mips::BNZ_H; 550 case Mips::BZ_W: return Mips::BNZ_W; 551 case Mips::BZ_D: return Mips::BNZ_D; 552 case Mips::BZ_V: return Mips::BNZ_V; 553 case Mips::BNZ_B: return Mips::BZ_B; 554 case Mips::BNZ_H: return Mips::BZ_H; 555 case Mips::BNZ_W: return Mips::BZ_W; 556 case Mips::BNZ_D: return Mips::BZ_D; 557 case Mips::BNZ_V: return Mips::BZ_V; 558 } 559 } 560 561 /// Adjust SP by Amount bytes. 562 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 563 MachineBasicBlock &MBB, 564 MachineBasicBlock::iterator I) const { 565 MipsABIInfo ABI = Subtarget.getABI(); 566 DebugLoc DL; 567 unsigned ADDiu = ABI.GetPtrAddiuOp(); 568 569 if (Amount == 0) 570 return; 571 572 if (isInt<16>(Amount)) { 573 // addi sp, sp, amount 574 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 575 } else { 576 // For numbers which are not 16bit integers we synthesize Amount inline 577 // then add or subtract it from sp. 578 unsigned Opc = ABI.GetPtrAdduOp(); 579 if (Amount < 0) { 580 Opc = ABI.GetPtrSubuOp(); 581 Amount = -Amount; 582 } 583 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); 584 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 585 } 586 } 587 588 /// This function generates the sequence of instructions needed to get the 589 /// result of adding register REG and immediate IMM. 590 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 591 MachineBasicBlock::iterator II, 592 const DebugLoc &DL, 593 unsigned *NewImm) const { 594 MipsAnalyzeImmediate AnalyzeImm; 595 const MipsSubtarget &STI = Subtarget; 596 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 597 unsigned Size = STI.isABI_N64() ? 64 : 32; 598 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 599 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 600 const TargetRegisterClass *RC = STI.isABI_N64() ? 601 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 602 bool LastInstrIsADDiu = NewImm; 603 604 const MipsAnalyzeImmediate::InstSeq &Seq = 605 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 606 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 607 608 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 609 610 // The first instruction can be a LUi, which is different from other 611 // instructions (ADDiu, ORI and SLL) in that it does not have a register 612 // operand. 613 unsigned Reg = RegInfo.createVirtualRegister(RC); 614 615 if (Inst->Opc == LUi) 616 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 617 else 618 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 619 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 620 621 // Build the remaining instructions in Seq. 622 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 623 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 624 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 625 626 if (LastInstrIsADDiu) 627 *NewImm = Inst->ImmOpnd; 628 629 return Reg; 630 } 631 632 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 633 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || 634 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || 635 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || 636 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || 637 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || 638 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || 639 Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || 640 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || 641 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || 642 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || 643 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || 644 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || 645 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || 646 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || 647 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || 648 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || 649 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || 650 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || 651 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || 652 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || 653 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || 654 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || 655 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || 656 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; 657 } 658 659 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, 660 MachineBasicBlock::iterator I) const { 661 662 MachineInstrBuilder MIB; 663 if (Subtarget.isGP64bit()) 664 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) 665 .addReg(Mips::RA_64, RegState::Undef); 666 else 667 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)) 668 .addReg(Mips::RA, RegState::Undef); 669 670 // Retain any imp-use flags. 671 for (auto & MO : I->operands()) { 672 if (MO.isImplicit()) 673 MIB.add(MO); 674 } 675 } 676 677 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB, 678 MachineBasicBlock::iterator I) const { 679 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); 680 } 681 682 std::pair<bool, bool> 683 MipsSEInstrInfo::compareOpndSize(unsigned Opc, 684 const MachineFunction &MF) const { 685 const MCInstrDesc &Desc = get(Opc); 686 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 687 const MipsRegisterInfo *RI = &getRegisterInfo(); 688 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); 689 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); 690 691 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize); 692 } 693 694 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB, 695 MachineBasicBlock::iterator I, 696 unsigned NewOpc) const { 697 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg()); 698 } 699 700 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB, 701 MachineBasicBlock::iterator I, 702 unsigned LoOpc, 703 unsigned HiOpc, 704 bool HasExplicitDef) const { 705 // Expand 706 // lo_hi pseudomtlohi $gpr0, $gpr1 707 // to these two instructions: 708 // mtlo $gpr0 709 // mthi $gpr1 710 711 DebugLoc DL = I->getDebugLoc(); 712 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); 713 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); 714 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); 715 716 // Add lo/hi registers if the mtlo/hi instructions created have explicit 717 // def registers. 718 if (HasExplicitDef) { 719 unsigned DstReg = I->getOperand(0).getReg(); 720 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 721 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 722 LoInst.addReg(DstLo, RegState::Define); 723 HiInst.addReg(DstHi, RegState::Define); 724 } 725 726 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); 727 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); 728 } 729 730 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, 731 MachineBasicBlock::iterator I, 732 unsigned CvtOpc, unsigned MovOpc, 733 bool IsI64) const { 734 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); 735 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 736 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 737 unsigned KillSrc = getKillRegState(Src.isKill()); 738 DebugLoc DL = I->getDebugLoc(); 739 bool DstIsLarger, SrcIsLarger; 740 741 std::tie(DstIsLarger, SrcIsLarger) = 742 compareOpndSize(CvtOpc, *MBB.getParent()); 743 744 if (DstIsLarger) 745 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 746 747 if (SrcIsLarger) 748 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 749 750 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); 751 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 752 } 753 754 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, 755 MachineBasicBlock::iterator I, 756 bool isMicroMips, 757 bool FP64) const { 758 unsigned DstReg = I->getOperand(0).getReg(); 759 unsigned SrcReg = I->getOperand(1).getReg(); 760 unsigned N = I->getOperand(2).getImm(); 761 DebugLoc dl = I->getDebugLoc(); 762 763 assert(N < 2 && "Invalid immediate"); 764 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; 765 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 766 767 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 768 // in MipsSEFrameLowering.cpp. 769 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 770 771 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 772 // in MipsSEFrameLowering.cpp. 773 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 774 775 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { 776 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we 777 // claim to read the whole 64-bits as part of a white lie used to 778 // temporarily work around a widespread bug in the -mfp64 support. 779 // The problem is that none of the 32-bit fpu ops mention the fact 780 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 781 // requires a major overhaul of the FPU implementation which can't 782 // be done right now due to time constraints. 783 // MFHC1 is one of two instructions that are affected since they are 784 // the only instructions that don't read the lower 32-bits. 785 // We therefore pretend that it reads the bottom 32-bits to 786 // artificially create a dependency and prevent the scheduler 787 // changing the behaviour of the code. 788 BuildMI(MBB, I, dl, 789 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) 790 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), 791 DstReg) 792 .addReg(SrcReg); 793 } else 794 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); 795 } 796 797 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, 798 MachineBasicBlock::iterator I, 799 bool isMicroMips, bool FP64) const { 800 unsigned DstReg = I->getOperand(0).getReg(); 801 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 802 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 803 DebugLoc dl = I->getDebugLoc(); 804 const TargetRegisterInfo &TRI = getRegisterInfo(); 805 806 // When mthc1 is available, use: 807 // mtc1 Lo, $fp 808 // mthc1 Hi, $fp 809 // 810 // Otherwise, for O32 FPXX ABI: 811 // spill + reload via ldc1 812 // This case is handled by the frame lowering code. 813 // 814 // Otherwise, for FP32: 815 // mtc1 Lo, $fp 816 // mtc1 Hi, $fp + 1 817 // 818 // The case where dmtc1 is available doesn't need to be handled here 819 // because it never creates a BuildPairF64 node. 820 821 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 822 // in MipsSEFrameLowering.cpp. 823 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 824 825 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 826 // in MipsSEFrameLowering.cpp. 827 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 828 829 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 830 .addReg(LoReg); 831 832 if (Subtarget.hasMTHC1()) { 833 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work 834 // around a widespread bug in the -mfp64 support. 835 // The problem is that none of the 32-bit fpu ops mention the fact 836 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 837 // requires a major overhaul of the FPU implementation which can't 838 // be done right now due to time constraints. 839 // MTHC1 is one of two instructions that are affected since they are 840 // the only instructions that don't read the lower 32-bits. 841 // We therefore pretend that it reads the bottom 32-bits to 842 // artificially create a dependency and prevent the scheduler 843 // changing the behaviour of the code. 844 BuildMI(MBB, I, dl, 845 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) 846 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), 847 DstReg) 848 .addReg(DstReg) 849 .addReg(HiReg); 850 } else if (Subtarget.isABI_FPXX()) 851 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); 852 else 853 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) 854 .addReg(HiReg); 855 } 856 857 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, 858 MachineBasicBlock::iterator I) const { 859 // This pseudo instruction is generated as part of the lowering of 860 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 861 // indirect jump to TargetReg 862 MipsABIInfo ABI = Subtarget.getABI(); 863 unsigned ADDU = ABI.GetPtrAdduOp(); 864 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; 865 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; 866 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; 867 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 868 unsigned OffsetReg = I->getOperand(0).getReg(); 869 unsigned TargetReg = I->getOperand(1).getReg(); 870 871 // addu $ra, $v0, $zero 872 // addu $sp, $sp, $v1 873 // jr $ra (via RetRA) 874 const TargetMachine &TM = MBB.getParent()->getTarget(); 875 if (TM.isPositionIndependent()) 876 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) 877 .addReg(TargetReg) 878 .addReg(ZERO); 879 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA) 880 .addReg(TargetReg) 881 .addReg(ZERO); 882 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); 883 expandRetRA(MBB, I); 884 } 885 886 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { 887 return new MipsSEInstrInfo(STI); 888 } 889