1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsMachineFunction.h"
17 #include "MipsTargetMachine.h"
18 #include "llvm/ADT/STLExtras.h"
19 #include "llvm/CodeGen/MachineInstrBuilder.h"
20 #include "llvm/CodeGen/MachineRegisterInfo.h"
21 #include "llvm/Support/ErrorHandling.h"
22 #include "llvm/Support/TargetRegistry.h"
23 
24 using namespace llvm;
25 
26 MipsSEInstrInfo::MipsSEInstrInfo(MipsTargetMachine &tm)
27   : MipsInstrInfo(tm,
28                   tm.getRelocationModel() == Reloc::PIC_ ? Mips::B : Mips::J),
29     RI(*tm.getSubtargetImpl(), *this),
30     IsN64(tm.getSubtarget<MipsSubtarget>().isABI_N64()) {}
31 
32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
33   return RI;
34 }
35 
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot.  If
39 /// not, return 0.  This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned MipsSEInstrInfo::
42 isLoadFromStackSlot(const MachineInstr *MI, int &FrameIndex) const
43 {
44   unsigned Opc = MI->getOpcode();
45 
46   if ((Opc == Mips::LW)    || (Opc == Mips::LW_P8)  || (Opc == Mips::LD) ||
47       (Opc == Mips::LD_P8) || (Opc == Mips::LWC1)   || (Opc == Mips::LWC1_P8) ||
48       (Opc == Mips::LDC1)  || (Opc == Mips::LDC164) ||
49       (Opc == Mips::LDC164_P8)) {
50     if ((MI->getOperand(1).isFI()) && // is a stack slot
51         (MI->getOperand(2).isImm()) &&  // the imm is zero
52         (isZeroImm(MI->getOperand(2)))) {
53       FrameIndex = MI->getOperand(1).getIndex();
54       return MI->getOperand(0).getReg();
55     }
56   }
57 
58   return 0;
59 }
60 
61 /// isStoreToStackSlot - If the specified machine instruction is a direct
62 /// store to a stack slot, return the virtual or physical register number of
63 /// the source reg along with the FrameIndex of the loaded stack slot.  If
64 /// not, return 0.  This predicate must return 0 if the instruction has
65 /// any side effects other than storing to the stack slot.
66 unsigned MipsSEInstrInfo::
67 isStoreToStackSlot(const MachineInstr *MI, int &FrameIndex) const
68 {
69   unsigned Opc = MI->getOpcode();
70 
71   if ((Opc == Mips::SW)    || (Opc == Mips::SW_P8)  || (Opc == Mips::SD) ||
72       (Opc == Mips::SD_P8) || (Opc == Mips::SWC1)   || (Opc == Mips::SWC1_P8) ||
73       (Opc == Mips::SDC1)  || (Opc == Mips::SDC164) ||
74       (Opc == Mips::SDC164_P8)) {
75     if ((MI->getOperand(1).isFI()) && // is a stack slot
76         (MI->getOperand(2).isImm()) &&  // the imm is zero
77         (isZeroImm(MI->getOperand(2)))) {
78       FrameIndex = MI->getOperand(1).getIndex();
79       return MI->getOperand(0).getReg();
80     }
81   }
82   return 0;
83 }
84 
85 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
86                                   MachineBasicBlock::iterator I, DebugLoc DL,
87                                   unsigned DestReg, unsigned SrcReg,
88                                   bool KillSrc) const {
89   unsigned Opc = 0, ZeroReg = 0;
90 
91   if (Mips::CPURegsRegClass.contains(DestReg)) { // Copy to CPU Reg.
92     if (Mips::CPURegsRegClass.contains(SrcReg))
93       Opc = Mips::OR, ZeroReg = Mips::ZERO;
94     else if (Mips::CCRRegClass.contains(SrcReg))
95       Opc = Mips::CFC1;
96     else if (Mips::FGR32RegClass.contains(SrcReg))
97       Opc = Mips::MFC1;
98     else if (Mips::HIRegsRegClass.contains(SrcReg))
99       Opc = Mips::MFHI, SrcReg = 0;
100     else if (Mips::LORegsRegClass.contains(SrcReg))
101       Opc = Mips::MFLO, SrcReg = 0;
102     else if (Mips::HIRegsDSPRegClass.contains(SrcReg))
103       Opc = Mips::MFHI_DSP;
104     else if (Mips::LORegsDSPRegClass.contains(SrcReg))
105       Opc = Mips::MFLO_DSP;
106   }
107   else if (Mips::CPURegsRegClass.contains(SrcReg)) { // Copy from CPU Reg.
108     if (Mips::CCRRegClass.contains(DestReg))
109       Opc = Mips::CTC1;
110     else if (Mips::FGR32RegClass.contains(DestReg))
111       Opc = Mips::MTC1;
112     else if (Mips::HIRegsRegClass.contains(DestReg))
113       Opc = Mips::MTHI, DestReg = 0;
114     else if (Mips::LORegsRegClass.contains(DestReg))
115       Opc = Mips::MTLO, DestReg = 0;
116     else if (Mips::HIRegsDSPRegClass.contains(DestReg))
117       Opc = Mips::MTHI_DSP;
118     else if (Mips::LORegsDSPRegClass.contains(DestReg))
119       Opc = Mips::MTLO_DSP;
120   }
121   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
122     Opc = Mips::FMOV_S;
123   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
124     Opc = Mips::FMOV_D32;
125   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
126     Opc = Mips::FMOV_D64;
127   else if (Mips::CCRRegClass.contains(DestReg, SrcReg))
128     Opc = Mips::MOVCCRToCCR;
129   else if (Mips::CPU64RegsRegClass.contains(DestReg)) { // Copy to CPU64 Reg.
130     if (Mips::CPU64RegsRegClass.contains(SrcReg))
131       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
132     else if (Mips::HIRegs64RegClass.contains(SrcReg))
133       Opc = Mips::MFHI64, SrcReg = 0;
134     else if (Mips::LORegs64RegClass.contains(SrcReg))
135       Opc = Mips::MFLO64, SrcReg = 0;
136     else if (Mips::FGR64RegClass.contains(SrcReg))
137       Opc = Mips::DMFC1;
138   }
139   else if (Mips::CPU64RegsRegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
140     if (Mips::HIRegs64RegClass.contains(DestReg))
141       Opc = Mips::MTHI64, DestReg = 0;
142     else if (Mips::LORegs64RegClass.contains(DestReg))
143       Opc = Mips::MTLO64, DestReg = 0;
144     else if (Mips::FGR64RegClass.contains(DestReg))
145       Opc = Mips::DMTC1;
146   }
147 
148   assert(Opc && "Cannot copy registers");
149 
150   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
151 
152   if (DestReg)
153     MIB.addReg(DestReg, RegState::Define);
154 
155   if (SrcReg)
156     MIB.addReg(SrcReg, getKillRegState(KillSrc));
157 
158   if (ZeroReg)
159     MIB.addReg(ZeroReg);
160 }
161 
162 void MipsSEInstrInfo::
163 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
164                 unsigned SrcReg, bool isKill, int FI,
165                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
166                 int64_t Offset) const {
167   DebugLoc DL;
168   if (I != MBB.end()) DL = I->getDebugLoc();
169   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
170 
171   unsigned Opc = 0;
172 
173   if (Mips::CPURegsRegClass.hasSubClassEq(RC))
174     Opc = IsN64 ? Mips::SW_P8 : Mips::SW;
175   else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
176     Opc = IsN64 ? Mips::SD_P8 : Mips::SD;
177   else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
178     Opc = IsN64 ? Mips::STORE_AC64_P8 : Mips::STORE_AC64;
179   else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
180     Opc = IsN64 ? Mips::STORE_AC_DSP_P8 : Mips::STORE_AC_DSP;
181   else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
182     Opc = IsN64 ? Mips::STORE_AC128_P8 : Mips::STORE_AC128;
183   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
184     Opc = IsN64 ? Mips::SWC1_P8 : Mips::SWC1;
185   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
186     Opc = Mips::SDC1;
187   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
188     Opc = IsN64 ? Mips::SDC164_P8 : Mips::SDC164;
189 
190   assert(Opc && "Register class not handled!");
191   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
192     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
193 }
194 
195 void MipsSEInstrInfo::
196 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
197                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
198                  const TargetRegisterInfo *TRI, int64_t Offset) const {
199   DebugLoc DL;
200   if (I != MBB.end()) DL = I->getDebugLoc();
201   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
202   unsigned Opc = 0;
203 
204   if (Mips::CPURegsRegClass.hasSubClassEq(RC))
205     Opc = IsN64 ? Mips::LW_P8 : Mips::LW;
206   else if (Mips::CPU64RegsRegClass.hasSubClassEq(RC))
207     Opc = IsN64 ? Mips::LD_P8 : Mips::LD;
208   else if (Mips::ACRegsRegClass.hasSubClassEq(RC))
209     Opc = IsN64 ? Mips::LOAD_AC64_P8 : Mips::LOAD_AC64;
210   else if (Mips::ACRegsDSPRegClass.hasSubClassEq(RC))
211     Opc = IsN64 ? Mips::LOAD_AC_DSP_P8 : Mips::LOAD_AC_DSP;
212   else if (Mips::ACRegs128RegClass.hasSubClassEq(RC))
213     Opc = IsN64 ? Mips::LOAD_AC128_P8 : Mips::LOAD_AC128;
214   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
215     Opc = IsN64 ? Mips::LWC1_P8 : Mips::LWC1;
216   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
217     Opc = Mips::LDC1;
218   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
219     Opc = IsN64 ? Mips::LDC164_P8 : Mips::LDC164;
220 
221   assert(Opc && "Register class not handled!");
222   BuildMI(MBB, I, DL, get(Opc), DestReg).addFrameIndex(FI).addImm(Offset)
223     .addMemOperand(MMO);
224 }
225 
226 bool MipsSEInstrInfo::expandPostRAPseudo(MachineBasicBlock::iterator MI) const {
227   MachineBasicBlock &MBB = *MI->getParent();
228 
229   switch(MI->getDesc().getOpcode()) {
230   default:
231     return false;
232   case Mips::RetRA:
233     ExpandRetRA(MBB, MI, Mips::RET);
234     break;
235   case Mips::BuildPairF64:
236     ExpandBuildPairF64(MBB, MI);
237     break;
238   case Mips::ExtractElementF64:
239     ExpandExtractElementF64(MBB, MI);
240     break;
241   case Mips::MIPSeh_return32:
242   case Mips::MIPSeh_return64:
243     ExpandEhReturn(MBB, MI);
244     break;
245   }
246 
247   MBB.erase(MI);
248   return true;
249 }
250 
251 /// GetOppositeBranchOpc - Return the inverse of the specified
252 /// opcode, e.g. turning BEQ to BNE.
253 unsigned MipsSEInstrInfo::GetOppositeBranchOpc(unsigned Opc) const {
254   switch (Opc) {
255   default:           llvm_unreachable("Illegal opcode!");
256   case Mips::BEQ:    return Mips::BNE;
257   case Mips::BNE:    return Mips::BEQ;
258   case Mips::BGTZ:   return Mips::BLEZ;
259   case Mips::BGEZ:   return Mips::BLTZ;
260   case Mips::BLTZ:   return Mips::BGEZ;
261   case Mips::BLEZ:   return Mips::BGTZ;
262   case Mips::BEQ64:  return Mips::BNE64;
263   case Mips::BNE64:  return Mips::BEQ64;
264   case Mips::BGTZ64: return Mips::BLEZ64;
265   case Mips::BGEZ64: return Mips::BLTZ64;
266   case Mips::BLTZ64: return Mips::BGEZ64;
267   case Mips::BLEZ64: return Mips::BGTZ64;
268   case Mips::BC1T:   return Mips::BC1F;
269   case Mips::BC1F:   return Mips::BC1T;
270   }
271 }
272 
273 /// Adjust SP by Amount bytes.
274 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
275                                      MachineBasicBlock &MBB,
276                                      MachineBasicBlock::iterator I) const {
277   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
278   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
279   unsigned ADDu = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
280   unsigned ADDiu = STI.isABI_N64() ? Mips::DADDiu : Mips::ADDiu;
281 
282   if (isInt<16>(Amount))// addi sp, sp, amount
283     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
284   else { // Expand immediate that doesn't fit in 16-bit.
285     unsigned Reg = loadImmediate(Amount, MBB, I, DL, 0);
286     BuildMI(MBB, I, DL, get(ADDu), SP).addReg(SP).addReg(Reg, RegState::Kill);
287   }
288 }
289 
290 /// This function generates the sequence of instructions needed to get the
291 /// result of adding register REG and immediate IMM.
292 unsigned
293 MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
294                                MachineBasicBlock::iterator II, DebugLoc DL,
295                                unsigned *NewImm) const {
296   MipsAnalyzeImmediate AnalyzeImm;
297   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
298   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
299   unsigned Size = STI.isABI_N64() ? 64 : 32;
300   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
301   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
302   const TargetRegisterClass *RC = STI.isABI_N64() ?
303     &Mips::CPU64RegsRegClass : &Mips::CPURegsRegClass;
304   bool LastInstrIsADDiu = NewImm;
305 
306   const MipsAnalyzeImmediate::InstSeq &Seq =
307     AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
308   MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
309 
310   assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
311 
312   // The first instruction can be a LUi, which is different from other
313   // instructions (ADDiu, ORI and SLL) in that it does not have a register
314   // operand.
315   unsigned Reg = RegInfo.createVirtualRegister(RC);
316 
317   if (Inst->Opc == LUi)
318     BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
319   else
320     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
321       .addImm(SignExtend64<16>(Inst->ImmOpnd));
322 
323   // Build the remaining instructions in Seq.
324   for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
325     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
326       .addImm(SignExtend64<16>(Inst->ImmOpnd));
327 
328   if (LastInstrIsADDiu)
329     *NewImm = Inst->ImmOpnd;
330 
331   return Reg;
332 }
333 
334 unsigned MipsSEInstrInfo::GetAnalyzableBrOpc(unsigned Opc) const {
335   return (Opc == Mips::BEQ    || Opc == Mips::BNE    || Opc == Mips::BGTZ   ||
336           Opc == Mips::BGEZ   || Opc == Mips::BLTZ   || Opc == Mips::BLEZ   ||
337           Opc == Mips::BEQ64  || Opc == Mips::BNE64  || Opc == Mips::BGTZ64 ||
338           Opc == Mips::BGEZ64 || Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 ||
339           Opc == Mips::BC1T   || Opc == Mips::BC1F   || Opc == Mips::B      ||
340           Opc == Mips::J) ?
341          Opc : 0;
342 }
343 
344 void MipsSEInstrInfo::ExpandRetRA(MachineBasicBlock &MBB,
345                                 MachineBasicBlock::iterator I,
346                                 unsigned Opc) const {
347   BuildMI(MBB, I, I->getDebugLoc(), get(Opc)).addReg(Mips::RA);
348 }
349 
350 void MipsSEInstrInfo::ExpandExtractElementF64(MachineBasicBlock &MBB,
351                                           MachineBasicBlock::iterator I) const {
352   unsigned DstReg = I->getOperand(0).getReg();
353   unsigned SrcReg = I->getOperand(1).getReg();
354   unsigned N = I->getOperand(2).getImm();
355   const MCInstrDesc& Mfc1Tdd = get(Mips::MFC1);
356   DebugLoc dl = I->getDebugLoc();
357 
358   assert(N < 2 && "Invalid immediate");
359   unsigned SubIdx = N ? Mips::sub_fpodd : Mips::sub_fpeven;
360   unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
361 
362   BuildMI(MBB, I, dl, Mfc1Tdd, DstReg).addReg(SubReg);
363 }
364 
365 void MipsSEInstrInfo::ExpandBuildPairF64(MachineBasicBlock &MBB,
366                                        MachineBasicBlock::iterator I) const {
367   unsigned DstReg = I->getOperand(0).getReg();
368   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
369   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
370   DebugLoc dl = I->getDebugLoc();
371   const TargetRegisterInfo &TRI = getRegisterInfo();
372 
373   // mtc1 Lo, $fp
374   // mtc1 Hi, $fp + 1
375   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpeven))
376     .addReg(LoReg);
377   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_fpodd))
378     .addReg(HiReg);
379 }
380 
381 void MipsSEInstrInfo::ExpandEhReturn(MachineBasicBlock &MBB,
382                                      MachineBasicBlock::iterator I) const {
383   // This pseudo instruction is generated as part of the lowering of
384   // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
385   // indirect jump to TargetReg
386   const MipsSubtarget &STI = TM.getSubtarget<MipsSubtarget>();
387   unsigned ADDU = STI.isABI_N64() ? Mips::DADDu : Mips::ADDu;
388   unsigned OR = STI.isABI_N64() ? Mips::OR64 : Mips::OR;
389   unsigned JR = STI.isABI_N64() ? Mips::JR64 : Mips::JR;
390   unsigned SP = STI.isABI_N64() ? Mips::SP_64 : Mips::SP;
391   unsigned RA = STI.isABI_N64() ? Mips::RA_64 : Mips::RA;
392   unsigned T9 = STI.isABI_N64() ? Mips::T9_64 : Mips::T9;
393   unsigned ZERO = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
394   unsigned OffsetReg = I->getOperand(0).getReg();
395   unsigned TargetReg = I->getOperand(1).getReg();
396 
397   // or   $ra, $v0, $zero
398   // addu $sp, $sp, $v1
399   // jr   $ra
400   if (TM.getRelocationModel() == Reloc::PIC_)
401     BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), T9)
402         .addReg(TargetReg).addReg(ZERO);
403   BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(OR), RA)
404       .addReg(TargetReg).addReg(ZERO);
405   BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(ADDU), SP)
406       .addReg(SP).addReg(OffsetReg);
407   BuildMI(MBB, I, I->getDebugLoc(), TM.getInstrInfo()->get(JR)).addReg(RA);
408 }
409 
410 const MipsInstrInfo *llvm::createMipsSEInstrInfo(MipsTargetMachine &TM) {
411   return new MipsSEInstrInfo(TM);
412 }
413