1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // This file contains the Mips32/64 implementation of the TargetInstrInfo class.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEInstrInfo.h"
15 #include "InstPrinter/MipsInstPrinter.h"
16 #include "MipsAnalyzeImmediate.h"
17 #include "MipsMachineFunction.h"
18 #include "MipsTargetMachine.h"
19 #include "llvm/ADT/STLExtras.h"
20 #include "llvm/CodeGen/MachineInstrBuilder.h"
21 #include "llvm/CodeGen/MachineRegisterInfo.h"
22 #include "llvm/Support/ErrorHandling.h"
23 #include "llvm/Support/MathExtras.h"
24 #include "llvm/Support/TargetRegistry.h"
25 
26 using namespace llvm;
27 
28 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI)
29     : MipsInstrInfo(STI, STI.isPositionIndependent() ? Mips::B : Mips::J),
30       RI() {}
31 
32 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const {
33   return RI;
34 }
35 
36 /// isLoadFromStackSlot - If the specified machine instruction is a direct
37 /// load from a stack slot, return the virtual or physical register number of
38 /// the destination along with the FrameIndex of the loaded stack slot.  If
39 /// not, return 0.  This predicate must return 0 if the instruction has
40 /// any side effects other than loading from the stack slot.
41 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
42                                               int &FrameIndex) const {
43   unsigned Opc = MI.getOpcode();
44 
45   if ((Opc == Mips::LW)   || (Opc == Mips::LD)   ||
46       (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) {
47     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
48         (MI.getOperand(2).isImm()) && // the imm is zero
49         (isZeroImm(MI.getOperand(2)))) {
50       FrameIndex = MI.getOperand(1).getIndex();
51       return MI.getOperand(0).getReg();
52     }
53   }
54 
55   return 0;
56 }
57 
58 /// isStoreToStackSlot - If the specified machine instruction is a direct
59 /// store to a stack slot, return the virtual or physical register number of
60 /// the source reg along with the FrameIndex of the loaded stack slot.  If
61 /// not, return 0.  This predicate must return 0 if the instruction has
62 /// any side effects other than storing to the stack slot.
63 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI,
64                                              int &FrameIndex) const {
65   unsigned Opc = MI.getOpcode();
66 
67   if ((Opc == Mips::SW)   || (Opc == Mips::SD)   ||
68       (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) {
69     if ((MI.getOperand(1).isFI()) &&  // is a stack slot
70         (MI.getOperand(2).isImm()) && // the imm is zero
71         (isZeroImm(MI.getOperand(2)))) {
72       FrameIndex = MI.getOperand(1).getIndex();
73       return MI.getOperand(0).getReg();
74     }
75   }
76   return 0;
77 }
78 
79 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB,
80                                   MachineBasicBlock::iterator I,
81                                   const DebugLoc &DL, unsigned DestReg,
82                                   unsigned SrcReg, bool KillSrc) const {
83   unsigned Opc = 0, ZeroReg = 0;
84   bool isMicroMips = Subtarget.inMicroMipsMode();
85 
86   if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg.
87     if (Mips::GPR32RegClass.contains(SrcReg)) {
88       if (isMicroMips)
89         Opc = Mips::MOVE16_MM;
90       else
91         Opc = Mips::OR, ZeroReg = Mips::ZERO;
92     } else if (Mips::CCRRegClass.contains(SrcReg))
93       Opc = Mips::CFC1;
94     else if (Mips::FGR32RegClass.contains(SrcReg))
95       Opc = Mips::MFC1;
96     else if (Mips::HI32RegClass.contains(SrcReg)) {
97       Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
98       SrcReg = 0;
99     } else if (Mips::LO32RegClass.contains(SrcReg)) {
100       Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
101       SrcReg = 0;
102     } else if (Mips::HI32DSPRegClass.contains(SrcReg))
103       Opc = Mips::MFHI_DSP;
104     else if (Mips::LO32DSPRegClass.contains(SrcReg))
105       Opc = Mips::MFLO_DSP;
106     else if (Mips::DSPCCRegClass.contains(SrcReg)) {
107       BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4)
108         .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc));
109       return;
110     }
111     else if (Mips::MSACtrlRegClass.contains(SrcReg))
112       Opc = Mips::CFCMSA;
113   }
114   else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg.
115     if (Mips::CCRRegClass.contains(DestReg))
116       Opc = Mips::CTC1;
117     else if (Mips::FGR32RegClass.contains(DestReg))
118       Opc = Mips::MTC1;
119     else if (Mips::HI32RegClass.contains(DestReg))
120       Opc = Mips::MTHI, DestReg = 0;
121     else if (Mips::LO32RegClass.contains(DestReg))
122       Opc = Mips::MTLO, DestReg = 0;
123     else if (Mips::HI32DSPRegClass.contains(DestReg))
124       Opc = Mips::MTHI_DSP;
125     else if (Mips::LO32DSPRegClass.contains(DestReg))
126       Opc = Mips::MTLO_DSP;
127     else if (Mips::DSPCCRegClass.contains(DestReg)) {
128       BuildMI(MBB, I, DL, get(Mips::WRDSP))
129         .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4)
130         .addReg(DestReg, RegState::ImplicitDefine);
131       return;
132     } else if (Mips::MSACtrlRegClass.contains(DestReg)) {
133       BuildMI(MBB, I, DL, get(Mips::CTCMSA))
134           .addReg(DestReg)
135           .addReg(SrcReg, getKillRegState(KillSrc));
136       return;
137     }
138   }
139   else if (Mips::FGR32RegClass.contains(DestReg, SrcReg))
140     Opc = Mips::FMOV_S;
141   else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg))
142     Opc = Mips::FMOV_D32;
143   else if (Mips::FGR64RegClass.contains(DestReg, SrcReg))
144     Opc = Mips::FMOV_D64;
145   else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg.
146     if (Mips::GPR64RegClass.contains(SrcReg))
147       Opc = Mips::OR64, ZeroReg = Mips::ZERO_64;
148     else if (Mips::HI64RegClass.contains(SrcReg))
149       Opc = Mips::MFHI64, SrcReg = 0;
150     else if (Mips::LO64RegClass.contains(SrcReg))
151       Opc = Mips::MFLO64, SrcReg = 0;
152     else if (Mips::FGR64RegClass.contains(SrcReg))
153       Opc = Mips::DMFC1;
154   }
155   else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg.
156     if (Mips::HI64RegClass.contains(DestReg))
157       Opc = Mips::MTHI64, DestReg = 0;
158     else if (Mips::LO64RegClass.contains(DestReg))
159       Opc = Mips::MTLO64, DestReg = 0;
160     else if (Mips::FGR64RegClass.contains(DestReg))
161       Opc = Mips::DMTC1;
162   }
163   else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg
164     if (Mips::MSA128BRegClass.contains(SrcReg))
165       Opc = Mips::MOVE_V;
166   }
167 
168   assert(Opc && "Cannot copy registers");
169 
170   MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc));
171 
172   if (DestReg)
173     MIB.addReg(DestReg, RegState::Define);
174 
175   if (SrcReg)
176     MIB.addReg(SrcReg, getKillRegState(KillSrc));
177 
178   if (ZeroReg)
179     MIB.addReg(ZeroReg);
180 }
181 
182 void MipsSEInstrInfo::
183 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
184                 unsigned SrcReg, bool isKill, int FI,
185                 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI,
186                 int64_t Offset) const {
187   DebugLoc DL;
188   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore);
189 
190   unsigned Opc = 0;
191 
192   if (Mips::GPR32RegClass.hasSubClassEq(RC))
193     Opc = Mips::SW;
194   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
195     Opc = Mips::SD;
196   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
197     Opc = Mips::STORE_ACC64;
198   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
199     Opc = Mips::STORE_ACC64DSP;
200   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
201     Opc = Mips::STORE_ACC128;
202   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
203     Opc = Mips::STORE_CCOND_DSP;
204   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
205     Opc = Mips::SWC1;
206   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
207     Opc = Mips::SDC1;
208   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
209     Opc = Mips::SDC164;
210   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
211     Opc = Mips::ST_B;
212   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
213            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
214     Opc = Mips::ST_H;
215   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
216            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
217     Opc = Mips::ST_W;
218   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
219            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
220     Opc = Mips::ST_D;
221   else if (Mips::LO32RegClass.hasSubClassEq(RC))
222     Opc = Mips::SW;
223   else if (Mips::LO64RegClass.hasSubClassEq(RC))
224     Opc = Mips::SD;
225   else if (Mips::HI32RegClass.hasSubClassEq(RC))
226     Opc = Mips::SW;
227   else if (Mips::HI64RegClass.hasSubClassEq(RC))
228     Opc = Mips::SD;
229 
230   // Hi, Lo are normally caller save but they are callee save
231   // for interrupt handling.
232   const Function *Func = MBB.getParent()->getFunction();
233   if (Func->hasFnAttribute("interrupt")) {
234     if (Mips::HI32RegClass.hasSubClassEq(RC)) {
235       BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0);
236       SrcReg = Mips::K0;
237     } else if (Mips::HI64RegClass.hasSubClassEq(RC)) {
238       BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64);
239       SrcReg = Mips::K0_64;
240     } else if (Mips::LO32RegClass.hasSubClassEq(RC)) {
241       BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0);
242       SrcReg = Mips::K0;
243     } else if (Mips::LO64RegClass.hasSubClassEq(RC)) {
244       BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64);
245       SrcReg = Mips::K0_64;
246     }
247   }
248 
249   assert(Opc && "Register class not handled!");
250   BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill))
251     .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO);
252 }
253 
254 void MipsSEInstrInfo::
255 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I,
256                  unsigned DestReg, int FI, const TargetRegisterClass *RC,
257                  const TargetRegisterInfo *TRI, int64_t Offset) const {
258   DebugLoc DL;
259   if (I != MBB.end()) DL = I->getDebugLoc();
260   MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad);
261   unsigned Opc = 0;
262 
263   const Function *Func = MBB.getParent()->getFunction();
264   bool ReqIndirectLoad = Func->hasFnAttribute("interrupt") &&
265                          (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 ||
266                           DestReg == Mips::HI0 || DestReg == Mips::HI0_64);
267 
268   if (Mips::GPR32RegClass.hasSubClassEq(RC))
269     Opc = Mips::LW;
270   else if (Mips::GPR64RegClass.hasSubClassEq(RC))
271     Opc = Mips::LD;
272   else if (Mips::ACC64RegClass.hasSubClassEq(RC))
273     Opc = Mips::LOAD_ACC64;
274   else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC))
275     Opc = Mips::LOAD_ACC64DSP;
276   else if (Mips::ACC128RegClass.hasSubClassEq(RC))
277     Opc = Mips::LOAD_ACC128;
278   else if (Mips::DSPCCRegClass.hasSubClassEq(RC))
279     Opc = Mips::LOAD_CCOND_DSP;
280   else if (Mips::FGR32RegClass.hasSubClassEq(RC))
281     Opc = Mips::LWC1;
282   else if (Mips::AFGR64RegClass.hasSubClassEq(RC))
283     Opc = Mips::LDC1;
284   else if (Mips::FGR64RegClass.hasSubClassEq(RC))
285     Opc = Mips::LDC164;
286   else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8))
287     Opc = Mips::LD_B;
288   else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) ||
289            TRI->isTypeLegalForClass(*RC, MVT::v8f16))
290     Opc = Mips::LD_H;
291   else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) ||
292            TRI->isTypeLegalForClass(*RC, MVT::v4f32))
293     Opc = Mips::LD_W;
294   else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) ||
295            TRI->isTypeLegalForClass(*RC, MVT::v2f64))
296     Opc = Mips::LD_D;
297   else if (Mips::HI32RegClass.hasSubClassEq(RC))
298     Opc = Mips::LW;
299   else if (Mips::HI64RegClass.hasSubClassEq(RC))
300     Opc = Mips::LD;
301   else if (Mips::LO32RegClass.hasSubClassEq(RC))
302     Opc = Mips::LW;
303   else if (Mips::LO64RegClass.hasSubClassEq(RC))
304     Opc = Mips::LD;
305 
306   assert(Opc && "Register class not handled!");
307 
308   if (!ReqIndirectLoad)
309     BuildMI(MBB, I, DL, get(Opc), DestReg)
310         .addFrameIndex(FI)
311         .addImm(Offset)
312         .addMemOperand(MMO);
313   else {
314     // Load HI/LO through K0. Notably the DestReg is encoded into the
315     // instruction itself.
316     unsigned Reg = Mips::K0;
317     unsigned LdOp = Mips::MTLO;
318     if (DestReg == Mips::HI0)
319       LdOp = Mips::MTHI;
320 
321     if (Subtarget.getABI().ArePtrs64bit()) {
322       Reg = Mips::K0_64;
323       if (DestReg == Mips::HI0_64)
324         LdOp = Mips::MTHI64;
325       else
326         LdOp = Mips::MTLO64;
327     }
328 
329     BuildMI(MBB, I, DL, get(Opc), Reg)
330         .addFrameIndex(FI)
331         .addImm(Offset)
332         .addMemOperand(MMO);
333     BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg);
334   }
335 }
336 
337 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const {
338   MachineBasicBlock &MBB = *MI.getParent();
339   bool isMicroMips = Subtarget.inMicroMipsMode();
340   unsigned Opc;
341 
342   switch (MI.getDesc().getOpcode()) {
343   default:
344     return false;
345   case Mips::RetRA:
346     expandRetRA(MBB, MI);
347     break;
348   case Mips::ERet:
349     expandERet(MBB, MI);
350     break;
351   case Mips::PseudoMFHI:
352     Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI;
353     expandPseudoMFHiLo(MBB, MI, Opc);
354     break;
355   case Mips::PseudoMFLO:
356     Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO;
357     expandPseudoMFHiLo(MBB, MI, Opc);
358     break;
359   case Mips::PseudoMFHI64:
360     expandPseudoMFHiLo(MBB, MI, Mips::MFHI64);
361     break;
362   case Mips::PseudoMFLO64:
363     expandPseudoMFHiLo(MBB, MI, Mips::MFLO64);
364     break;
365   case Mips::PseudoMTLOHI:
366     expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false);
367     break;
368   case Mips::PseudoMTLOHI64:
369     expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false);
370     break;
371   case Mips::PseudoMTLOHI_DSP:
372     expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true);
373     break;
374   case Mips::PseudoCVT_S_W:
375     expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false);
376     break;
377   case Mips::PseudoCVT_D32_W:
378     expandCvtFPInt(MBB, MI, Mips::CVT_D32_W, Mips::MTC1, false);
379     break;
380   case Mips::PseudoCVT_S_L:
381     expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true);
382     break;
383   case Mips::PseudoCVT_D64_W:
384     expandCvtFPInt(MBB, MI, Mips::CVT_D64_W, Mips::MTC1, true);
385     break;
386   case Mips::PseudoCVT_D64_L:
387     expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true);
388     break;
389   case Mips::BuildPairF64:
390     expandBuildPairF64(MBB, MI, false);
391     break;
392   case Mips::BuildPairF64_64:
393     expandBuildPairF64(MBB, MI, true);
394     break;
395   case Mips::ExtractElementF64:
396     expandExtractElementF64(MBB, MI, false);
397     break;
398   case Mips::ExtractElementF64_64:
399     expandExtractElementF64(MBB, MI, true);
400     break;
401   case Mips::MIPSeh_return32:
402   case Mips::MIPSeh_return64:
403     expandEhReturn(MBB, MI);
404     break;
405   }
406 
407   MBB.erase(MI);
408   return true;
409 }
410 
411 /// getOppositeBranchOpc - Return the inverse of the specified
412 /// opcode, e.g. turning BEQ to BNE.
413 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const {
414   switch (Opc) {
415   default:           llvm_unreachable("Illegal opcode!");
416   case Mips::BEQ:    return Mips::BNE;
417   case Mips::BEQ_MM: return Mips::BNE_MM;
418   case Mips::BNE:    return Mips::BEQ;
419   case Mips::BNE_MM: return Mips::BEQ_MM;
420   case Mips::BGTZ:   return Mips::BLEZ;
421   case Mips::BGEZ:   return Mips::BLTZ;
422   case Mips::BLTZ:   return Mips::BGEZ;
423   case Mips::BLEZ:   return Mips::BGTZ;
424   case Mips::BEQ64:  return Mips::BNE64;
425   case Mips::BNE64:  return Mips::BEQ64;
426   case Mips::BGTZ64: return Mips::BLEZ64;
427   case Mips::BGEZ64: return Mips::BLTZ64;
428   case Mips::BLTZ64: return Mips::BGEZ64;
429   case Mips::BLEZ64: return Mips::BGTZ64;
430   case Mips::BC1T:   return Mips::BC1F;
431   case Mips::BC1F:   return Mips::BC1T;
432   case Mips::BEQZC_MM: return Mips::BNEZC_MM;
433   case Mips::BNEZC_MM: return Mips::BEQZC_MM;
434   case Mips::BEQZC:  return Mips::BNEZC;
435   case Mips::BNEZC:  return Mips::BEQZC;
436   case Mips::BEQC:   return Mips::BNEC;
437   case Mips::BNEC:   return Mips::BEQC;
438   case Mips::BGTZC:  return Mips::BLEZC;
439   case Mips::BGEZC:  return Mips::BLTZC;
440   case Mips::BLTZC:  return Mips::BGEZC;
441   case Mips::BLEZC:  return Mips::BGTZC;
442   case Mips::BEQZC64:  return Mips::BNEZC64;
443   case Mips::BNEZC64:  return Mips::BEQZC64;
444   case Mips::BEQC64:   return Mips::BNEC64;
445   case Mips::BNEC64:   return Mips::BEQC64;
446   case Mips::BGEC64:   return Mips::BLTC64;
447   case Mips::BGEUC64:  return Mips::BLTUC64;
448   case Mips::BLTC64:   return Mips::BGEC64;
449   case Mips::BLTUC64:  return Mips::BGEUC64;
450   case Mips::BGTZC64:  return Mips::BLEZC64;
451   case Mips::BGEZC64:  return Mips::BLTZC64;
452   case Mips::BLTZC64:  return Mips::BGEZC64;
453   case Mips::BLEZC64:  return Mips::BGTZC64;
454   }
455 }
456 
457 /// Adjust SP by Amount bytes.
458 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount,
459                                      MachineBasicBlock &MBB,
460                                      MachineBasicBlock::iterator I) const {
461   MipsABIInfo ABI = Subtarget.getABI();
462   DebugLoc DL;
463   unsigned ADDiu = ABI.GetPtrAddiuOp();
464 
465   if (Amount == 0)
466     return;
467 
468   if (isInt<16>(Amount)) {
469     // addi sp, sp, amount
470     BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount);
471   } else {
472     // For numbers which are not 16bit integers we synthesize Amount inline
473     // then add or subtract it from sp.
474     unsigned Opc = ABI.GetPtrAdduOp();
475     if (Amount < 0) {
476       Opc = ABI.GetPtrSubuOp();
477       Amount = -Amount;
478     }
479     unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr);
480     BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill);
481   }
482 }
483 
484 /// This function generates the sequence of instructions needed to get the
485 /// result of adding register REG and immediate IMM.
486 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB,
487                                         MachineBasicBlock::iterator II,
488                                         const DebugLoc &DL,
489                                         unsigned *NewImm) const {
490   MipsAnalyzeImmediate AnalyzeImm;
491   const MipsSubtarget &STI = Subtarget;
492   MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo();
493   unsigned Size = STI.isABI_N64() ? 64 : 32;
494   unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi;
495   unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO;
496   const TargetRegisterClass *RC = STI.isABI_N64() ?
497     &Mips::GPR64RegClass : &Mips::GPR32RegClass;
498   bool LastInstrIsADDiu = NewImm;
499 
500   const MipsAnalyzeImmediate::InstSeq &Seq =
501     AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu);
502   MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
503 
504   assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1)));
505 
506   // The first instruction can be a LUi, which is different from other
507   // instructions (ADDiu, ORI and SLL) in that it does not have a register
508   // operand.
509   unsigned Reg = RegInfo.createVirtualRegister(RC);
510 
511   if (Inst->Opc == LUi)
512     BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd));
513   else
514     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg)
515       .addImm(SignExtend64<16>(Inst->ImmOpnd));
516 
517   // Build the remaining instructions in Seq.
518   for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst)
519     BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill)
520       .addImm(SignExtend64<16>(Inst->ImmOpnd));
521 
522   if (LastInstrIsADDiu)
523     *NewImm = Inst->ImmOpnd;
524 
525   return Reg;
526 }
527 
528 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const {
529   return (Opc == Mips::BEQ    || Opc == Mips::BEQ_MM || Opc == Mips::BNE    ||
530           Opc == Mips::BNE_MM || Opc == Mips::BGTZ   || Opc == Mips::BGEZ   ||
531           Opc == Mips::BLTZ   || Opc == Mips::BLEZ   || Opc == Mips::BEQ64  ||
532           Opc == Mips::BNE64  || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 ||
533           Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T   ||
534           Opc == Mips::BC1F   || Opc == Mips::B      || Opc == Mips::J      ||
535           Opc == Mips::BEQZC_MM || Opc == Mips::BNEZC_MM || Opc == Mips::BEQC ||
536           Opc == Mips::BNEC   || Opc == Mips::BLTC   || Opc == Mips::BGEC   ||
537           Opc == Mips::BLTUC  || Opc == Mips::BGEUC  || Opc == Mips::BGTZC  ||
538           Opc == Mips::BLEZC  || Opc == Mips::BGEZC  || Opc == Mips::BLTZC  ||
539           Opc == Mips::BEQZC  || Opc == Mips::BNEZC  || Opc == Mips::BEQZC64 ||
540           Opc == Mips::BNEZC64 || Opc == Mips::BEQC64 || Opc == Mips::BNEC64 ||
541           Opc == Mips::BGEC64 || Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 ||
542           Opc == Mips::BLTUC64 || Opc == Mips::BGTZC64 ||
543           Opc == Mips::BGEZC64 || Opc == Mips::BLTZC64 ||
544           Opc == Mips::BLEZC64 || Opc == Mips::BC) ? Opc : 0;
545 }
546 
547 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB,
548                                   MachineBasicBlock::iterator I) const {
549 
550   MachineInstrBuilder MIB;
551   if (Subtarget.isGP64bit())
552     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64))
553               .addReg(Mips::RA_64, RegState::Undef);
554   else
555     MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn))
556               .addReg(Mips::RA, RegState::Undef);
557 
558   // Retain any imp-use flags.
559   for (auto & MO : I->operands()) {
560     if (MO.isImplicit())
561       MIB.add(MO);
562   }
563 }
564 
565 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB,
566                                  MachineBasicBlock::iterator I) const {
567   BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET));
568 }
569 
570 std::pair<bool, bool>
571 MipsSEInstrInfo::compareOpndSize(unsigned Opc,
572                                  const MachineFunction &MF) const {
573   const MCInstrDesc &Desc = get(Opc);
574   assert(Desc.NumOperands == 2 && "Unary instruction expected.");
575   const MipsRegisterInfo *RI = &getRegisterInfo();
576   unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF));
577   unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF));
578 
579   return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize);
580 }
581 
582 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB,
583                                          MachineBasicBlock::iterator I,
584                                          unsigned NewOpc) const {
585   BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg());
586 }
587 
588 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB,
589                                          MachineBasicBlock::iterator I,
590                                          unsigned LoOpc,
591                                          unsigned HiOpc,
592                                          bool HasExplicitDef) const {
593   // Expand
594   //  lo_hi pseudomtlohi $gpr0, $gpr1
595   // to these two instructions:
596   //  mtlo $gpr0
597   //  mthi $gpr1
598 
599   DebugLoc DL = I->getDebugLoc();
600   const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2);
601   MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc));
602   MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc));
603 
604   // Add lo/hi registers if the mtlo/hi instructions created have explicit
605   // def registers.
606   if (HasExplicitDef) {
607     unsigned DstReg = I->getOperand(0).getReg();
608     unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
609     unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi);
610     LoInst.addReg(DstLo, RegState::Define);
611     HiInst.addReg(DstHi, RegState::Define);
612   }
613 
614   LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill()));
615   HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill()));
616 }
617 
618 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB,
619                                      MachineBasicBlock::iterator I,
620                                      unsigned CvtOpc, unsigned MovOpc,
621                                      bool IsI64) const {
622   const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc);
623   const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1);
624   unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg;
625   unsigned KillSrc =  getKillRegState(Src.isKill());
626   DebugLoc DL = I->getDebugLoc();
627   bool DstIsLarger, SrcIsLarger;
628 
629   std::tie(DstIsLarger, SrcIsLarger) =
630       compareOpndSize(CvtOpc, *MBB.getParent());
631 
632   if (DstIsLarger)
633     TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
634 
635   if (SrcIsLarger)
636     DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo);
637 
638   BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc);
639   BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill);
640 }
641 
642 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB,
643                                               MachineBasicBlock::iterator I,
644                                               bool FP64) const {
645   unsigned DstReg = I->getOperand(0).getReg();
646   unsigned SrcReg = I->getOperand(1).getReg();
647   unsigned N = I->getOperand(2).getImm();
648   DebugLoc dl = I->getDebugLoc();
649 
650   assert(N < 2 && "Invalid immediate");
651   unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo;
652   unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx);
653 
654   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
655   // in MipsSEFrameLowering.cpp.
656   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
657 
658   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
659   // in MipsSEFrameLowering.cpp.
660   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
661 
662   if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) {
663     // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we
664     //        claim to read the whole 64-bits as part of a white lie used to
665     //        temporarily work around a widespread bug in the -mfp64 support.
666     //        The problem is that none of the 32-bit fpu ops mention the fact
667     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
668     //        requires a major overhaul of the FPU implementation which can't
669     //        be done right now due to time constraints.
670     //        MFHC1 is one of two instructions that are affected since they are
671     //        the only instructions that don't read the lower 32-bits.
672     //        We therefore pretend that it reads the bottom 32-bits to
673     //        artificially create a dependency and prevent the scheduler
674     //        changing the behaviour of the code.
675     BuildMI(MBB, I, dl, get(FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32), DstReg)
676         .addReg(SrcReg);
677   } else
678     BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg);
679 }
680 
681 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB,
682                                          MachineBasicBlock::iterator I,
683                                          bool FP64) const {
684   unsigned DstReg = I->getOperand(0).getReg();
685   unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg();
686   const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1);
687   DebugLoc dl = I->getDebugLoc();
688   const TargetRegisterInfo &TRI = getRegisterInfo();
689 
690   // When mthc1 is available, use:
691   //   mtc1 Lo, $fp
692   //   mthc1 Hi, $fp
693   //
694   // Otherwise, for O32 FPXX ABI:
695   //   spill + reload via ldc1
696   // This case is handled by the frame lowering code.
697   //
698   // Otherwise, for FP32:
699   //   mtc1 Lo, $fp
700   //   mtc1 Hi, $fp + 1
701   //
702   // The case where dmtc1 is available doesn't need to be handled here
703   // because it never creates a BuildPairF64 node.
704 
705   // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload
706   // in MipsSEFrameLowering.cpp.
707   assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2()));
708 
709   // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload
710   // in MipsSEFrameLowering.cpp.
711   assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg()));
712 
713   BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo))
714     .addReg(LoReg);
715 
716   if (Subtarget.hasMTHC1()) {
717     // FIXME: The .addReg(DstReg) is a white lie used to temporarily work
718     //        around a widespread bug in the -mfp64 support.
719     //        The problem is that none of the 32-bit fpu ops mention the fact
720     //        that they clobber the upper 32-bits of the 64-bit FPR. Fixing that
721     //        requires a major overhaul of the FPU implementation which can't
722     //        be done right now due to time constraints.
723     //        MTHC1 is one of two instructions that are affected since they are
724     //        the only instructions that don't read the lower 32-bits.
725     //        We therefore pretend that it reads the bottom 32-bits to
726     //        artificially create a dependency and prevent the scheduler
727     //        changing the behaviour of the code.
728     BuildMI(MBB, I, dl, get(FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32), DstReg)
729         .addReg(DstReg)
730         .addReg(HiReg);
731   } else if (Subtarget.isABI_FPXX())
732     llvm_unreachable("BuildPairF64 not expanded in frame lowering code!");
733   else
734     BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi))
735       .addReg(HiReg);
736 }
737 
738 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB,
739                                      MachineBasicBlock::iterator I) const {
740   // This pseudo instruction is generated as part of the lowering of
741   // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and
742   // indirect jump to TargetReg
743   MipsABIInfo ABI = Subtarget.getABI();
744   unsigned ADDU = ABI.GetPtrAdduOp();
745   unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP;
746   unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA;
747   unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9;
748   unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO;
749   unsigned OffsetReg = I->getOperand(0).getReg();
750   unsigned TargetReg = I->getOperand(1).getReg();
751 
752   // addu $ra, $v0, $zero
753   // addu $sp, $sp, $v1
754   // jr   $ra (via RetRA)
755   const TargetMachine &TM = MBB.getParent()->getTarget();
756   if (TM.isPositionIndependent())
757     BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9)
758         .addReg(TargetReg)
759         .addReg(ZERO);
760   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA)
761       .addReg(TargetReg)
762       .addReg(ZERO);
763   BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg);
764   expandRetRA(MBB, I);
765 }
766 
767 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) {
768   return new MipsSEInstrInfo(STI);
769 }
770