1 //===-- MipsSEInstrInfo.cpp - Mips32/64 Instruction Information -----------===// 2 // 3 // Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions. 4 // See https://llvm.org/LICENSE.txt for license information. 5 // SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception 6 // 7 //===----------------------------------------------------------------------===// 8 // 9 // This file contains the Mips32/64 implementation of the TargetInstrInfo class. 10 // 11 //===----------------------------------------------------------------------===// 12 13 #include "MipsSEInstrInfo.h" 14 #include "InstPrinter/MipsInstPrinter.h" 15 #include "MipsAnalyzeImmediate.h" 16 #include "MipsMachineFunction.h" 17 #include "MipsTargetMachine.h" 18 #include "llvm/ADT/STLExtras.h" 19 #include "llvm/CodeGen/MachineInstrBuilder.h" 20 #include "llvm/CodeGen/MachineRegisterInfo.h" 21 #include "llvm/Support/ErrorHandling.h" 22 #include "llvm/Support/MathExtras.h" 23 #include "llvm/Support/TargetRegistry.h" 24 25 using namespace llvm; 26 27 static unsigned getUnconditionalBranch(const MipsSubtarget &STI) { 28 if (STI.inMicroMipsMode()) 29 return STI.isPositionIndependent() ? Mips::B_MM : Mips::J_MM; 30 return STI.isPositionIndependent() ? Mips::B : Mips::J; 31 } 32 33 MipsSEInstrInfo::MipsSEInstrInfo(const MipsSubtarget &STI) 34 : MipsInstrInfo(STI, getUnconditionalBranch(STI)), RI() {} 35 36 const MipsRegisterInfo &MipsSEInstrInfo::getRegisterInfo() const { 37 return RI; 38 } 39 40 /// isLoadFromStackSlot - If the specified machine instruction is a direct 41 /// load from a stack slot, return the virtual or physical register number of 42 /// the destination along with the FrameIndex of the loaded stack slot. If 43 /// not, return 0. This predicate must return 0 if the instruction has 44 /// any side effects other than loading from the stack slot. 45 unsigned MipsSEInstrInfo::isLoadFromStackSlot(const MachineInstr &MI, 46 int &FrameIndex) const { 47 unsigned Opc = MI.getOpcode(); 48 49 if ((Opc == Mips::LW) || (Opc == Mips::LD) || 50 (Opc == Mips::LWC1) || (Opc == Mips::LDC1) || (Opc == Mips::LDC164)) { 51 if ((MI.getOperand(1).isFI()) && // is a stack slot 52 (MI.getOperand(2).isImm()) && // the imm is zero 53 (isZeroImm(MI.getOperand(2)))) { 54 FrameIndex = MI.getOperand(1).getIndex(); 55 return MI.getOperand(0).getReg(); 56 } 57 } 58 59 return 0; 60 } 61 62 /// isStoreToStackSlot - If the specified machine instruction is a direct 63 /// store to a stack slot, return the virtual or physical register number of 64 /// the source reg along with the FrameIndex of the loaded stack slot. If 65 /// not, return 0. This predicate must return 0 if the instruction has 66 /// any side effects other than storing to the stack slot. 67 unsigned MipsSEInstrInfo::isStoreToStackSlot(const MachineInstr &MI, 68 int &FrameIndex) const { 69 unsigned Opc = MI.getOpcode(); 70 71 if ((Opc == Mips::SW) || (Opc == Mips::SD) || 72 (Opc == Mips::SWC1) || (Opc == Mips::SDC1) || (Opc == Mips::SDC164)) { 73 if ((MI.getOperand(1).isFI()) && // is a stack slot 74 (MI.getOperand(2).isImm()) && // the imm is zero 75 (isZeroImm(MI.getOperand(2)))) { 76 FrameIndex = MI.getOperand(1).getIndex(); 77 return MI.getOperand(0).getReg(); 78 } 79 } 80 return 0; 81 } 82 83 void MipsSEInstrInfo::copyPhysReg(MachineBasicBlock &MBB, 84 MachineBasicBlock::iterator I, 85 const DebugLoc &DL, unsigned DestReg, 86 unsigned SrcReg, bool KillSrc) const { 87 unsigned Opc = 0, ZeroReg = 0; 88 bool isMicroMips = Subtarget.inMicroMipsMode(); 89 90 if (Mips::GPR32RegClass.contains(DestReg)) { // Copy to CPU Reg. 91 if (Mips::GPR32RegClass.contains(SrcReg)) { 92 if (isMicroMips) 93 Opc = Mips::MOVE16_MM; 94 else 95 Opc = Mips::OR, ZeroReg = Mips::ZERO; 96 } else if (Mips::CCRRegClass.contains(SrcReg)) 97 Opc = Mips::CFC1; 98 else if (Mips::FGR32RegClass.contains(SrcReg)) 99 Opc = Mips::MFC1; 100 else if (Mips::HI32RegClass.contains(SrcReg)) { 101 Opc = isMicroMips ? Mips::MFHI16_MM : Mips::MFHI; 102 SrcReg = 0; 103 } else if (Mips::LO32RegClass.contains(SrcReg)) { 104 Opc = isMicroMips ? Mips::MFLO16_MM : Mips::MFLO; 105 SrcReg = 0; 106 } else if (Mips::HI32DSPRegClass.contains(SrcReg)) 107 Opc = Mips::MFHI_DSP; 108 else if (Mips::LO32DSPRegClass.contains(SrcReg)) 109 Opc = Mips::MFLO_DSP; 110 else if (Mips::DSPCCRegClass.contains(SrcReg)) { 111 BuildMI(MBB, I, DL, get(Mips::RDDSP), DestReg).addImm(1 << 4) 112 .addReg(SrcReg, RegState::Implicit | getKillRegState(KillSrc)); 113 return; 114 } 115 else if (Mips::MSACtrlRegClass.contains(SrcReg)) 116 Opc = Mips::CFCMSA; 117 } 118 else if (Mips::GPR32RegClass.contains(SrcReg)) { // Copy from CPU Reg. 119 if (Mips::CCRRegClass.contains(DestReg)) 120 Opc = Mips::CTC1; 121 else if (Mips::FGR32RegClass.contains(DestReg)) 122 Opc = Mips::MTC1; 123 else if (Mips::HI32RegClass.contains(DestReg)) 124 Opc = Mips::MTHI, DestReg = 0; 125 else if (Mips::LO32RegClass.contains(DestReg)) 126 Opc = Mips::MTLO, DestReg = 0; 127 else if (Mips::HI32DSPRegClass.contains(DestReg)) 128 Opc = Mips::MTHI_DSP; 129 else if (Mips::LO32DSPRegClass.contains(DestReg)) 130 Opc = Mips::MTLO_DSP; 131 else if (Mips::DSPCCRegClass.contains(DestReg)) { 132 BuildMI(MBB, I, DL, get(Mips::WRDSP)) 133 .addReg(SrcReg, getKillRegState(KillSrc)).addImm(1 << 4) 134 .addReg(DestReg, RegState::ImplicitDefine); 135 return; 136 } else if (Mips::MSACtrlRegClass.contains(DestReg)) { 137 BuildMI(MBB, I, DL, get(Mips::CTCMSA)) 138 .addReg(DestReg) 139 .addReg(SrcReg, getKillRegState(KillSrc)); 140 return; 141 } 142 } 143 else if (Mips::FGR32RegClass.contains(DestReg, SrcReg)) 144 Opc = Mips::FMOV_S; 145 else if (Mips::AFGR64RegClass.contains(DestReg, SrcReg)) 146 Opc = Mips::FMOV_D32; 147 else if (Mips::FGR64RegClass.contains(DestReg, SrcReg)) 148 Opc = Mips::FMOV_D64; 149 else if (Mips::GPR64RegClass.contains(DestReg)) { // Copy to CPU64 Reg. 150 if (Mips::GPR64RegClass.contains(SrcReg)) 151 Opc = Mips::OR64, ZeroReg = Mips::ZERO_64; 152 else if (Mips::HI64RegClass.contains(SrcReg)) 153 Opc = Mips::MFHI64, SrcReg = 0; 154 else if (Mips::LO64RegClass.contains(SrcReg)) 155 Opc = Mips::MFLO64, SrcReg = 0; 156 else if (Mips::FGR64RegClass.contains(SrcReg)) 157 Opc = Mips::DMFC1; 158 } 159 else if (Mips::GPR64RegClass.contains(SrcReg)) { // Copy from CPU64 Reg. 160 if (Mips::HI64RegClass.contains(DestReg)) 161 Opc = Mips::MTHI64, DestReg = 0; 162 else if (Mips::LO64RegClass.contains(DestReg)) 163 Opc = Mips::MTLO64, DestReg = 0; 164 else if (Mips::FGR64RegClass.contains(DestReg)) 165 Opc = Mips::DMTC1; 166 } 167 else if (Mips::MSA128BRegClass.contains(DestReg)) { // Copy to MSA reg 168 if (Mips::MSA128BRegClass.contains(SrcReg)) 169 Opc = Mips::MOVE_V; 170 } 171 172 assert(Opc && "Cannot copy registers"); 173 174 MachineInstrBuilder MIB = BuildMI(MBB, I, DL, get(Opc)); 175 176 if (DestReg) 177 MIB.addReg(DestReg, RegState::Define); 178 179 if (SrcReg) 180 MIB.addReg(SrcReg, getKillRegState(KillSrc)); 181 182 if (ZeroReg) 183 MIB.addReg(ZeroReg); 184 } 185 186 static bool isORCopyInst(const MachineInstr &MI) { 187 switch (MI.getOpcode()) { 188 default: 189 break; 190 case Mips::OR_MM: 191 case Mips::OR: 192 if (MI.getOperand(2).getReg() == Mips::ZERO) 193 return true; 194 break; 195 case Mips::OR64: 196 if (MI.getOperand(2).getReg() == Mips::ZERO_64) 197 return true; 198 break; 199 } 200 return false; 201 } 202 203 /// If @MI is WRDSP/RRDSP instruction return true with @isWrite set to true 204 /// if it is WRDSP instruction. 205 static bool isReadOrWriteToDSPReg(const MachineInstr &MI, bool &isWrite) { 206 switch (MI.getOpcode()) { 207 default: 208 return false; 209 case Mips::WRDSP: 210 case Mips::WRDSP_MM: 211 isWrite = true; 212 break; 213 case Mips::RDDSP: 214 case Mips::RDDSP_MM: 215 isWrite = false; 216 break; 217 } 218 return true; 219 } 220 221 /// We check for the common case of 'or', as it's MIPS' preferred instruction 222 /// for GPRs but we have to check the operands to ensure that is the case. 223 /// Other move instructions for MIPS are directly identifiable. 224 bool MipsSEInstrInfo::isCopyInstrImpl(const MachineInstr &MI, 225 const MachineOperand *&Src, 226 const MachineOperand *&Dest) const { 227 bool isDSPControlWrite = false; 228 // Condition is made to match the creation of WRDSP/RDDSP copy instruction 229 // from copyPhysReg function. 230 if (isReadOrWriteToDSPReg(MI, isDSPControlWrite)) { 231 if (!MI.getOperand(1).isImm() || MI.getOperand(1).getImm() != (1<<4)) 232 return false; 233 else if (isDSPControlWrite) { 234 Src = &MI.getOperand(0); 235 Dest = &MI.getOperand(2); 236 } else { 237 Dest = &MI.getOperand(0); 238 Src = &MI.getOperand(2); 239 } 240 return true; 241 } else if (MI.isMoveReg() || isORCopyInst(MI)) { 242 Dest = &MI.getOperand(0); 243 Src = &MI.getOperand(1); 244 return true; 245 } 246 return false; 247 } 248 249 void MipsSEInstrInfo:: 250 storeRegToStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 251 unsigned SrcReg, bool isKill, int FI, 252 const TargetRegisterClass *RC, const TargetRegisterInfo *TRI, 253 int64_t Offset) const { 254 DebugLoc DL; 255 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOStore); 256 257 unsigned Opc = 0; 258 259 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 260 Opc = Mips::SW; 261 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 262 Opc = Mips::SD; 263 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 264 Opc = Mips::STORE_ACC64; 265 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 266 Opc = Mips::STORE_ACC64DSP; 267 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 268 Opc = Mips::STORE_ACC128; 269 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 270 Opc = Mips::STORE_CCOND_DSP; 271 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 272 Opc = Mips::SWC1; 273 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 274 Opc = Mips::SDC1; 275 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 276 Opc = Mips::SDC164; 277 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 278 Opc = Mips::ST_B; 279 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 280 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 281 Opc = Mips::ST_H; 282 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 283 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 284 Opc = Mips::ST_W; 285 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 286 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 287 Opc = Mips::ST_D; 288 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 289 Opc = Mips::SW; 290 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 291 Opc = Mips::SD; 292 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 293 Opc = Mips::SW; 294 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 295 Opc = Mips::SD; 296 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 297 Opc = Mips::SWDSP; 298 299 // Hi, Lo are normally caller save but they are callee save 300 // for interrupt handling. 301 const Function &Func = MBB.getParent()->getFunction(); 302 if (Func.hasFnAttribute("interrupt")) { 303 if (Mips::HI32RegClass.hasSubClassEq(RC)) { 304 BuildMI(MBB, I, DL, get(Mips::MFHI), Mips::K0); 305 SrcReg = Mips::K0; 306 } else if (Mips::HI64RegClass.hasSubClassEq(RC)) { 307 BuildMI(MBB, I, DL, get(Mips::MFHI64), Mips::K0_64); 308 SrcReg = Mips::K0_64; 309 } else if (Mips::LO32RegClass.hasSubClassEq(RC)) { 310 BuildMI(MBB, I, DL, get(Mips::MFLO), Mips::K0); 311 SrcReg = Mips::K0; 312 } else if (Mips::LO64RegClass.hasSubClassEq(RC)) { 313 BuildMI(MBB, I, DL, get(Mips::MFLO64), Mips::K0_64); 314 SrcReg = Mips::K0_64; 315 } 316 } 317 318 assert(Opc && "Register class not handled!"); 319 BuildMI(MBB, I, DL, get(Opc)).addReg(SrcReg, getKillRegState(isKill)) 320 .addFrameIndex(FI).addImm(Offset).addMemOperand(MMO); 321 } 322 323 void MipsSEInstrInfo:: 324 loadRegFromStack(MachineBasicBlock &MBB, MachineBasicBlock::iterator I, 325 unsigned DestReg, int FI, const TargetRegisterClass *RC, 326 const TargetRegisterInfo *TRI, int64_t Offset) const { 327 DebugLoc DL; 328 if (I != MBB.end()) DL = I->getDebugLoc(); 329 MachineMemOperand *MMO = GetMemOperand(MBB, FI, MachineMemOperand::MOLoad); 330 unsigned Opc = 0; 331 332 const Function &Func = MBB.getParent()->getFunction(); 333 bool ReqIndirectLoad = Func.hasFnAttribute("interrupt") && 334 (DestReg == Mips::LO0 || DestReg == Mips::LO0_64 || 335 DestReg == Mips::HI0 || DestReg == Mips::HI0_64); 336 337 if (Mips::GPR32RegClass.hasSubClassEq(RC)) 338 Opc = Mips::LW; 339 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) 340 Opc = Mips::LD; 341 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) 342 Opc = Mips::LOAD_ACC64; 343 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) 344 Opc = Mips::LOAD_ACC64DSP; 345 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) 346 Opc = Mips::LOAD_ACC128; 347 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) 348 Opc = Mips::LOAD_CCOND_DSP; 349 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) 350 Opc = Mips::LWC1; 351 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) 352 Opc = Mips::LDC1; 353 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) 354 Opc = Mips::LDC164; 355 else if (TRI->isTypeLegalForClass(*RC, MVT::v16i8)) 356 Opc = Mips::LD_B; 357 else if (TRI->isTypeLegalForClass(*RC, MVT::v8i16) || 358 TRI->isTypeLegalForClass(*RC, MVT::v8f16)) 359 Opc = Mips::LD_H; 360 else if (TRI->isTypeLegalForClass(*RC, MVT::v4i32) || 361 TRI->isTypeLegalForClass(*RC, MVT::v4f32)) 362 Opc = Mips::LD_W; 363 else if (TRI->isTypeLegalForClass(*RC, MVT::v2i64) || 364 TRI->isTypeLegalForClass(*RC, MVT::v2f64)) 365 Opc = Mips::LD_D; 366 else if (Mips::HI32RegClass.hasSubClassEq(RC)) 367 Opc = Mips::LW; 368 else if (Mips::HI64RegClass.hasSubClassEq(RC)) 369 Opc = Mips::LD; 370 else if (Mips::LO32RegClass.hasSubClassEq(RC)) 371 Opc = Mips::LW; 372 else if (Mips::LO64RegClass.hasSubClassEq(RC)) 373 Opc = Mips::LD; 374 else if (Mips::DSPRRegClass.hasSubClassEq(RC)) 375 Opc = Mips::LWDSP; 376 377 assert(Opc && "Register class not handled!"); 378 379 if (!ReqIndirectLoad) 380 BuildMI(MBB, I, DL, get(Opc), DestReg) 381 .addFrameIndex(FI) 382 .addImm(Offset) 383 .addMemOperand(MMO); 384 else { 385 // Load HI/LO through K0. Notably the DestReg is encoded into the 386 // instruction itself. 387 unsigned Reg = Mips::K0; 388 unsigned LdOp = Mips::MTLO; 389 if (DestReg == Mips::HI0) 390 LdOp = Mips::MTHI; 391 392 if (Subtarget.getABI().ArePtrs64bit()) { 393 Reg = Mips::K0_64; 394 if (DestReg == Mips::HI0_64) 395 LdOp = Mips::MTHI64; 396 else 397 LdOp = Mips::MTLO64; 398 } 399 400 BuildMI(MBB, I, DL, get(Opc), Reg) 401 .addFrameIndex(FI) 402 .addImm(Offset) 403 .addMemOperand(MMO); 404 BuildMI(MBB, I, DL, get(LdOp)).addReg(Reg); 405 } 406 } 407 408 bool MipsSEInstrInfo::expandPostRAPseudo(MachineInstr &MI) const { 409 MachineBasicBlock &MBB = *MI.getParent(); 410 bool isMicroMips = Subtarget.inMicroMipsMode(); 411 unsigned Opc; 412 413 switch (MI.getDesc().getOpcode()) { 414 default: 415 return false; 416 case Mips::RetRA: 417 expandRetRA(MBB, MI); 418 break; 419 case Mips::ERet: 420 expandERet(MBB, MI); 421 break; 422 case Mips::PseudoMFHI: 423 expandPseudoMFHiLo(MBB, MI, Mips::MFHI); 424 break; 425 case Mips::PseudoMFHI_MM: 426 expandPseudoMFHiLo(MBB, MI, Mips::MFHI16_MM); 427 break; 428 case Mips::PseudoMFLO: 429 expandPseudoMFHiLo(MBB, MI, Mips::MFLO); 430 break; 431 case Mips::PseudoMFLO_MM: 432 expandPseudoMFHiLo(MBB, MI, Mips::MFLO16_MM); 433 break; 434 case Mips::PseudoMFHI64: 435 expandPseudoMFHiLo(MBB, MI, Mips::MFHI64); 436 break; 437 case Mips::PseudoMFLO64: 438 expandPseudoMFHiLo(MBB, MI, Mips::MFLO64); 439 break; 440 case Mips::PseudoMTLOHI: 441 expandPseudoMTLoHi(MBB, MI, Mips::MTLO, Mips::MTHI, false); 442 break; 443 case Mips::PseudoMTLOHI64: 444 expandPseudoMTLoHi(MBB, MI, Mips::MTLO64, Mips::MTHI64, false); 445 break; 446 case Mips::PseudoMTLOHI_DSP: 447 expandPseudoMTLoHi(MBB, MI, Mips::MTLO_DSP, Mips::MTHI_DSP, true); 448 break; 449 case Mips::PseudoCVT_S_W: 450 expandCvtFPInt(MBB, MI, Mips::CVT_S_W, Mips::MTC1, false); 451 break; 452 case Mips::PseudoCVT_D32_W: 453 Opc = isMicroMips ? Mips::CVT_D32_W_MM : Mips::CVT_D32_W; 454 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, false); 455 break; 456 case Mips::PseudoCVT_S_L: 457 expandCvtFPInt(MBB, MI, Mips::CVT_S_L, Mips::DMTC1, true); 458 break; 459 case Mips::PseudoCVT_D64_W: 460 Opc = isMicroMips ? Mips::CVT_D64_W_MM : Mips::CVT_D64_W; 461 expandCvtFPInt(MBB, MI, Opc, Mips::MTC1, true); 462 break; 463 case Mips::PseudoCVT_D64_L: 464 expandCvtFPInt(MBB, MI, Mips::CVT_D64_L, Mips::DMTC1, true); 465 break; 466 case Mips::BuildPairF64: 467 expandBuildPairF64(MBB, MI, isMicroMips, false); 468 break; 469 case Mips::BuildPairF64_64: 470 expandBuildPairF64(MBB, MI, isMicroMips, true); 471 break; 472 case Mips::ExtractElementF64: 473 expandExtractElementF64(MBB, MI, isMicroMips, false); 474 break; 475 case Mips::ExtractElementF64_64: 476 expandExtractElementF64(MBB, MI, isMicroMips, true); 477 break; 478 case Mips::MIPSeh_return32: 479 case Mips::MIPSeh_return64: 480 expandEhReturn(MBB, MI); 481 break; 482 } 483 484 MBB.erase(MI); 485 return true; 486 } 487 488 /// getOppositeBranchOpc - Return the inverse of the specified 489 /// opcode, e.g. turning BEQ to BNE. 490 unsigned MipsSEInstrInfo::getOppositeBranchOpc(unsigned Opc) const { 491 switch (Opc) { 492 default: llvm_unreachable("Illegal opcode!"); 493 case Mips::BEQ: return Mips::BNE; 494 case Mips::BEQ_MM: return Mips::BNE_MM; 495 case Mips::BNE: return Mips::BEQ; 496 case Mips::BNE_MM: return Mips::BEQ_MM; 497 case Mips::BGTZ: return Mips::BLEZ; 498 case Mips::BGEZ: return Mips::BLTZ; 499 case Mips::BLTZ: return Mips::BGEZ; 500 case Mips::BLEZ: return Mips::BGTZ; 501 case Mips::BGTZ_MM: return Mips::BLEZ_MM; 502 case Mips::BGEZ_MM: return Mips::BLTZ_MM; 503 case Mips::BLTZ_MM: return Mips::BGEZ_MM; 504 case Mips::BLEZ_MM: return Mips::BGTZ_MM; 505 case Mips::BEQ64: return Mips::BNE64; 506 case Mips::BNE64: return Mips::BEQ64; 507 case Mips::BGTZ64: return Mips::BLEZ64; 508 case Mips::BGEZ64: return Mips::BLTZ64; 509 case Mips::BLTZ64: return Mips::BGEZ64; 510 case Mips::BLEZ64: return Mips::BGTZ64; 511 case Mips::BC1T: return Mips::BC1F; 512 case Mips::BC1F: return Mips::BC1T; 513 case Mips::BC1T_MM: return Mips::BC1F_MM; 514 case Mips::BC1F_MM: return Mips::BC1T_MM; 515 case Mips::BEQZ16_MM: return Mips::BNEZ16_MM; 516 case Mips::BNEZ16_MM: return Mips::BEQZ16_MM; 517 case Mips::BEQZC_MM: return Mips::BNEZC_MM; 518 case Mips::BNEZC_MM: return Mips::BEQZC_MM; 519 case Mips::BEQZC: return Mips::BNEZC; 520 case Mips::BNEZC: return Mips::BEQZC; 521 case Mips::BLEZC: return Mips::BGTZC; 522 case Mips::BGEZC: return Mips::BLTZC; 523 case Mips::BGEC: return Mips::BLTC; 524 case Mips::BGTZC: return Mips::BLEZC; 525 case Mips::BLTZC: return Mips::BGEZC; 526 case Mips::BLTC: return Mips::BGEC; 527 case Mips::BGEUC: return Mips::BLTUC; 528 case Mips::BLTUC: return Mips::BGEUC; 529 case Mips::BEQC: return Mips::BNEC; 530 case Mips::BNEC: return Mips::BEQC; 531 case Mips::BC1EQZ: return Mips::BC1NEZ; 532 case Mips::BC1NEZ: return Mips::BC1EQZ; 533 case Mips::BEQZC_MMR6: return Mips::BNEZC_MMR6; 534 case Mips::BNEZC_MMR6: return Mips::BEQZC_MMR6; 535 case Mips::BLEZC_MMR6: return Mips::BGTZC_MMR6; 536 case Mips::BGEZC_MMR6: return Mips::BLTZC_MMR6; 537 case Mips::BGEC_MMR6: return Mips::BLTC_MMR6; 538 case Mips::BGTZC_MMR6: return Mips::BLEZC_MMR6; 539 case Mips::BLTZC_MMR6: return Mips::BGEZC_MMR6; 540 case Mips::BLTC_MMR6: return Mips::BGEC_MMR6; 541 case Mips::BGEUC_MMR6: return Mips::BLTUC_MMR6; 542 case Mips::BLTUC_MMR6: return Mips::BGEUC_MMR6; 543 case Mips::BEQC_MMR6: return Mips::BNEC_MMR6; 544 case Mips::BNEC_MMR6: return Mips::BEQC_MMR6; 545 case Mips::BC1EQZC_MMR6: return Mips::BC1NEZC_MMR6; 546 case Mips::BC1NEZC_MMR6: return Mips::BC1EQZC_MMR6; 547 case Mips::BEQZC64: return Mips::BNEZC64; 548 case Mips::BNEZC64: return Mips::BEQZC64; 549 case Mips::BEQC64: return Mips::BNEC64; 550 case Mips::BNEC64: return Mips::BEQC64; 551 case Mips::BGEC64: return Mips::BLTC64; 552 case Mips::BGEUC64: return Mips::BLTUC64; 553 case Mips::BLTC64: return Mips::BGEC64; 554 case Mips::BLTUC64: return Mips::BGEUC64; 555 case Mips::BGTZC64: return Mips::BLEZC64; 556 case Mips::BGEZC64: return Mips::BLTZC64; 557 case Mips::BLTZC64: return Mips::BGEZC64; 558 case Mips::BLEZC64: return Mips::BGTZC64; 559 case Mips::BBIT0: return Mips::BBIT1; 560 case Mips::BBIT1: return Mips::BBIT0; 561 case Mips::BBIT032: return Mips::BBIT132; 562 case Mips::BBIT132: return Mips::BBIT032; 563 case Mips::BZ_B: return Mips::BNZ_B; 564 case Mips::BZ_H: return Mips::BNZ_H; 565 case Mips::BZ_W: return Mips::BNZ_W; 566 case Mips::BZ_D: return Mips::BNZ_D; 567 case Mips::BZ_V: return Mips::BNZ_V; 568 case Mips::BNZ_B: return Mips::BZ_B; 569 case Mips::BNZ_H: return Mips::BZ_H; 570 case Mips::BNZ_W: return Mips::BZ_W; 571 case Mips::BNZ_D: return Mips::BZ_D; 572 case Mips::BNZ_V: return Mips::BZ_V; 573 } 574 } 575 576 /// Adjust SP by Amount bytes. 577 void MipsSEInstrInfo::adjustStackPtr(unsigned SP, int64_t Amount, 578 MachineBasicBlock &MBB, 579 MachineBasicBlock::iterator I) const { 580 MipsABIInfo ABI = Subtarget.getABI(); 581 DebugLoc DL; 582 unsigned ADDiu = ABI.GetPtrAddiuOp(); 583 584 if (Amount == 0) 585 return; 586 587 if (isInt<16>(Amount)) { 588 // addi sp, sp, amount 589 BuildMI(MBB, I, DL, get(ADDiu), SP).addReg(SP).addImm(Amount); 590 } else { 591 // For numbers which are not 16bit integers we synthesize Amount inline 592 // then add or subtract it from sp. 593 unsigned Opc = ABI.GetPtrAdduOp(); 594 if (Amount < 0) { 595 Opc = ABI.GetPtrSubuOp(); 596 Amount = -Amount; 597 } 598 unsigned Reg = loadImmediate(Amount, MBB, I, DL, nullptr); 599 BuildMI(MBB, I, DL, get(Opc), SP).addReg(SP).addReg(Reg, RegState::Kill); 600 } 601 } 602 603 /// This function generates the sequence of instructions needed to get the 604 /// result of adding register REG and immediate IMM. 605 unsigned MipsSEInstrInfo::loadImmediate(int64_t Imm, MachineBasicBlock &MBB, 606 MachineBasicBlock::iterator II, 607 const DebugLoc &DL, 608 unsigned *NewImm) const { 609 MipsAnalyzeImmediate AnalyzeImm; 610 const MipsSubtarget &STI = Subtarget; 611 MachineRegisterInfo &RegInfo = MBB.getParent()->getRegInfo(); 612 unsigned Size = STI.isABI_N64() ? 64 : 32; 613 unsigned LUi = STI.isABI_N64() ? Mips::LUi64 : Mips::LUi; 614 unsigned ZEROReg = STI.isABI_N64() ? Mips::ZERO_64 : Mips::ZERO; 615 const TargetRegisterClass *RC = STI.isABI_N64() ? 616 &Mips::GPR64RegClass : &Mips::GPR32RegClass; 617 bool LastInstrIsADDiu = NewImm; 618 619 const MipsAnalyzeImmediate::InstSeq &Seq = 620 AnalyzeImm.Analyze(Imm, Size, LastInstrIsADDiu); 621 MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin(); 622 623 assert(Seq.size() && (!LastInstrIsADDiu || (Seq.size() > 1))); 624 625 // The first instruction can be a LUi, which is different from other 626 // instructions (ADDiu, ORI and SLL) in that it does not have a register 627 // operand. 628 unsigned Reg = RegInfo.createVirtualRegister(RC); 629 630 if (Inst->Opc == LUi) 631 BuildMI(MBB, II, DL, get(LUi), Reg).addImm(SignExtend64<16>(Inst->ImmOpnd)); 632 else 633 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(ZEROReg) 634 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 635 636 // Build the remaining instructions in Seq. 637 for (++Inst; Inst != Seq.end() - LastInstrIsADDiu; ++Inst) 638 BuildMI(MBB, II, DL, get(Inst->Opc), Reg).addReg(Reg, RegState::Kill) 639 .addImm(SignExtend64<16>(Inst->ImmOpnd)); 640 641 if (LastInstrIsADDiu) 642 *NewImm = Inst->ImmOpnd; 643 644 return Reg; 645 } 646 647 unsigned MipsSEInstrInfo::getAnalyzableBrOpc(unsigned Opc) const { 648 return (Opc == Mips::BEQ || Opc == Mips::BEQ_MM || Opc == Mips::BNE || 649 Opc == Mips::BNE_MM || Opc == Mips::BGTZ || Opc == Mips::BGEZ || 650 Opc == Mips::BLTZ || Opc == Mips::BLEZ || Opc == Mips::BEQ64 || 651 Opc == Mips::BNE64 || Opc == Mips::BGTZ64 || Opc == Mips::BGEZ64 || 652 Opc == Mips::BLTZ64 || Opc == Mips::BLEZ64 || Opc == Mips::BC1T || 653 Opc == Mips::BC1F || Opc == Mips::B || Opc == Mips::J || 654 Opc == Mips::J_MM || Opc == Mips::B_MM || Opc == Mips::BEQZC_MM || 655 Opc == Mips::BNEZC_MM || Opc == Mips::BEQC || Opc == Mips::BNEC || 656 Opc == Mips::BLTC || Opc == Mips::BGEC || Opc == Mips::BLTUC || 657 Opc == Mips::BGEUC || Opc == Mips::BGTZC || Opc == Mips::BLEZC || 658 Opc == Mips::BGEZC || Opc == Mips::BLTZC || Opc == Mips::BEQZC || 659 Opc == Mips::BNEZC || Opc == Mips::BEQZC64 || Opc == Mips::BNEZC64 || 660 Opc == Mips::BEQC64 || Opc == Mips::BNEC64 || Opc == Mips::BGEC64 || 661 Opc == Mips::BGEUC64 || Opc == Mips::BLTC64 || Opc == Mips::BLTUC64 || 662 Opc == Mips::BGTZC64 || Opc == Mips::BGEZC64 || 663 Opc == Mips::BLTZC64 || Opc == Mips::BLEZC64 || Opc == Mips::BC || 664 Opc == Mips::BBIT0 || Opc == Mips::BBIT1 || Opc == Mips::BBIT032 || 665 Opc == Mips::BBIT132 || Opc == Mips::BC_MMR6 || 666 Opc == Mips::BEQC_MMR6 || Opc == Mips::BNEC_MMR6 || 667 Opc == Mips::BLTC_MMR6 || Opc == Mips::BGEC_MMR6 || 668 Opc == Mips::BLTUC_MMR6 || Opc == Mips::BGEUC_MMR6 || 669 Opc == Mips::BGTZC_MMR6 || Opc == Mips::BLEZC_MMR6 || 670 Opc == Mips::BGEZC_MMR6 || Opc == Mips::BLTZC_MMR6 || 671 Opc == Mips::BEQZC_MMR6 || Opc == Mips::BNEZC_MMR6) ? Opc : 0; 672 } 673 674 void MipsSEInstrInfo::expandRetRA(MachineBasicBlock &MBB, 675 MachineBasicBlock::iterator I) const { 676 677 MachineInstrBuilder MIB; 678 if (Subtarget.isGP64bit()) 679 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn64)) 680 .addReg(Mips::RA_64, RegState::Undef); 681 else 682 MIB = BuildMI(MBB, I, I->getDebugLoc(), get(Mips::PseudoReturn)) 683 .addReg(Mips::RA, RegState::Undef); 684 685 // Retain any imp-use flags. 686 for (auto & MO : I->operands()) { 687 if (MO.isImplicit()) 688 MIB.add(MO); 689 } 690 } 691 692 void MipsSEInstrInfo::expandERet(MachineBasicBlock &MBB, 693 MachineBasicBlock::iterator I) const { 694 BuildMI(MBB, I, I->getDebugLoc(), get(Mips::ERET)); 695 } 696 697 std::pair<bool, bool> 698 MipsSEInstrInfo::compareOpndSize(unsigned Opc, 699 const MachineFunction &MF) const { 700 const MCInstrDesc &Desc = get(Opc); 701 assert(Desc.NumOperands == 2 && "Unary instruction expected."); 702 const MipsRegisterInfo *RI = &getRegisterInfo(); 703 unsigned DstRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 0, RI, MF)); 704 unsigned SrcRegSize = RI->getRegSizeInBits(*getRegClass(Desc, 1, RI, MF)); 705 706 return std::make_pair(DstRegSize > SrcRegSize, DstRegSize < SrcRegSize); 707 } 708 709 void MipsSEInstrInfo::expandPseudoMFHiLo(MachineBasicBlock &MBB, 710 MachineBasicBlock::iterator I, 711 unsigned NewOpc) const { 712 BuildMI(MBB, I, I->getDebugLoc(), get(NewOpc), I->getOperand(0).getReg()); 713 } 714 715 void MipsSEInstrInfo::expandPseudoMTLoHi(MachineBasicBlock &MBB, 716 MachineBasicBlock::iterator I, 717 unsigned LoOpc, 718 unsigned HiOpc, 719 bool HasExplicitDef) const { 720 // Expand 721 // lo_hi pseudomtlohi $gpr0, $gpr1 722 // to these two instructions: 723 // mtlo $gpr0 724 // mthi $gpr1 725 726 DebugLoc DL = I->getDebugLoc(); 727 const MachineOperand &SrcLo = I->getOperand(1), &SrcHi = I->getOperand(2); 728 MachineInstrBuilder LoInst = BuildMI(MBB, I, DL, get(LoOpc)); 729 MachineInstrBuilder HiInst = BuildMI(MBB, I, DL, get(HiOpc)); 730 731 // Add lo/hi registers if the mtlo/hi instructions created have explicit 732 // def registers. 733 if (HasExplicitDef) { 734 unsigned DstReg = I->getOperand(0).getReg(); 735 unsigned DstLo = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 736 unsigned DstHi = getRegisterInfo().getSubReg(DstReg, Mips::sub_hi); 737 LoInst.addReg(DstLo, RegState::Define); 738 HiInst.addReg(DstHi, RegState::Define); 739 } 740 741 LoInst.addReg(SrcLo.getReg(), getKillRegState(SrcLo.isKill())); 742 HiInst.addReg(SrcHi.getReg(), getKillRegState(SrcHi.isKill())); 743 } 744 745 void MipsSEInstrInfo::expandCvtFPInt(MachineBasicBlock &MBB, 746 MachineBasicBlock::iterator I, 747 unsigned CvtOpc, unsigned MovOpc, 748 bool IsI64) const { 749 const MCInstrDesc &CvtDesc = get(CvtOpc), &MovDesc = get(MovOpc); 750 const MachineOperand &Dst = I->getOperand(0), &Src = I->getOperand(1); 751 unsigned DstReg = Dst.getReg(), SrcReg = Src.getReg(), TmpReg = DstReg; 752 unsigned KillSrc = getKillRegState(Src.isKill()); 753 DebugLoc DL = I->getDebugLoc(); 754 bool DstIsLarger, SrcIsLarger; 755 756 std::tie(DstIsLarger, SrcIsLarger) = 757 compareOpndSize(CvtOpc, *MBB.getParent()); 758 759 if (DstIsLarger) 760 TmpReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 761 762 if (SrcIsLarger) 763 DstReg = getRegisterInfo().getSubReg(DstReg, Mips::sub_lo); 764 765 BuildMI(MBB, I, DL, MovDesc, TmpReg).addReg(SrcReg, KillSrc); 766 BuildMI(MBB, I, DL, CvtDesc, DstReg).addReg(TmpReg, RegState::Kill); 767 } 768 769 void MipsSEInstrInfo::expandExtractElementF64(MachineBasicBlock &MBB, 770 MachineBasicBlock::iterator I, 771 bool isMicroMips, 772 bool FP64) const { 773 unsigned DstReg = I->getOperand(0).getReg(); 774 unsigned SrcReg = I->getOperand(1).getReg(); 775 unsigned N = I->getOperand(2).getImm(); 776 DebugLoc dl = I->getDebugLoc(); 777 778 assert(N < 2 && "Invalid immediate"); 779 unsigned SubIdx = N ? Mips::sub_hi : Mips::sub_lo; 780 unsigned SubReg = getRegisterInfo().getSubReg(SrcReg, SubIdx); 781 782 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 783 // in MipsSEFrameLowering.cpp. 784 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 785 786 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 787 // in MipsSEFrameLowering.cpp. 788 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 789 790 if (SubIdx == Mips::sub_hi && Subtarget.hasMTHC1()) { 791 // FIXME: Strictly speaking MFHC1 only reads the top 32-bits however, we 792 // claim to read the whole 64-bits as part of a white lie used to 793 // temporarily work around a widespread bug in the -mfp64 support. 794 // The problem is that none of the 32-bit fpu ops mention the fact 795 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 796 // requires a major overhaul of the FPU implementation which can't 797 // be done right now due to time constraints. 798 // MFHC1 is one of two instructions that are affected since they are 799 // the only instructions that don't read the lower 32-bits. 800 // We therefore pretend that it reads the bottom 32-bits to 801 // artificially create a dependency and prevent the scheduler 802 // changing the behaviour of the code. 803 BuildMI(MBB, I, dl, 804 get(isMicroMips ? (FP64 ? Mips::MFHC1_D64_MM : Mips::MFHC1_D32_MM) 805 : (FP64 ? Mips::MFHC1_D64 : Mips::MFHC1_D32)), 806 DstReg) 807 .addReg(SrcReg); 808 } else 809 BuildMI(MBB, I, dl, get(Mips::MFC1), DstReg).addReg(SubReg); 810 } 811 812 void MipsSEInstrInfo::expandBuildPairF64(MachineBasicBlock &MBB, 813 MachineBasicBlock::iterator I, 814 bool isMicroMips, bool FP64) const { 815 unsigned DstReg = I->getOperand(0).getReg(); 816 unsigned LoReg = I->getOperand(1).getReg(), HiReg = I->getOperand(2).getReg(); 817 const MCInstrDesc& Mtc1Tdd = get(Mips::MTC1); 818 DebugLoc dl = I->getDebugLoc(); 819 const TargetRegisterInfo &TRI = getRegisterInfo(); 820 821 // When mthc1 is available, use: 822 // mtc1 Lo, $fp 823 // mthc1 Hi, $fp 824 // 825 // Otherwise, for O32 FPXX ABI: 826 // spill + reload via ldc1 827 // This case is handled by the frame lowering code. 828 // 829 // Otherwise, for FP32: 830 // mtc1 Lo, $fp 831 // mtc1 Hi, $fp + 1 832 // 833 // The case where dmtc1 is available doesn't need to be handled here 834 // because it never creates a BuildPairF64 node. 835 836 // FPXX on MIPS-II or MIPS32r1 should have been handled with a spill/reload 837 // in MipsSEFrameLowering.cpp. 838 assert(!(Subtarget.isABI_FPXX() && !Subtarget.hasMips32r2())); 839 840 // FP64A (FP64 with nooddspreg) should have been handled with a spill/reload 841 // in MipsSEFrameLowering.cpp. 842 assert(!(Subtarget.isFP64bit() && !Subtarget.useOddSPReg())); 843 844 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_lo)) 845 .addReg(LoReg); 846 847 if (Subtarget.hasMTHC1()) { 848 // FIXME: The .addReg(DstReg) is a white lie used to temporarily work 849 // around a widespread bug in the -mfp64 support. 850 // The problem is that none of the 32-bit fpu ops mention the fact 851 // that they clobber the upper 32-bits of the 64-bit FPR. Fixing that 852 // requires a major overhaul of the FPU implementation which can't 853 // be done right now due to time constraints. 854 // MTHC1 is one of two instructions that are affected since they are 855 // the only instructions that don't read the lower 32-bits. 856 // We therefore pretend that it reads the bottom 32-bits to 857 // artificially create a dependency and prevent the scheduler 858 // changing the behaviour of the code. 859 BuildMI(MBB, I, dl, 860 get(isMicroMips ? (FP64 ? Mips::MTHC1_D64_MM : Mips::MTHC1_D32_MM) 861 : (FP64 ? Mips::MTHC1_D64 : Mips::MTHC1_D32)), 862 DstReg) 863 .addReg(DstReg) 864 .addReg(HiReg); 865 } else if (Subtarget.isABI_FPXX()) 866 llvm_unreachable("BuildPairF64 not expanded in frame lowering code!"); 867 else 868 BuildMI(MBB, I, dl, Mtc1Tdd, TRI.getSubReg(DstReg, Mips::sub_hi)) 869 .addReg(HiReg); 870 } 871 872 void MipsSEInstrInfo::expandEhReturn(MachineBasicBlock &MBB, 873 MachineBasicBlock::iterator I) const { 874 // This pseudo instruction is generated as part of the lowering of 875 // ISD::EH_RETURN. We convert it to a stack increment by OffsetReg, and 876 // indirect jump to TargetReg 877 MipsABIInfo ABI = Subtarget.getABI(); 878 unsigned ADDU = ABI.GetPtrAdduOp(); 879 unsigned SP = Subtarget.isGP64bit() ? Mips::SP_64 : Mips::SP; 880 unsigned RA = Subtarget.isGP64bit() ? Mips::RA_64 : Mips::RA; 881 unsigned T9 = Subtarget.isGP64bit() ? Mips::T9_64 : Mips::T9; 882 unsigned ZERO = Subtarget.isGP64bit() ? Mips::ZERO_64 : Mips::ZERO; 883 unsigned OffsetReg = I->getOperand(0).getReg(); 884 unsigned TargetReg = I->getOperand(1).getReg(); 885 886 // addu $ra, $v0, $zero 887 // addu $sp, $sp, $v1 888 // jr $ra (via RetRA) 889 const TargetMachine &TM = MBB.getParent()->getTarget(); 890 if (TM.isPositionIndependent()) 891 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), T9) 892 .addReg(TargetReg) 893 .addReg(ZERO); 894 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), RA) 895 .addReg(TargetReg) 896 .addReg(ZERO); 897 BuildMI(MBB, I, I->getDebugLoc(), get(ADDU), SP).addReg(SP).addReg(OffsetReg); 898 expandRetRA(MBB, I); 899 } 900 901 const MipsInstrInfo *llvm::createMipsSEInstrInfo(const MipsSubtarget &STI) { 902 return new MipsSEInstrInfo(STI); 903 } 904