1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsTargetLowering specialized for mips32/64. 11 // 12 //===----------------------------------------------------------------------===// 13 #define DEBUG_TYPE "mips-isel" 14 #include "MipsSEISelLowering.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsTargetMachine.h" 17 #include "llvm/CodeGen/MachineInstrBuilder.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/IR/Intrinsics.h" 20 #include "llvm/Support/CommandLine.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include "llvm/Target/TargetInstrInfo.h" 24 25 using namespace llvm; 26 27 static cl::opt<bool> 28 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 29 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 30 31 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), 32 cl::desc("Expand double precision loads and " 33 "stores to their single precision " 34 "counterparts")); 35 36 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) 37 : MipsTargetLowering(TM) { 38 // Set up the register classes 39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 40 41 if (HasMips64) 42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); 43 44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) { 45 // Expand all truncating stores and extending loads. 46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 48 49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { 50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) 51 setTruncStoreAction((MVT::SimpleValueType)VT0, 52 (MVT::SimpleValueType)VT1, Expand); 53 54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); 57 } 58 } 59 60 if (Subtarget->hasDSP()) { 61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 62 63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); 65 66 // Expand all builtin opcodes. 67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 68 setOperationAction(Opc, VecTys[i], Expand); 69 70 setOperationAction(ISD::ADD, VecTys[i], Legal); 71 setOperationAction(ISD::SUB, VecTys[i], Legal); 72 setOperationAction(ISD::LOAD, VecTys[i], Legal); 73 setOperationAction(ISD::STORE, VecTys[i], Legal); 74 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 75 } 76 77 setTargetDAGCombine(ISD::SHL); 78 setTargetDAGCombine(ISD::SRA); 79 setTargetDAGCombine(ISD::SRL); 80 setTargetDAGCombine(ISD::SETCC); 81 setTargetDAGCombine(ISD::VSELECT); 82 } 83 84 if (Subtarget->hasDSPR2()) 85 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 86 87 if (Subtarget->hasMSA()) { 88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); 92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); 93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); 94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); 95 96 setTargetDAGCombine(ISD::AND); 97 setTargetDAGCombine(ISD::OR); 98 setTargetDAGCombine(ISD::SRA); 99 setTargetDAGCombine(ISD::VSELECT); 100 setTargetDAGCombine(ISD::XOR); 101 } 102 103 if (!Subtarget->mipsSEUsesSoftFloat()) { 104 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 105 106 // When dealing with single precision only, use libcalls 107 if (!Subtarget->isSingleFloat()) { 108 if (Subtarget->isFP64bit()) 109 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 110 else 111 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 112 } 113 } 114 115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 117 setOperationAction(ISD::MULHS, MVT::i32, Custom); 118 setOperationAction(ISD::MULHU, MVT::i32, Custom); 119 120 if (HasMips64) { 121 setOperationAction(ISD::MULHS, MVT::i64, Custom); 122 setOperationAction(ISD::MULHU, MVT::i64, Custom); 123 setOperationAction(ISD::MUL, MVT::i64, Custom); 124 } 125 126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 127 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 128 129 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 130 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 131 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 132 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 134 setOperationAction(ISD::LOAD, MVT::i32, Custom); 135 setOperationAction(ISD::STORE, MVT::i32, Custom); 136 137 setTargetDAGCombine(ISD::ADDE); 138 setTargetDAGCombine(ISD::SUBE); 139 setTargetDAGCombine(ISD::MUL); 140 141 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 142 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 143 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 144 145 if (NoDPLoadStore) { 146 setOperationAction(ISD::LOAD, MVT::f64, Custom); 147 setOperationAction(ISD::STORE, MVT::f64, Custom); 148 } 149 150 computeRegisterProperties(); 151 } 152 153 const MipsTargetLowering * 154 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { 155 return new MipsSETargetLowering(TM); 156 } 157 158 // Enable MSA support for the given integer type and Register class. 159 void MipsSETargetLowering:: 160 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 161 addRegisterClass(Ty, RC); 162 163 // Expand all builtin opcodes. 164 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 165 setOperationAction(Opc, Ty, Expand); 166 167 setOperationAction(ISD::BITCAST, Ty, Legal); 168 setOperationAction(ISD::LOAD, Ty, Legal); 169 setOperationAction(ISD::STORE, Ty, Legal); 170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 171 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 172 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 173 174 setOperationAction(ISD::ADD, Ty, Legal); 175 setOperationAction(ISD::AND, Ty, Legal); 176 setOperationAction(ISD::CTLZ, Ty, Legal); 177 setOperationAction(ISD::CTPOP, Ty, Legal); 178 setOperationAction(ISD::MUL, Ty, Legal); 179 setOperationAction(ISD::OR, Ty, Legal); 180 setOperationAction(ISD::SDIV, Ty, Legal); 181 setOperationAction(ISD::SREM, Ty, Legal); 182 setOperationAction(ISD::SHL, Ty, Legal); 183 setOperationAction(ISD::SRA, Ty, Legal); 184 setOperationAction(ISD::SRL, Ty, Legal); 185 setOperationAction(ISD::SUB, Ty, Legal); 186 setOperationAction(ISD::UDIV, Ty, Legal); 187 setOperationAction(ISD::UREM, Ty, Legal); 188 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 189 setOperationAction(ISD::VSELECT, Ty, Legal); 190 setOperationAction(ISD::XOR, Ty, Legal); 191 192 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 193 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); 194 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); 195 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 196 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); 197 } 198 199 setOperationAction(ISD::SETCC, Ty, Legal); 200 setCondCodeAction(ISD::SETNE, Ty, Expand); 201 setCondCodeAction(ISD::SETGE, Ty, Expand); 202 setCondCodeAction(ISD::SETGT, Ty, Expand); 203 setCondCodeAction(ISD::SETUGE, Ty, Expand); 204 setCondCodeAction(ISD::SETUGT, Ty, Expand); 205 } 206 207 // Enable MSA support for the given floating-point type and Register class. 208 void MipsSETargetLowering:: 209 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 210 addRegisterClass(Ty, RC); 211 212 // Expand all builtin opcodes. 213 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 214 setOperationAction(Opc, Ty, Expand); 215 216 setOperationAction(ISD::LOAD, Ty, Legal); 217 setOperationAction(ISD::STORE, Ty, Legal); 218 setOperationAction(ISD::BITCAST, Ty, Legal); 219 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 220 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 221 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 222 223 if (Ty != MVT::v8f16) { 224 setOperationAction(ISD::FABS, Ty, Legal); 225 setOperationAction(ISD::FADD, Ty, Legal); 226 setOperationAction(ISD::FDIV, Ty, Legal); 227 setOperationAction(ISD::FEXP2, Ty, Legal); 228 setOperationAction(ISD::FLOG2, Ty, Legal); 229 setOperationAction(ISD::FMA, Ty, Legal); 230 setOperationAction(ISD::FMUL, Ty, Legal); 231 setOperationAction(ISD::FRINT, Ty, Legal); 232 setOperationAction(ISD::FSQRT, Ty, Legal); 233 setOperationAction(ISD::FSUB, Ty, Legal); 234 setOperationAction(ISD::VSELECT, Ty, Legal); 235 236 setOperationAction(ISD::SETCC, Ty, Legal); 237 setCondCodeAction(ISD::SETOGE, Ty, Expand); 238 setCondCodeAction(ISD::SETOGT, Ty, Expand); 239 setCondCodeAction(ISD::SETUGE, Ty, Expand); 240 setCondCodeAction(ISD::SETUGT, Ty, Expand); 241 setCondCodeAction(ISD::SETGE, Ty, Expand); 242 setCondCodeAction(ISD::SETGT, Ty, Expand); 243 } 244 } 245 246 bool 247 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, 248 unsigned, 249 bool *Fast) const { 250 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 251 252 switch (SVT) { 253 case MVT::i64: 254 case MVT::i32: 255 if (Fast) 256 *Fast = true; 257 return true; 258 default: 259 return false; 260 } 261 } 262 263 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, 264 SelectionDAG &DAG) const { 265 switch(Op.getOpcode()) { 266 case ISD::LOAD: return lowerLOAD(Op, DAG); 267 case ISD::STORE: return lowerSTORE(Op, DAG); 268 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 269 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 270 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 271 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 272 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 273 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 274 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, 275 DAG); 276 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 277 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); 278 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); 279 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 280 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); 281 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 282 } 283 284 return MipsTargetLowering::LowerOperation(Op, DAG); 285 } 286 287 // selectMADD - 288 // Transforms a subgraph in CurDAG if the following pattern is found: 289 // (addc multLo, Lo0), (adde multHi, Hi0), 290 // where, 291 // multHi/Lo: product of multiplication 292 // Lo0: initial value of Lo register 293 // Hi0: initial value of Hi register 294 // Return true if pattern matching was successful. 295 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) { 296 // ADDENode's second operand must be a flag output of an ADDC node in order 297 // for the matching to be successful. 298 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 299 300 if (ADDCNode->getOpcode() != ISD::ADDC) 301 return false; 302 303 SDValue MultHi = ADDENode->getOperand(0); 304 SDValue MultLo = ADDCNode->getOperand(0); 305 SDNode *MultNode = MultHi.getNode(); 306 unsigned MultOpc = MultHi.getOpcode(); 307 308 // MultHi and MultLo must be generated by the same node, 309 if (MultLo.getNode() != MultNode) 310 return false; 311 312 // and it must be a multiplication. 313 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 314 return false; 315 316 // MultLo amd MultHi must be the first and second output of MultNode 317 // respectively. 318 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 319 return false; 320 321 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 322 // of the values of MultNode, in which case MultNode will be removed in later 323 // phases. 324 // If there exist users other than ADDENode or ADDCNode, this function returns 325 // here, which will result in MultNode being mapped to a single MULT 326 // instruction node rather than a pair of MULT and MADD instructions being 327 // produced. 328 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 329 return false; 330 331 SDLoc DL(ADDENode); 332 333 // Initialize accumulator. 334 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 335 ADDCNode->getOperand(1), 336 ADDENode->getOperand(1)); 337 338 // create MipsMAdd(u) node 339 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 340 341 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, 342 MultNode->getOperand(0),// Factor 0 343 MultNode->getOperand(1),// Factor 1 344 ACCIn); 345 346 // replace uses of adde and addc here 347 if (!SDValue(ADDCNode, 0).use_empty()) { 348 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 349 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut); 350 } 351 if (!SDValue(ADDENode, 0).use_empty()) { 352 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 353 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut); 354 } 355 356 return true; 357 } 358 359 // selectMSUB - 360 // Transforms a subgraph in CurDAG if the following pattern is found: 361 // (addc Lo0, multLo), (sube Hi0, multHi), 362 // where, 363 // multHi/Lo: product of multiplication 364 // Lo0: initial value of Lo register 365 // Hi0: initial value of Hi register 366 // Return true if pattern matching was successful. 367 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { 368 // SUBENode's second operand must be a flag output of an SUBC node in order 369 // for the matching to be successful. 370 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 371 372 if (SUBCNode->getOpcode() != ISD::SUBC) 373 return false; 374 375 SDValue MultHi = SUBENode->getOperand(1); 376 SDValue MultLo = SUBCNode->getOperand(1); 377 SDNode *MultNode = MultHi.getNode(); 378 unsigned MultOpc = MultHi.getOpcode(); 379 380 // MultHi and MultLo must be generated by the same node, 381 if (MultLo.getNode() != MultNode) 382 return false; 383 384 // and it must be a multiplication. 385 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 386 return false; 387 388 // MultLo amd MultHi must be the first and second output of MultNode 389 // respectively. 390 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 391 return false; 392 393 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 394 // of the values of MultNode, in which case MultNode will be removed in later 395 // phases. 396 // If there exist users other than SUBENode or SUBCNode, this function returns 397 // here, which will result in MultNode being mapped to a single MULT 398 // instruction node rather than a pair of MULT and MSUB instructions being 399 // produced. 400 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 401 return false; 402 403 SDLoc DL(SUBENode); 404 405 // Initialize accumulator. 406 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 407 SUBCNode->getOperand(0), 408 SUBENode->getOperand(0)); 409 410 // create MipsSub(u) node 411 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 412 413 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, 414 MultNode->getOperand(0),// Factor 0 415 MultNode->getOperand(1),// Factor 1 416 ACCIn); 417 418 // replace uses of sube and subc here 419 if (!SDValue(SUBCNode, 0).use_empty()) { 420 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); 421 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut); 422 } 423 if (!SDValue(SUBENode, 0).use_empty()) { 424 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); 425 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut); 426 } 427 428 return true; 429 } 430 431 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, 432 TargetLowering::DAGCombinerInfo &DCI, 433 const MipsSubtarget *Subtarget) { 434 if (DCI.isBeforeLegalize()) 435 return SDValue(); 436 437 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 438 selectMADD(N, &DAG)) 439 return SDValue(N, 0); 440 441 return SDValue(); 442 } 443 444 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT 445 // 446 // Performs the following transformations: 447 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its 448 // sign/zero-extension is completely overwritten by the new one performed by 449 // the ISD::AND. 450 // - Removes redundant zero extensions performed by an ISD::AND. 451 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 452 TargetLowering::DAGCombinerInfo &DCI, 453 const MipsSubtarget *Subtarget) { 454 if (!Subtarget->hasMSA()) 455 return SDValue(); 456 457 SDValue Op0 = N->getOperand(0); 458 SDValue Op1 = N->getOperand(1); 459 unsigned Op0Opcode = Op0->getOpcode(); 460 461 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d) 462 // where $d + 1 == 2^n and n == 32 463 // or $d + 1 == 2^n and n <= 32 and ZExt 464 // -> (MipsVExtractZExt $a, $b, $c) 465 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT || 466 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) { 467 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); 468 469 if (!Mask) 470 return SDValue(); 471 472 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 473 474 if (Log2IfPositive <= 0) 475 return SDValue(); // Mask+1 is not a power of 2 476 477 SDValue Op0Op2 = Op0->getOperand(2); 478 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); 479 unsigned ExtendTySize = ExtendTy.getSizeInBits(); 480 unsigned Log2 = Log2IfPositive; 481 482 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || 483 Log2 == ExtendTySize) { 484 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 485 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, 486 Op0->getVTList(), Ops, Op0->getNumOperands()); 487 return Op0; 488 } 489 } 490 491 return SDValue(); 492 } 493 494 // Determine if the specified node is a constant vector splat. 495 // 496 // Returns true and sets Imm if: 497 // * N is a ISD::BUILD_VECTOR representing a constant splat 498 // 499 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The 500 // differences are that it assumes the MSA has already been checked and the 501 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and 502 // must not be in order for binsri.d to be selectable). 503 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) { 504 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode()); 505 506 if (Node == NULL) 507 return false; 508 509 APInt SplatValue, SplatUndef; 510 unsigned SplatBitSize; 511 bool HasAnyUndefs; 512 513 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 514 8, !IsLittleEndian)) 515 return false; 516 517 Imm = SplatValue; 518 519 return true; 520 } 521 522 // Test whether the given node is an all-ones build_vector. 523 static bool isVectorAllOnes(SDValue N) { 524 // Look through bitcasts. Endianness doesn't matter because we are looking 525 // for an all-ones value. 526 if (N->getOpcode() == ISD::BITCAST) 527 N = N->getOperand(0); 528 529 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N); 530 531 if (!BVN) 532 return false; 533 534 APInt SplatValue, SplatUndef; 535 unsigned SplatBitSize; 536 bool HasAnyUndefs; 537 538 // Endianness doesn't matter in this context because we are looking for 539 // an all-ones value. 540 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs)) 541 return SplatValue.isAllOnesValue(); 542 543 return false; 544 } 545 546 // Test whether N is the bitwise inverse of OfNode. 547 static bool isBitwiseInverse(SDValue N, SDValue OfNode) { 548 if (N->getOpcode() != ISD::XOR) 549 return false; 550 551 if (isVectorAllOnes(N->getOperand(0))) 552 return N->getOperand(1) == OfNode; 553 554 if (isVectorAllOnes(N->getOperand(1))) 555 return N->getOperand(0) == OfNode; 556 557 return false; 558 } 559 560 // Perform combines where ISD::OR is the root node. 561 // 562 // Performs the following transformations: 563 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b) 564 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit 565 // vector type. 566 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 567 TargetLowering::DAGCombinerInfo &DCI, 568 const MipsSubtarget *Subtarget) { 569 if (!Subtarget->hasMSA()) 570 return SDValue(); 571 572 EVT Ty = N->getValueType(0); 573 574 if (!Ty.is128BitVector()) 575 return SDValue(); 576 577 SDValue Op0 = N->getOperand(0); 578 SDValue Op1 = N->getOperand(1); 579 580 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) { 581 SDValue Op0Op0 = Op0->getOperand(0); 582 SDValue Op0Op1 = Op0->getOperand(1); 583 SDValue Op1Op0 = Op1->getOperand(0); 584 SDValue Op1Op1 = Op1->getOperand(1); 585 bool IsLittleEndian = !Subtarget->isLittle(); 586 587 SDValue IfSet, IfClr, Cond; 588 bool IsConstantMask = false; 589 APInt Mask, InvMask; 590 591 // If Op0Op0 is an appropriate mask, try to find it's inverse in either 592 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while 593 // looking. 594 // IfClr will be set if we find a valid match. 595 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) { 596 Cond = Op0Op0; 597 IfSet = Op0Op1; 598 599 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && 600 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 601 IfClr = Op1Op1; 602 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && 603 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 604 IfClr = Op1Op0; 605 606 IsConstantMask = true; 607 } 608 609 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same 610 // thing again using this mask. 611 // IfClr will be set if we find a valid match. 612 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) { 613 Cond = Op0Op1; 614 IfSet = Op0Op0; 615 616 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && 617 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 618 IfClr = Op1Op1; 619 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && 620 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 621 IfClr = Op1Op0; 622 623 IsConstantMask = true; 624 } 625 626 // If IfClr is not yet set, try looking for a non-constant match. 627 // IfClr will be set if we find a valid match amongst the eight 628 // possibilities. 629 if (!IfClr.getNode()) { 630 if (isBitwiseInverse(Op0Op0, Op1Op0)) { 631 Cond = Op1Op0; 632 IfSet = Op1Op1; 633 IfClr = Op0Op1; 634 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) { 635 Cond = Op1Op0; 636 IfSet = Op1Op1; 637 IfClr = Op0Op0; 638 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) { 639 Cond = Op1Op1; 640 IfSet = Op1Op0; 641 IfClr = Op0Op1; 642 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) { 643 Cond = Op1Op1; 644 IfSet = Op1Op0; 645 IfClr = Op0Op0; 646 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) { 647 Cond = Op0Op0; 648 IfSet = Op0Op1; 649 IfClr = Op1Op1; 650 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) { 651 Cond = Op0Op0; 652 IfSet = Op0Op1; 653 IfClr = Op1Op0; 654 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) { 655 Cond = Op0Op1; 656 IfSet = Op0Op0; 657 IfClr = Op1Op1; 658 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) { 659 Cond = Op0Op1; 660 IfSet = Op0Op0; 661 IfClr = Op1Op0; 662 } 663 } 664 665 // At this point, IfClr will be set if we have a valid match. 666 if (!IfClr.getNode()) 667 return SDValue(); 668 669 assert(Cond.getNode() && IfSet.getNode()); 670 671 // Fold degenerate cases. 672 if (IsConstantMask) { 673 if (Mask.isAllOnesValue()) 674 return IfSet; 675 else if (Mask == 0) 676 return IfClr; 677 } 678 679 // Transform the DAG into an equivalent VSELECT. 680 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet); 681 } 682 683 return SDValue(); 684 } 685 686 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, 687 TargetLowering::DAGCombinerInfo &DCI, 688 const MipsSubtarget *Subtarget) { 689 if (DCI.isBeforeLegalize()) 690 return SDValue(); 691 692 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 693 selectMSUB(N, &DAG)) 694 return SDValue(N, 0); 695 696 return SDValue(); 697 } 698 699 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, 700 EVT ShiftTy, SelectionDAG &DAG) { 701 // Clear the upper (64 - VT.sizeInBits) bits. 702 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits()); 703 704 // Return 0. 705 if (C == 0) 706 return DAG.getConstant(0, VT); 707 708 // Return x. 709 if (C == 1) 710 return X; 711 712 // If c is power of 2, return (shl x, log2(c)). 713 if (isPowerOf2_64(C)) 714 return DAG.getNode(ISD::SHL, DL, VT, X, 715 DAG.getConstant(Log2_64(C), ShiftTy)); 716 717 unsigned Log2Ceil = Log2_64_Ceil(C); 718 uint64_t Floor = 1LL << Log2_64(C); 719 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil; 720 721 // If |c - floor_c| <= |c - ceil_c|, 722 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))), 723 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). 724 if (C - Floor <= Ceil - C) { 725 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 726 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 727 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 728 } 729 730 // If |c - floor_c| > |c - ceil_c|, 731 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). 732 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 733 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 734 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); 735 } 736 737 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, 738 const TargetLowering::DAGCombinerInfo &DCI, 739 const MipsSETargetLowering *TL) { 740 EVT VT = N->getValueType(0); 741 742 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 743 if (!VT.isVector()) 744 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), 745 VT, TL->getScalarShiftAmountTy(VT), DAG); 746 747 return SDValue(N, 0); 748 } 749 750 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, 751 SelectionDAG &DAG, 752 const MipsSubtarget *Subtarget) { 753 // See if this is a vector splat immediate node. 754 APInt SplatValue, SplatUndef; 755 unsigned SplatBitSize; 756 bool HasAnyUndefs; 757 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); 758 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 759 760 if (!Subtarget->hasDSP()) 761 return SDValue(); 762 763 if (!BV || 764 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 765 EltSize, !Subtarget->isLittle()) || 766 (SplatBitSize != EltSize) || 767 (SplatValue.getZExtValue() >= EltSize)) 768 return SDValue(); 769 770 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0), 771 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32)); 772 } 773 774 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 775 TargetLowering::DAGCombinerInfo &DCI, 776 const MipsSubtarget *Subtarget) { 777 EVT Ty = N->getValueType(0); 778 779 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 780 return SDValue(); 781 782 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); 783 } 784 785 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold 786 // constant splats into MipsISD::SHRA_DSP for DSPr2. 787 // 788 // Performs the following transformations: 789 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its 790 // sign/zero-extension is completely overwritten by the new one performed by 791 // the ISD::SRA and ISD::SHL nodes. 792 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 793 // sequence. 794 // 795 // See performDSPShiftCombine for more information about the transformation 796 // used for DSPr2. 797 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, 798 TargetLowering::DAGCombinerInfo &DCI, 799 const MipsSubtarget *Subtarget) { 800 EVT Ty = N->getValueType(0); 801 802 if (Subtarget->hasMSA()) { 803 SDValue Op0 = N->getOperand(0); 804 SDValue Op1 = N->getOperand(1); 805 806 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d) 807 // where $d + sizeof($c) == 32 808 // or $d + sizeof($c) <= 32 and SExt 809 // -> (MipsVExtractSExt $a, $b, $c) 810 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 811 SDValue Op0Op0 = Op0->getOperand(0); 812 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1); 813 814 if (!ShAmount) 815 return SDValue(); 816 817 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && 818 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) 819 return SDValue(); 820 821 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); 822 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); 823 824 if (TotalBits == 32 || 825 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && 826 TotalBits <= 32)) { 827 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), 828 Op0Op0->getOperand(2) }; 829 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, 830 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands()); 831 return Op0Op0; 832 } 833 } 834 } 835 836 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) 837 return SDValue(); 838 839 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); 840 } 841 842 843 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, 844 TargetLowering::DAGCombinerInfo &DCI, 845 const MipsSubtarget *Subtarget) { 846 EVT Ty = N->getValueType(0); 847 848 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) 849 return SDValue(); 850 851 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); 852 } 853 854 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { 855 bool IsV216 = (Ty == MVT::v2i16); 856 857 switch (CC) { 858 case ISD::SETEQ: 859 case ISD::SETNE: return true; 860 case ISD::SETLT: 861 case ISD::SETLE: 862 case ISD::SETGT: 863 case ISD::SETGE: return IsV216; 864 case ISD::SETULT: 865 case ISD::SETULE: 866 case ISD::SETUGT: 867 case ISD::SETUGE: return !IsV216; 868 default: return false; 869 } 870 } 871 872 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { 873 EVT Ty = N->getValueType(0); 874 875 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 876 return SDValue(); 877 878 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) 879 return SDValue(); 880 881 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), 882 N->getOperand(1), N->getOperand(2)); 883 } 884 885 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { 886 EVT Ty = N->getValueType(0); 887 888 if (Ty.is128BitVector() && Ty.isInteger()) { 889 // Try the following combines: 890 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 891 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) 892 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 893 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) 894 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 895 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) 896 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 897 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) 898 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but 899 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 900 // legalizer. 901 SDValue Op0 = N->getOperand(0); 902 903 if (Op0->getOpcode() != ISD::SETCC) 904 return SDValue(); 905 906 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); 907 bool Signed; 908 909 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 910 Signed = true; 911 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 912 Signed = false; 913 else 914 return SDValue(); 915 916 SDValue Op1 = N->getOperand(1); 917 SDValue Op2 = N->getOperand(2); 918 SDValue Op0Op0 = Op0->getOperand(0); 919 SDValue Op0Op1 = Op0->getOperand(1); 920 921 if (Op1 == Op0Op0 && Op2 == Op0Op1) 922 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), 923 Ty, Op1, Op2); 924 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 925 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), 926 Ty, Op1, Op2); 927 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { 928 SDValue SetCC = N->getOperand(0); 929 930 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 931 return SDValue(); 932 933 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty, 934 SetCC.getOperand(0), SetCC.getOperand(1), 935 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); 936 } 937 938 return SDValue(); 939 } 940 941 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, 942 const MipsSubtarget *Subtarget) { 943 EVT Ty = N->getValueType(0); 944 945 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { 946 // Try the following combines: 947 // (xor (or $a, $b), (build_vector allones)) 948 // (xor (or $a, $b), (bitcast (build_vector allones))) 949 SDValue Op0 = N->getOperand(0); 950 SDValue Op1 = N->getOperand(1); 951 SDValue NotOp; 952 953 if (ISD::isBuildVectorAllOnes(Op0.getNode())) 954 NotOp = Op1; 955 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) 956 NotOp = Op0; 957 else 958 return SDValue(); 959 960 if (NotOp->getOpcode() == ISD::OR) 961 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), 962 NotOp->getOperand(1)); 963 } 964 965 return SDValue(); 966 } 967 968 SDValue 969 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 970 SelectionDAG &DAG = DCI.DAG; 971 SDValue Val; 972 973 switch (N->getOpcode()) { 974 case ISD::ADDE: 975 return performADDECombine(N, DAG, DCI, Subtarget); 976 case ISD::AND: 977 Val = performANDCombine(N, DAG, DCI, Subtarget); 978 break; 979 case ISD::OR: 980 Val = performORCombine(N, DAG, DCI, Subtarget); 981 break; 982 case ISD::SUBE: 983 return performSUBECombine(N, DAG, DCI, Subtarget); 984 case ISD::MUL: 985 return performMULCombine(N, DAG, DCI, this); 986 case ISD::SHL: 987 return performSHLCombine(N, DAG, DCI, Subtarget); 988 case ISD::SRA: 989 return performSRACombine(N, DAG, DCI, Subtarget); 990 case ISD::SRL: 991 return performSRLCombine(N, DAG, DCI, Subtarget); 992 case ISD::VSELECT: 993 return performVSELECTCombine(N, DAG); 994 case ISD::XOR: 995 Val = performXORCombine(N, DAG, Subtarget); 996 break; 997 case ISD::SETCC: 998 Val = performSETCCCombine(N, DAG); 999 break; 1000 } 1001 1002 if (Val.getNode()) { 1003 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; 1004 N->printrWithDepth(dbgs(), &DAG); 1005 dbgs() << "\n=> \n"; 1006 Val.getNode()->printrWithDepth(dbgs(), &DAG); 1007 dbgs() << "\n"); 1008 return Val; 1009 } 1010 1011 return MipsTargetLowering::PerformDAGCombine(N, DCI); 1012 } 1013 1014 MachineBasicBlock * 1015 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1016 MachineBasicBlock *BB) const { 1017 switch (MI->getOpcode()) { 1018 default: 1019 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 1020 case Mips::BPOSGE32_PSEUDO: 1021 return emitBPOSGE32(MI, BB); 1022 case Mips::SNZ_B_PSEUDO: 1023 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B); 1024 case Mips::SNZ_H_PSEUDO: 1025 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H); 1026 case Mips::SNZ_W_PSEUDO: 1027 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W); 1028 case Mips::SNZ_D_PSEUDO: 1029 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D); 1030 case Mips::SNZ_V_PSEUDO: 1031 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V); 1032 case Mips::SZ_B_PSEUDO: 1033 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); 1034 case Mips::SZ_H_PSEUDO: 1035 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); 1036 case Mips::SZ_W_PSEUDO: 1037 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W); 1038 case Mips::SZ_D_PSEUDO: 1039 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D); 1040 case Mips::SZ_V_PSEUDO: 1041 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V); 1042 case Mips::COPY_FW_PSEUDO: 1043 return emitCOPY_FW(MI, BB); 1044 case Mips::COPY_FD_PSEUDO: 1045 return emitCOPY_FD(MI, BB); 1046 case Mips::INSERT_FW_PSEUDO: 1047 return emitINSERT_FW(MI, BB); 1048 case Mips::INSERT_FD_PSEUDO: 1049 return emitINSERT_FD(MI, BB); 1050 case Mips::FILL_FW_PSEUDO: 1051 return emitFILL_FW(MI, BB); 1052 case Mips::FILL_FD_PSEUDO: 1053 return emitFILL_FD(MI, BB); 1054 case Mips::FEXP2_W_1_PSEUDO: 1055 return emitFEXP2_W_1(MI, BB); 1056 case Mips::FEXP2_D_1_PSEUDO: 1057 return emitFEXP2_D_1(MI, BB); 1058 } 1059 } 1060 1061 bool MipsSETargetLowering:: 1062 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 1063 unsigned NextStackOffset, 1064 const MipsFunctionInfo& FI) const { 1065 if (!EnableMipsTailCalls) 1066 return false; 1067 1068 // Return false if either the callee or caller has a byval argument. 1069 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 1070 return false; 1071 1072 // Return true if the callee's argument area is no larger than the 1073 // caller's. 1074 return NextStackOffset <= FI.getIncomingArgSize(); 1075 } 1076 1077 void MipsSETargetLowering:: 1078 getOpndList(SmallVectorImpl<SDValue> &Ops, 1079 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 1080 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 1081 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 1082 Ops.push_back(Callee); 1083 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 1084 InternalLinkage, CLI, Callee, Chain); 1085 } 1086 1087 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1088 LoadSDNode &Nd = *cast<LoadSDNode>(Op); 1089 1090 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 1091 return MipsTargetLowering::lowerLOAD(Op, DAG); 1092 1093 // Replace a double precision load with two i32 loads and a buildpair64. 1094 SDLoc DL(Op); 1095 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 1096 EVT PtrVT = Ptr.getValueType(); 1097 1098 // i32 load from lower address. 1099 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, 1100 MachinePointerInfo(), Nd.isVolatile(), 1101 Nd.isNonTemporal(), Nd.isInvariant(), 1102 Nd.getAlignment()); 1103 1104 // i32 load from higher address. 1105 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 1106 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, 1107 MachinePointerInfo(), Nd.isVolatile(), 1108 Nd.isNonTemporal(), Nd.isInvariant(), 1109 std::min(Nd.getAlignment(), 4U)); 1110 1111 if (!Subtarget->isLittle()) 1112 std::swap(Lo, Hi); 1113 1114 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 1115 SDValue Ops[2] = {BP, Hi.getValue(1)}; 1116 return DAG.getMergeValues(Ops, 2, DL); 1117 } 1118 1119 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 1120 StoreSDNode &Nd = *cast<StoreSDNode>(Op); 1121 1122 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 1123 return MipsTargetLowering::lowerSTORE(Op, DAG); 1124 1125 // Replace a double precision store with two extractelement64s and i32 stores. 1126 SDLoc DL(Op); 1127 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 1128 EVT PtrVT = Ptr.getValueType(); 1129 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1130 Val, DAG.getConstant(0, MVT::i32)); 1131 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1132 Val, DAG.getConstant(1, MVT::i32)); 1133 1134 if (!Subtarget->isLittle()) 1135 std::swap(Lo, Hi); 1136 1137 // i32 store to lower address. 1138 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), 1139 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), 1140 Nd.getTBAAInfo()); 1141 1142 // i32 store to higher address. 1143 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 1144 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), 1145 Nd.isVolatile(), Nd.isNonTemporal(), 1146 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo()); 1147 } 1148 1149 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, 1150 bool HasLo, bool HasHi, 1151 SelectionDAG &DAG) const { 1152 EVT Ty = Op.getOperand(0).getValueType(); 1153 SDLoc DL(Op); 1154 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, 1155 Op.getOperand(0), Op.getOperand(1)); 1156 SDValue Lo, Hi; 1157 1158 if (HasLo) 1159 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); 1160 if (HasHi) 1161 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); 1162 1163 if (!HasLo || !HasHi) 1164 return HasLo ? Lo : Hi; 1165 1166 SDValue Vals[] = { Lo, Hi }; 1167 return DAG.getMergeValues(Vals, 2, DL); 1168 } 1169 1170 1171 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { 1172 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 1173 DAG.getConstant(0, MVT::i32)); 1174 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 1175 DAG.getConstant(1, MVT::i32)); 1176 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); 1177 } 1178 1179 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) { 1180 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); 1181 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); 1182 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); 1183 } 1184 1185 // This function expands mips intrinsic nodes which have 64-bit input operands 1186 // or output values. 1187 // 1188 // out64 = intrinsic-node in64 1189 // => 1190 // lo = copy (extract-element (in64, 0)) 1191 // hi = copy (extract-element (in64, 1)) 1192 // mips-specific-node 1193 // v0 = copy lo 1194 // v1 = copy hi 1195 // out64 = merge-values (v0, v1) 1196 // 1197 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1198 SDLoc DL(Op); 1199 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 1200 SmallVector<SDValue, 3> Ops; 1201 unsigned OpNo = 0; 1202 1203 // See if Op has a chain input. 1204 if (HasChainIn) 1205 Ops.push_back(Op->getOperand(OpNo++)); 1206 1207 // The next operand is the intrinsic opcode. 1208 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); 1209 1210 // See if the next operand has type i64. 1211 SDValue Opnd = Op->getOperand(++OpNo), In64; 1212 1213 if (Opnd.getValueType() == MVT::i64) 1214 In64 = initAccumulator(Opnd, DL, DAG); 1215 else 1216 Ops.push_back(Opnd); 1217 1218 // Push the remaining operands. 1219 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) 1220 Ops.push_back(Op->getOperand(OpNo)); 1221 1222 // Add In64 to the end of the list. 1223 if (In64.getNode()) 1224 Ops.push_back(In64); 1225 1226 // Scan output. 1227 SmallVector<EVT, 2> ResTys; 1228 1229 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); 1230 I != E; ++I) 1231 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); 1232 1233 // Create node. 1234 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size()); 1235 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; 1236 1237 if (!HasChainIn) 1238 return Out; 1239 1240 assert(Val->getValueType(1) == MVT::Other); 1241 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; 1242 return DAG.getMergeValues(Vals, 2, DL); 1243 } 1244 1245 // Lower an MSA copy intrinsic into the specified SelectionDAG node 1246 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1247 SDLoc DL(Op); 1248 SDValue Vec = Op->getOperand(1); 1249 SDValue Idx = Op->getOperand(2); 1250 EVT ResTy = Op->getValueType(0); 1251 EVT EltTy = Vec->getValueType(0).getVectorElementType(); 1252 1253 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx, 1254 DAG.getValueType(EltTy)); 1255 1256 return Result; 1257 } 1258 1259 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) { 1260 EVT ResVecTy = Op->getValueType(0); 1261 EVT ViaVecTy = ResVecTy; 1262 SDLoc DL(Op); 1263 1264 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and 1265 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating 1266 // lanes. 1267 SDValue LaneA; 1268 SDValue LaneB = Op->getOperand(2); 1269 1270 if (ResVecTy == MVT::v2i64) { 1271 LaneA = DAG.getConstant(0, MVT::i32); 1272 ViaVecTy = MVT::v4i32; 1273 } else 1274 LaneA = LaneB; 1275 1276 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, 1277 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB }; 1278 1279 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops, 1280 ViaVecTy.getVectorNumElements()); 1281 1282 if (ViaVecTy != ResVecTy) 1283 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result); 1284 1285 return Result; 1286 } 1287 1288 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { 1289 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0)); 1290 } 1291 1292 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, 1293 bool BigEndian, SelectionDAG &DAG) { 1294 EVT ViaVecTy = VecTy; 1295 SDValue SplatValueA = SplatValue; 1296 SDValue SplatValueB = SplatValue; 1297 SDLoc DL(SplatValue); 1298 1299 if (VecTy == MVT::v2i64) { 1300 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's. 1301 ViaVecTy = MVT::v4i32; 1302 1303 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue); 1304 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue, 1305 DAG.getConstant(32, MVT::i32)); 1306 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB); 1307 } 1308 1309 // We currently hold the parts in little endian order. Swap them if 1310 // necessary. 1311 if (BigEndian) 1312 std::swap(SplatValueA, SplatValueB); 1313 1314 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1315 SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1316 SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1317 SplatValueA, SplatValueB, SplatValueA, SplatValueB }; 1318 1319 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops, 1320 ViaVecTy.getVectorNumElements()); 1321 1322 if (VecTy != ViaVecTy) 1323 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); 1324 1325 return Result; 1326 } 1327 1328 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, 1329 unsigned Opc, SDValue Imm, 1330 bool BigEndian) { 1331 EVT VecTy = Op->getValueType(0); 1332 SDValue Exp2Imm; 1333 SDLoc DL(Op); 1334 1335 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it 1336 // here for now. 1337 if (VecTy == MVT::v2i64) { 1338 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) { 1339 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue(); 1340 1341 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32); 1342 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32); 1343 1344 if (BigEndian) 1345 std::swap(BitImmLoOp, BitImmHiOp); 1346 1347 Exp2Imm = 1348 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, 1349 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp, 1350 BitImmHiOp, BitImmLoOp, BitImmHiOp)); 1351 } 1352 } 1353 1354 if (Exp2Imm.getNode() == NULL) { 1355 // We couldnt constant fold, do a vector shift instead 1356 1357 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since 1358 // only values 0-63 are valid. 1359 if (VecTy == MVT::v2i64) 1360 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm); 1361 1362 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG); 1363 1364 Exp2Imm = 1365 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm); 1366 } 1367 1368 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm); 1369 } 1370 1371 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) { 1372 EVT ResTy = Op->getValueType(0); 1373 SDLoc DL(Op); 1374 SDValue One = DAG.getConstant(1, ResTy); 1375 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); 1376 1377 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), 1378 DAG.getNOT(DL, Bit, ResTy)); 1379 } 1380 1381 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { 1382 SDLoc DL(Op); 1383 EVT ResTy = Op->getValueType(0); 1384 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1) 1385 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue(); 1386 SDValue BitMask = DAG.getConstant(~BitImm, ResTy); 1387 1388 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); 1389 } 1390 1391 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, 1392 SelectionDAG &DAG) const { 1393 SDLoc DL(Op); 1394 1395 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 1396 default: 1397 return SDValue(); 1398 case Intrinsic::mips_shilo: 1399 return lowerDSPIntr(Op, DAG, MipsISD::SHILO); 1400 case Intrinsic::mips_dpau_h_qbl: 1401 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); 1402 case Intrinsic::mips_dpau_h_qbr: 1403 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); 1404 case Intrinsic::mips_dpsu_h_qbl: 1405 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); 1406 case Intrinsic::mips_dpsu_h_qbr: 1407 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); 1408 case Intrinsic::mips_dpa_w_ph: 1409 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); 1410 case Intrinsic::mips_dps_w_ph: 1411 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); 1412 case Intrinsic::mips_dpax_w_ph: 1413 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); 1414 case Intrinsic::mips_dpsx_w_ph: 1415 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); 1416 case Intrinsic::mips_mulsa_w_ph: 1417 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); 1418 case Intrinsic::mips_mult: 1419 return lowerDSPIntr(Op, DAG, MipsISD::Mult); 1420 case Intrinsic::mips_multu: 1421 return lowerDSPIntr(Op, DAG, MipsISD::Multu); 1422 case Intrinsic::mips_madd: 1423 return lowerDSPIntr(Op, DAG, MipsISD::MAdd); 1424 case Intrinsic::mips_maddu: 1425 return lowerDSPIntr(Op, DAG, MipsISD::MAddu); 1426 case Intrinsic::mips_msub: 1427 return lowerDSPIntr(Op, DAG, MipsISD::MSub); 1428 case Intrinsic::mips_msubu: 1429 return lowerDSPIntr(Op, DAG, MipsISD::MSubu); 1430 case Intrinsic::mips_addv_b: 1431 case Intrinsic::mips_addv_h: 1432 case Intrinsic::mips_addv_w: 1433 case Intrinsic::mips_addv_d: 1434 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1435 Op->getOperand(2)); 1436 case Intrinsic::mips_addvi_b: 1437 case Intrinsic::mips_addvi_h: 1438 case Intrinsic::mips_addvi_w: 1439 case Intrinsic::mips_addvi_d: 1440 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1441 lowerMSASplatImm(Op, 2, DAG)); 1442 case Intrinsic::mips_and_v: 1443 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1444 Op->getOperand(2)); 1445 case Intrinsic::mips_andi_b: 1446 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1447 lowerMSASplatImm(Op, 2, DAG)); 1448 case Intrinsic::mips_bclr_b: 1449 case Intrinsic::mips_bclr_h: 1450 case Intrinsic::mips_bclr_w: 1451 case Intrinsic::mips_bclr_d: 1452 return lowerMSABitClear(Op, DAG); 1453 case Intrinsic::mips_bclri_b: 1454 case Intrinsic::mips_bclri_h: 1455 case Intrinsic::mips_bclri_w: 1456 case Intrinsic::mips_bclri_d: 1457 return lowerMSABitClearImm(Op, DAG); 1458 case Intrinsic::mips_binsli_b: 1459 case Intrinsic::mips_binsli_h: 1460 case Intrinsic::mips_binsli_w: 1461 case Intrinsic::mips_binsli_d: { 1462 EVT VecTy = Op->getValueType(0); 1463 EVT EltTy = VecTy.getVectorElementType(); 1464 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), 1465 Op->getConstantOperandVal(3)); 1466 return DAG.getNode(ISD::VSELECT, DL, VecTy, 1467 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1), 1468 Op->getOperand(2)); 1469 } 1470 case Intrinsic::mips_binsri_b: 1471 case Intrinsic::mips_binsri_h: 1472 case Intrinsic::mips_binsri_w: 1473 case Intrinsic::mips_binsri_d: { 1474 EVT VecTy = Op->getValueType(0); 1475 EVT EltTy = VecTy.getVectorElementType(); 1476 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), 1477 Op->getConstantOperandVal(3)); 1478 return DAG.getNode(ISD::VSELECT, DL, VecTy, 1479 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1), 1480 Op->getOperand(2)); 1481 } 1482 case Intrinsic::mips_bmnz_v: 1483 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), 1484 Op->getOperand(2), Op->getOperand(1)); 1485 case Intrinsic::mips_bmnzi_b: 1486 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1487 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), 1488 Op->getOperand(1)); 1489 case Intrinsic::mips_bmz_v: 1490 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), 1491 Op->getOperand(1), Op->getOperand(2)); 1492 case Intrinsic::mips_bmzi_b: 1493 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1494 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), 1495 Op->getOperand(2)); 1496 case Intrinsic::mips_bneg_b: 1497 case Intrinsic::mips_bneg_h: 1498 case Intrinsic::mips_bneg_w: 1499 case Intrinsic::mips_bneg_d: { 1500 EVT VecTy = Op->getValueType(0); 1501 SDValue One = DAG.getConstant(1, VecTy); 1502 1503 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), 1504 DAG.getNode(ISD::SHL, DL, VecTy, One, 1505 Op->getOperand(2))); 1506 } 1507 case Intrinsic::mips_bnegi_b: 1508 case Intrinsic::mips_bnegi_h: 1509 case Intrinsic::mips_bnegi_w: 1510 case Intrinsic::mips_bnegi_d: 1511 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), 1512 !Subtarget->isLittle()); 1513 case Intrinsic::mips_bnz_b: 1514 case Intrinsic::mips_bnz_h: 1515 case Intrinsic::mips_bnz_w: 1516 case Intrinsic::mips_bnz_d: 1517 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), 1518 Op->getOperand(1)); 1519 case Intrinsic::mips_bnz_v: 1520 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), 1521 Op->getOperand(1)); 1522 case Intrinsic::mips_bsel_v: 1523 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1524 Op->getOperand(1), Op->getOperand(2), 1525 Op->getOperand(3)); 1526 case Intrinsic::mips_bseli_b: 1527 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1528 Op->getOperand(1), Op->getOperand(2), 1529 lowerMSASplatImm(Op, 3, DAG)); 1530 case Intrinsic::mips_bset_b: 1531 case Intrinsic::mips_bset_h: 1532 case Intrinsic::mips_bset_w: 1533 case Intrinsic::mips_bset_d: { 1534 EVT VecTy = Op->getValueType(0); 1535 SDValue One = DAG.getConstant(1, VecTy); 1536 1537 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), 1538 DAG.getNode(ISD::SHL, DL, VecTy, One, 1539 Op->getOperand(2))); 1540 } 1541 case Intrinsic::mips_bseti_b: 1542 case Intrinsic::mips_bseti_h: 1543 case Intrinsic::mips_bseti_w: 1544 case Intrinsic::mips_bseti_d: 1545 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), 1546 !Subtarget->isLittle()); 1547 case Intrinsic::mips_bz_b: 1548 case Intrinsic::mips_bz_h: 1549 case Intrinsic::mips_bz_w: 1550 case Intrinsic::mips_bz_d: 1551 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), 1552 Op->getOperand(1)); 1553 case Intrinsic::mips_bz_v: 1554 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), 1555 Op->getOperand(1)); 1556 case Intrinsic::mips_ceq_b: 1557 case Intrinsic::mips_ceq_h: 1558 case Intrinsic::mips_ceq_w: 1559 case Intrinsic::mips_ceq_d: 1560 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1561 Op->getOperand(2), ISD::SETEQ); 1562 case Intrinsic::mips_ceqi_b: 1563 case Intrinsic::mips_ceqi_h: 1564 case Intrinsic::mips_ceqi_w: 1565 case Intrinsic::mips_ceqi_d: 1566 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1567 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); 1568 case Intrinsic::mips_cle_s_b: 1569 case Intrinsic::mips_cle_s_h: 1570 case Intrinsic::mips_cle_s_w: 1571 case Intrinsic::mips_cle_s_d: 1572 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1573 Op->getOperand(2), ISD::SETLE); 1574 case Intrinsic::mips_clei_s_b: 1575 case Intrinsic::mips_clei_s_h: 1576 case Intrinsic::mips_clei_s_w: 1577 case Intrinsic::mips_clei_s_d: 1578 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1579 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); 1580 case Intrinsic::mips_cle_u_b: 1581 case Intrinsic::mips_cle_u_h: 1582 case Intrinsic::mips_cle_u_w: 1583 case Intrinsic::mips_cle_u_d: 1584 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1585 Op->getOperand(2), ISD::SETULE); 1586 case Intrinsic::mips_clei_u_b: 1587 case Intrinsic::mips_clei_u_h: 1588 case Intrinsic::mips_clei_u_w: 1589 case Intrinsic::mips_clei_u_d: 1590 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1591 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); 1592 case Intrinsic::mips_clt_s_b: 1593 case Intrinsic::mips_clt_s_h: 1594 case Intrinsic::mips_clt_s_w: 1595 case Intrinsic::mips_clt_s_d: 1596 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1597 Op->getOperand(2), ISD::SETLT); 1598 case Intrinsic::mips_clti_s_b: 1599 case Intrinsic::mips_clti_s_h: 1600 case Intrinsic::mips_clti_s_w: 1601 case Intrinsic::mips_clti_s_d: 1602 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1603 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); 1604 case Intrinsic::mips_clt_u_b: 1605 case Intrinsic::mips_clt_u_h: 1606 case Intrinsic::mips_clt_u_w: 1607 case Intrinsic::mips_clt_u_d: 1608 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1609 Op->getOperand(2), ISD::SETULT); 1610 case Intrinsic::mips_clti_u_b: 1611 case Intrinsic::mips_clti_u_h: 1612 case Intrinsic::mips_clti_u_w: 1613 case Intrinsic::mips_clti_u_d: 1614 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1615 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1616 case Intrinsic::mips_copy_s_b: 1617 case Intrinsic::mips_copy_s_h: 1618 case Intrinsic::mips_copy_s_w: 1619 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1620 case Intrinsic::mips_copy_s_d: 1621 if (HasMips64) 1622 // Lower directly into VEXTRACT_SEXT_ELT since i64 is legal on Mips64. 1623 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1624 else { 1625 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type 1626 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1627 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 1628 Op->getValueType(0), Op->getOperand(1), 1629 Op->getOperand(2)); 1630 } 1631 case Intrinsic::mips_copy_u_b: 1632 case Intrinsic::mips_copy_u_h: 1633 case Intrinsic::mips_copy_u_w: 1634 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1635 case Intrinsic::mips_copy_u_d: 1636 if (HasMips64) 1637 // Lower directly into VEXTRACT_ZEXT_ELT since i64 is legal on Mips64. 1638 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1639 else { 1640 // Lower into the generic EXTRACT_VECTOR_ELT node and let the type 1641 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1642 // Note: When i64 is illegal, this results in copy_s.w instructions 1643 // instead of copy_u.w instructions. This makes no difference to the 1644 // behaviour since i64 is only illegal when the register file is 32-bit. 1645 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), 1646 Op->getValueType(0), Op->getOperand(1), 1647 Op->getOperand(2)); 1648 } 1649 case Intrinsic::mips_div_s_b: 1650 case Intrinsic::mips_div_s_h: 1651 case Intrinsic::mips_div_s_w: 1652 case Intrinsic::mips_div_s_d: 1653 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), 1654 Op->getOperand(2)); 1655 case Intrinsic::mips_div_u_b: 1656 case Intrinsic::mips_div_u_h: 1657 case Intrinsic::mips_div_u_w: 1658 case Intrinsic::mips_div_u_d: 1659 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), 1660 Op->getOperand(2)); 1661 case Intrinsic::mips_fadd_w: 1662 case Intrinsic::mips_fadd_d: 1663 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), 1664 Op->getOperand(2)); 1665 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away 1666 case Intrinsic::mips_fceq_w: 1667 case Intrinsic::mips_fceq_d: 1668 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1669 Op->getOperand(2), ISD::SETOEQ); 1670 case Intrinsic::mips_fcle_w: 1671 case Intrinsic::mips_fcle_d: 1672 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1673 Op->getOperand(2), ISD::SETOLE); 1674 case Intrinsic::mips_fclt_w: 1675 case Intrinsic::mips_fclt_d: 1676 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1677 Op->getOperand(2), ISD::SETOLT); 1678 case Intrinsic::mips_fcne_w: 1679 case Intrinsic::mips_fcne_d: 1680 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1681 Op->getOperand(2), ISD::SETONE); 1682 case Intrinsic::mips_fcor_w: 1683 case Intrinsic::mips_fcor_d: 1684 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1685 Op->getOperand(2), ISD::SETO); 1686 case Intrinsic::mips_fcueq_w: 1687 case Intrinsic::mips_fcueq_d: 1688 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1689 Op->getOperand(2), ISD::SETUEQ); 1690 case Intrinsic::mips_fcule_w: 1691 case Intrinsic::mips_fcule_d: 1692 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1693 Op->getOperand(2), ISD::SETULE); 1694 case Intrinsic::mips_fcult_w: 1695 case Intrinsic::mips_fcult_d: 1696 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1697 Op->getOperand(2), ISD::SETULT); 1698 case Intrinsic::mips_fcun_w: 1699 case Intrinsic::mips_fcun_d: 1700 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1701 Op->getOperand(2), ISD::SETUO); 1702 case Intrinsic::mips_fcune_w: 1703 case Intrinsic::mips_fcune_d: 1704 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1705 Op->getOperand(2), ISD::SETUNE); 1706 case Intrinsic::mips_fdiv_w: 1707 case Intrinsic::mips_fdiv_d: 1708 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), 1709 Op->getOperand(2)); 1710 case Intrinsic::mips_ffint_u_w: 1711 case Intrinsic::mips_ffint_u_d: 1712 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), 1713 Op->getOperand(1)); 1714 case Intrinsic::mips_ffint_s_w: 1715 case Intrinsic::mips_ffint_s_d: 1716 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), 1717 Op->getOperand(1)); 1718 case Intrinsic::mips_fill_b: 1719 case Intrinsic::mips_fill_h: 1720 case Intrinsic::mips_fill_w: 1721 case Intrinsic::mips_fill_d: { 1722 SmallVector<SDValue, 16> Ops; 1723 EVT ResTy = Op->getValueType(0); 1724 1725 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1726 Ops.push_back(Op->getOperand(1)); 1727 1728 // If ResTy is v2i64 then the type legalizer will break this node down into 1729 // an equivalent v4i32. 1730 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size()); 1731 } 1732 case Intrinsic::mips_fexp2_w: 1733 case Intrinsic::mips_fexp2_d: { 1734 EVT ResTy = Op->getValueType(0); 1735 return DAG.getNode( 1736 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), 1737 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); 1738 } 1739 case Intrinsic::mips_flog2_w: 1740 case Intrinsic::mips_flog2_d: 1741 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); 1742 case Intrinsic::mips_fmadd_w: 1743 case Intrinsic::mips_fmadd_d: 1744 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), 1745 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1746 case Intrinsic::mips_fmul_w: 1747 case Intrinsic::mips_fmul_d: 1748 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), 1749 Op->getOperand(2)); 1750 case Intrinsic::mips_fmsub_w: 1751 case Intrinsic::mips_fmsub_d: { 1752 EVT ResTy = Op->getValueType(0); 1753 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1), 1754 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, 1755 Op->getOperand(2), Op->getOperand(3))); 1756 } 1757 case Intrinsic::mips_frint_w: 1758 case Intrinsic::mips_frint_d: 1759 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); 1760 case Intrinsic::mips_fsqrt_w: 1761 case Intrinsic::mips_fsqrt_d: 1762 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); 1763 case Intrinsic::mips_fsub_w: 1764 case Intrinsic::mips_fsub_d: 1765 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), 1766 Op->getOperand(2)); 1767 case Intrinsic::mips_ftrunc_u_w: 1768 case Intrinsic::mips_ftrunc_u_d: 1769 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), 1770 Op->getOperand(1)); 1771 case Intrinsic::mips_ftrunc_s_w: 1772 case Intrinsic::mips_ftrunc_s_d: 1773 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), 1774 Op->getOperand(1)); 1775 case Intrinsic::mips_ilvev_b: 1776 case Intrinsic::mips_ilvev_h: 1777 case Intrinsic::mips_ilvev_w: 1778 case Intrinsic::mips_ilvev_d: 1779 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), 1780 Op->getOperand(1), Op->getOperand(2)); 1781 case Intrinsic::mips_ilvl_b: 1782 case Intrinsic::mips_ilvl_h: 1783 case Intrinsic::mips_ilvl_w: 1784 case Intrinsic::mips_ilvl_d: 1785 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), 1786 Op->getOperand(1), Op->getOperand(2)); 1787 case Intrinsic::mips_ilvod_b: 1788 case Intrinsic::mips_ilvod_h: 1789 case Intrinsic::mips_ilvod_w: 1790 case Intrinsic::mips_ilvod_d: 1791 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), 1792 Op->getOperand(1), Op->getOperand(2)); 1793 case Intrinsic::mips_ilvr_b: 1794 case Intrinsic::mips_ilvr_h: 1795 case Intrinsic::mips_ilvr_w: 1796 case Intrinsic::mips_ilvr_d: 1797 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), 1798 Op->getOperand(1), Op->getOperand(2)); 1799 case Intrinsic::mips_insert_b: 1800 case Intrinsic::mips_insert_h: 1801 case Intrinsic::mips_insert_w: 1802 case Intrinsic::mips_insert_d: 1803 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1804 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); 1805 case Intrinsic::mips_ldi_b: 1806 case Intrinsic::mips_ldi_h: 1807 case Intrinsic::mips_ldi_w: 1808 case Intrinsic::mips_ldi_d: 1809 return lowerMSASplatImm(Op, 1, DAG); 1810 case Intrinsic::mips_lsa: 1811 case Intrinsic::mips_dlsa: { 1812 EVT ResTy = Op->getValueType(0); 1813 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1814 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, 1815 Op->getOperand(2), Op->getOperand(3))); 1816 } 1817 case Intrinsic::mips_maddv_b: 1818 case Intrinsic::mips_maddv_h: 1819 case Intrinsic::mips_maddv_w: 1820 case Intrinsic::mips_maddv_d: { 1821 EVT ResTy = Op->getValueType(0); 1822 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1823 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1824 Op->getOperand(2), Op->getOperand(3))); 1825 } 1826 case Intrinsic::mips_max_s_b: 1827 case Intrinsic::mips_max_s_h: 1828 case Intrinsic::mips_max_s_w: 1829 case Intrinsic::mips_max_s_d: 1830 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1831 Op->getOperand(1), Op->getOperand(2)); 1832 case Intrinsic::mips_max_u_b: 1833 case Intrinsic::mips_max_u_h: 1834 case Intrinsic::mips_max_u_w: 1835 case Intrinsic::mips_max_u_d: 1836 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1837 Op->getOperand(1), Op->getOperand(2)); 1838 case Intrinsic::mips_maxi_s_b: 1839 case Intrinsic::mips_maxi_s_h: 1840 case Intrinsic::mips_maxi_s_w: 1841 case Intrinsic::mips_maxi_s_d: 1842 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1843 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1844 case Intrinsic::mips_maxi_u_b: 1845 case Intrinsic::mips_maxi_u_h: 1846 case Intrinsic::mips_maxi_u_w: 1847 case Intrinsic::mips_maxi_u_d: 1848 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1849 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1850 case Intrinsic::mips_min_s_b: 1851 case Intrinsic::mips_min_s_h: 1852 case Intrinsic::mips_min_s_w: 1853 case Intrinsic::mips_min_s_d: 1854 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1855 Op->getOperand(1), Op->getOperand(2)); 1856 case Intrinsic::mips_min_u_b: 1857 case Intrinsic::mips_min_u_h: 1858 case Intrinsic::mips_min_u_w: 1859 case Intrinsic::mips_min_u_d: 1860 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1861 Op->getOperand(1), Op->getOperand(2)); 1862 case Intrinsic::mips_mini_s_b: 1863 case Intrinsic::mips_mini_s_h: 1864 case Intrinsic::mips_mini_s_w: 1865 case Intrinsic::mips_mini_s_d: 1866 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1867 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1868 case Intrinsic::mips_mini_u_b: 1869 case Intrinsic::mips_mini_u_h: 1870 case Intrinsic::mips_mini_u_w: 1871 case Intrinsic::mips_mini_u_d: 1872 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1873 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1874 case Intrinsic::mips_mod_s_b: 1875 case Intrinsic::mips_mod_s_h: 1876 case Intrinsic::mips_mod_s_w: 1877 case Intrinsic::mips_mod_s_d: 1878 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), 1879 Op->getOperand(2)); 1880 case Intrinsic::mips_mod_u_b: 1881 case Intrinsic::mips_mod_u_h: 1882 case Intrinsic::mips_mod_u_w: 1883 case Intrinsic::mips_mod_u_d: 1884 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), 1885 Op->getOperand(2)); 1886 case Intrinsic::mips_mulv_b: 1887 case Intrinsic::mips_mulv_h: 1888 case Intrinsic::mips_mulv_w: 1889 case Intrinsic::mips_mulv_d: 1890 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), 1891 Op->getOperand(2)); 1892 case Intrinsic::mips_msubv_b: 1893 case Intrinsic::mips_msubv_h: 1894 case Intrinsic::mips_msubv_w: 1895 case Intrinsic::mips_msubv_d: { 1896 EVT ResTy = Op->getValueType(0); 1897 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), 1898 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1899 Op->getOperand(2), Op->getOperand(3))); 1900 } 1901 case Intrinsic::mips_nlzc_b: 1902 case Intrinsic::mips_nlzc_h: 1903 case Intrinsic::mips_nlzc_w: 1904 case Intrinsic::mips_nlzc_d: 1905 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); 1906 case Intrinsic::mips_nor_v: { 1907 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1908 Op->getOperand(1), Op->getOperand(2)); 1909 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1910 } 1911 case Intrinsic::mips_nori_b: { 1912 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1913 Op->getOperand(1), 1914 lowerMSASplatImm(Op, 2, DAG)); 1915 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1916 } 1917 case Intrinsic::mips_or_v: 1918 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), 1919 Op->getOperand(2)); 1920 case Intrinsic::mips_ori_b: 1921 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1922 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1923 case Intrinsic::mips_pckev_b: 1924 case Intrinsic::mips_pckev_h: 1925 case Intrinsic::mips_pckev_w: 1926 case Intrinsic::mips_pckev_d: 1927 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), 1928 Op->getOperand(1), Op->getOperand(2)); 1929 case Intrinsic::mips_pckod_b: 1930 case Intrinsic::mips_pckod_h: 1931 case Intrinsic::mips_pckod_w: 1932 case Intrinsic::mips_pckod_d: 1933 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), 1934 Op->getOperand(1), Op->getOperand(2)); 1935 case Intrinsic::mips_pcnt_b: 1936 case Intrinsic::mips_pcnt_h: 1937 case Intrinsic::mips_pcnt_w: 1938 case Intrinsic::mips_pcnt_d: 1939 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); 1940 case Intrinsic::mips_shf_b: 1941 case Intrinsic::mips_shf_h: 1942 case Intrinsic::mips_shf_w: 1943 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), 1944 Op->getOperand(2), Op->getOperand(1)); 1945 case Intrinsic::mips_sll_b: 1946 case Intrinsic::mips_sll_h: 1947 case Intrinsic::mips_sll_w: 1948 case Intrinsic::mips_sll_d: 1949 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), 1950 Op->getOperand(2)); 1951 case Intrinsic::mips_slli_b: 1952 case Intrinsic::mips_slli_h: 1953 case Intrinsic::mips_slli_w: 1954 case Intrinsic::mips_slli_d: 1955 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), 1956 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1957 case Intrinsic::mips_splat_b: 1958 case Intrinsic::mips_splat_h: 1959 case Intrinsic::mips_splat_w: 1960 case Intrinsic::mips_splat_d: 1961 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle 1962 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because 1963 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32. 1964 // Instead we lower to MipsISD::VSHF and match from there. 1965 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1966 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), 1967 Op->getOperand(1)); 1968 case Intrinsic::mips_splati_b: 1969 case Intrinsic::mips_splati_h: 1970 case Intrinsic::mips_splati_w: 1971 case Intrinsic::mips_splati_d: 1972 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1973 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 1974 Op->getOperand(1)); 1975 case Intrinsic::mips_sra_b: 1976 case Intrinsic::mips_sra_h: 1977 case Intrinsic::mips_sra_w: 1978 case Intrinsic::mips_sra_d: 1979 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), 1980 Op->getOperand(2)); 1981 case Intrinsic::mips_srai_b: 1982 case Intrinsic::mips_srai_h: 1983 case Intrinsic::mips_srai_w: 1984 case Intrinsic::mips_srai_d: 1985 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), 1986 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1987 case Intrinsic::mips_srl_b: 1988 case Intrinsic::mips_srl_h: 1989 case Intrinsic::mips_srl_w: 1990 case Intrinsic::mips_srl_d: 1991 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), 1992 Op->getOperand(2)); 1993 case Intrinsic::mips_srli_b: 1994 case Intrinsic::mips_srli_h: 1995 case Intrinsic::mips_srli_w: 1996 case Intrinsic::mips_srli_d: 1997 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), 1998 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1999 case Intrinsic::mips_subv_b: 2000 case Intrinsic::mips_subv_h: 2001 case Intrinsic::mips_subv_w: 2002 case Intrinsic::mips_subv_d: 2003 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), 2004 Op->getOperand(2)); 2005 case Intrinsic::mips_subvi_b: 2006 case Intrinsic::mips_subvi_h: 2007 case Intrinsic::mips_subvi_w: 2008 case Intrinsic::mips_subvi_d: 2009 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), 2010 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2011 case Intrinsic::mips_vshf_b: 2012 case Intrinsic::mips_vshf_h: 2013 case Intrinsic::mips_vshf_w: 2014 case Intrinsic::mips_vshf_d: 2015 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 2016 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 2017 case Intrinsic::mips_xor_v: 2018 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), 2019 Op->getOperand(2)); 2020 case Intrinsic::mips_xori_b: 2021 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), 2022 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2023 } 2024 } 2025 2026 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 2027 SDLoc DL(Op); 2028 SDValue ChainIn = Op->getOperand(0); 2029 SDValue Address = Op->getOperand(2); 2030 SDValue Offset = Op->getOperand(3); 2031 EVT ResTy = Op->getValueType(0); 2032 EVT PtrTy = Address->getValueType(0); 2033 2034 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 2035 2036 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false, 2037 false, false, 16); 2038 } 2039 2040 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, 2041 SelectionDAG &DAG) const { 2042 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 2043 switch (Intr) { 2044 default: 2045 return SDValue(); 2046 case Intrinsic::mips_extp: 2047 return lowerDSPIntr(Op, DAG, MipsISD::EXTP); 2048 case Intrinsic::mips_extpdp: 2049 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); 2050 case Intrinsic::mips_extr_w: 2051 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); 2052 case Intrinsic::mips_extr_r_w: 2053 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); 2054 case Intrinsic::mips_extr_rs_w: 2055 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); 2056 case Intrinsic::mips_extr_s_h: 2057 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); 2058 case Intrinsic::mips_mthlip: 2059 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); 2060 case Intrinsic::mips_mulsaq_s_w_ph: 2061 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); 2062 case Intrinsic::mips_maq_s_w_phl: 2063 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); 2064 case Intrinsic::mips_maq_s_w_phr: 2065 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); 2066 case Intrinsic::mips_maq_sa_w_phl: 2067 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); 2068 case Intrinsic::mips_maq_sa_w_phr: 2069 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); 2070 case Intrinsic::mips_dpaq_s_w_ph: 2071 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); 2072 case Intrinsic::mips_dpsq_s_w_ph: 2073 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); 2074 case Intrinsic::mips_dpaq_sa_l_w: 2075 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); 2076 case Intrinsic::mips_dpsq_sa_l_w: 2077 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); 2078 case Intrinsic::mips_dpaqx_s_w_ph: 2079 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); 2080 case Intrinsic::mips_dpaqx_sa_w_ph: 2081 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); 2082 case Intrinsic::mips_dpsqx_s_w_ph: 2083 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); 2084 case Intrinsic::mips_dpsqx_sa_w_ph: 2085 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); 2086 case Intrinsic::mips_ld_b: 2087 case Intrinsic::mips_ld_h: 2088 case Intrinsic::mips_ld_w: 2089 case Intrinsic::mips_ld_d: 2090 return lowerMSALoadIntr(Op, DAG, Intr); 2091 } 2092 } 2093 2094 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 2095 SDLoc DL(Op); 2096 SDValue ChainIn = Op->getOperand(0); 2097 SDValue Value = Op->getOperand(2); 2098 SDValue Address = Op->getOperand(3); 2099 SDValue Offset = Op->getOperand(4); 2100 EVT PtrTy = Address->getValueType(0); 2101 2102 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 2103 2104 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false, 2105 false, 16); 2106 } 2107 2108 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, 2109 SelectionDAG &DAG) const { 2110 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 2111 switch (Intr) { 2112 default: 2113 return SDValue(); 2114 case Intrinsic::mips_st_b: 2115 case Intrinsic::mips_st_h: 2116 case Intrinsic::mips_st_w: 2117 case Intrinsic::mips_st_d: 2118 return lowerMSAStoreIntr(Op, DAG, Intr); 2119 } 2120 } 2121 2122 /// \brief Check if the given BuildVectorSDNode is a splat. 2123 /// This method currently relies on DAG nodes being reused when equivalent, 2124 /// so it's possible for this to return false even when isConstantSplat returns 2125 /// true. 2126 static bool isSplatVector(const BuildVectorSDNode *N) { 2127 unsigned int nOps = N->getNumOperands(); 2128 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector"); 2129 2130 SDValue Operand0 = N->getOperand(0); 2131 2132 for (unsigned int i = 1; i < nOps; ++i) { 2133 if (N->getOperand(i) != Operand0) 2134 return false; 2135 } 2136 2137 return true; 2138 } 2139 2140 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT. 2141 // 2142 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We 2143 // choose to sign-extend but we could have equally chosen zero-extend. The 2144 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT 2145 // result into this node later (possibly changing it to a zero-extend in the 2146 // process). 2147 SDValue MipsSETargetLowering:: 2148 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 2149 SDLoc DL(Op); 2150 EVT ResTy = Op->getValueType(0); 2151 SDValue Op0 = Op->getOperand(0); 2152 EVT VecTy = Op0->getValueType(0); 2153 2154 if (!VecTy.is128BitVector()) 2155 return SDValue(); 2156 2157 if (ResTy.isInteger()) { 2158 SDValue Op1 = Op->getOperand(1); 2159 EVT EltTy = VecTy.getVectorElementType(); 2160 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, 2161 DAG.getValueType(EltTy)); 2162 } 2163 2164 return Op; 2165 } 2166 2167 static bool isConstantOrUndef(const SDValue Op) { 2168 if (Op->getOpcode() == ISD::UNDEF) 2169 return true; 2170 if (dyn_cast<ConstantSDNode>(Op)) 2171 return true; 2172 if (dyn_cast<ConstantFPSDNode>(Op)) 2173 return true; 2174 return false; 2175 } 2176 2177 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { 2178 for (unsigned i = 0; i < Op->getNumOperands(); ++i) 2179 if (isConstantOrUndef(Op->getOperand(i))) 2180 return true; 2181 return false; 2182 } 2183 2184 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the 2185 // backend. 2186 // 2187 // Lowers according to the following rules: 2188 // - Constant splats are legal as-is as long as the SplatBitSize is a power of 2189 // 2 less than or equal to 64 and the value fits into a signed 10-bit 2190 // immediate 2191 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize 2192 // is a power of 2 less than or equal to 64 and the value does not fit into a 2193 // signed 10-bit immediate 2194 // - Non-constant splats are legal as-is. 2195 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 2196 // - All others are illegal and must be expanded. 2197 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, 2198 SelectionDAG &DAG) const { 2199 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op); 2200 EVT ResTy = Op->getValueType(0); 2201 SDLoc DL(Op); 2202 APInt SplatValue, SplatUndef; 2203 unsigned SplatBitSize; 2204 bool HasAnyUndefs; 2205 2206 if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) 2207 return SDValue(); 2208 2209 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 2210 HasAnyUndefs, 8, 2211 !Subtarget->isLittle()) && SplatBitSize <= 64) { 2212 // We can only cope with 8, 16, 32, or 64-bit elements 2213 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && 2214 SplatBitSize != 64) 2215 return SDValue(); 2216 2217 // If the value fits into a simm10 then we can use ldi.[bhwd] 2218 // However, if it isn't an integer type we will have to bitcast from an 2219 // integer type first. Also, if there are any undefs, we must lower them 2220 // to defined values first. 2221 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10)) 2222 return Op; 2223 2224 EVT ViaVecTy; 2225 2226 switch (SplatBitSize) { 2227 default: 2228 return SDValue(); 2229 case 8: 2230 ViaVecTy = MVT::v16i8; 2231 break; 2232 case 16: 2233 ViaVecTy = MVT::v8i16; 2234 break; 2235 case 32: 2236 ViaVecTy = MVT::v4i32; 2237 break; 2238 case 64: 2239 // There's no fill.d to fall back on for 64-bit values 2240 return SDValue(); 2241 } 2242 2243 // SelectionDAG::getConstant will promote SplatValue appropriately. 2244 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy); 2245 2246 // Bitcast to the type we originally wanted 2247 if (ViaVecTy != ResTy) 2248 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); 2249 2250 return Result; 2251 } else if (isSplatVector(Node)) 2252 return Op; 2253 else if (!isConstantOrUndefBUILD_VECTOR(Node)) { 2254 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 2255 // The resulting code is the same length as the expansion, but it doesn't 2256 // use memory operations 2257 EVT ResTy = Node->getValueType(0); 2258 2259 assert(ResTy.isVector()); 2260 2261 unsigned NumElts = ResTy.getVectorNumElements(); 2262 SDValue Vector = DAG.getUNDEF(ResTy); 2263 for (unsigned i = 0; i < NumElts; ++i) { 2264 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, 2265 Node->getOperand(i), 2266 DAG.getConstant(i, MVT::i32)); 2267 } 2268 return Vector; 2269 } 2270 2271 return SDValue(); 2272 } 2273 2274 // Lower VECTOR_SHUFFLE into SHF (if possible). 2275 // 2276 // SHF splits the vector into blocks of four elements, then shuffles these 2277 // elements according to a <4 x i2> constant (encoded as an integer immediate). 2278 // 2279 // It is therefore possible to lower into SHF when the mask takes the form: 2280 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> 2281 // When undef's appear they are treated as if they were whatever value is 2282 // necessary in order to fit the above form. 2283 // 2284 // For example: 2285 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef, 2286 // <8 x i32> <i32 3, i32 2, i32 1, i32 0, 2287 // i32 7, i32 6, i32 5, i32 4> 2288 // is lowered to: 2289 // (SHF_H $w0, $w1, 27) 2290 // where the 27 comes from: 2291 // 3 + (2 << 2) + (1 << 4) + (0 << 6) 2292 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, 2293 SmallVector<int, 16> Indices, 2294 SelectionDAG &DAG) { 2295 int SHFIndices[4] = { -1, -1, -1, -1 }; 2296 2297 if (Indices.size() < 4) 2298 return SDValue(); 2299 2300 for (unsigned i = 0; i < 4; ++i) { 2301 for (unsigned j = i; j < Indices.size(); j += 4) { 2302 int Idx = Indices[j]; 2303 2304 // Convert from vector index to 4-element subvector index 2305 // If an index refers to an element outside of the subvector then give up 2306 if (Idx != -1) { 2307 Idx -= 4 * (j / 4); 2308 if (Idx < 0 || Idx >= 4) 2309 return SDValue(); 2310 } 2311 2312 // If the mask has an undef, replace it with the current index. 2313 // Note that it might still be undef if the current index is also undef 2314 if (SHFIndices[i] == -1) 2315 SHFIndices[i] = Idx; 2316 2317 // Check that non-undef values are the same as in the mask. If they 2318 // aren't then give up 2319 if (!(Idx == -1 || Idx == SHFIndices[i])) 2320 return SDValue(); 2321 } 2322 } 2323 2324 // Calculate the immediate. Replace any remaining undefs with zero 2325 APInt Imm(32, 0); 2326 for (int i = 3; i >= 0; --i) { 2327 int Idx = SHFIndices[i]; 2328 2329 if (Idx == -1) 2330 Idx = 0; 2331 2332 Imm <<= 2; 2333 Imm |= Idx & 0x3; 2334 } 2335 2336 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy, 2337 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0)); 2338 } 2339 2340 // Lower VECTOR_SHUFFLE into ILVEV (if possible). 2341 // 2342 // ILVEV interleaves the even elements from each vector. 2343 // 2344 // It is possible to lower into ILVEV when the mask takes the form: 2345 // <0, n, 2, n+2, 4, n+4, ...> 2346 // where n is the number of elements in the vector. 2347 // 2348 // When undef's appear in the mask they are treated as if they were whatever 2349 // value is necessary in order to fit the above form. 2350 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, 2351 SmallVector<int, 16> Indices, 2352 SelectionDAG &DAG) { 2353 assert ((Indices.size() % 2) == 0); 2354 int WsIdx = 0; 2355 int WtIdx = ResTy.getVectorNumElements(); 2356 2357 for (unsigned i = 0; i < Indices.size(); i += 2) { 2358 if (Indices[i] != -1 && Indices[i] != WsIdx) 2359 return SDValue(); 2360 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2361 return SDValue(); 2362 WsIdx += 2; 2363 WtIdx += 2; 2364 } 2365 2366 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0), 2367 Op->getOperand(1)); 2368 } 2369 2370 // Lower VECTOR_SHUFFLE into ILVOD (if possible). 2371 // 2372 // ILVOD interleaves the odd elements from each vector. 2373 // 2374 // It is possible to lower into ILVOD when the mask takes the form: 2375 // <1, n+1, 3, n+3, 5, n+5, ...> 2376 // where n is the number of elements in the vector. 2377 // 2378 // When undef's appear in the mask they are treated as if they were whatever 2379 // value is necessary in order to fit the above form. 2380 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, 2381 SmallVector<int, 16> Indices, 2382 SelectionDAG &DAG) { 2383 assert ((Indices.size() % 2) == 0); 2384 int WsIdx = 1; 2385 int WtIdx = ResTy.getVectorNumElements() + 1; 2386 2387 for (unsigned i = 0; i < Indices.size(); i += 2) { 2388 if (Indices[i] != -1 && Indices[i] != WsIdx) 2389 return SDValue(); 2390 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2391 return SDValue(); 2392 WsIdx += 2; 2393 WtIdx += 2; 2394 } 2395 2396 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0), 2397 Op->getOperand(1)); 2398 } 2399 2400 // Lower VECTOR_SHUFFLE into ILVL (if possible). 2401 // 2402 // ILVL interleaves consecutive elements from the left half of each vector. 2403 // 2404 // It is possible to lower into ILVL when the mask takes the form: 2405 // <0, n, 1, n+1, 2, n+2, ...> 2406 // where n is the number of elements in the vector. 2407 // 2408 // When undef's appear in the mask they are treated as if they were whatever 2409 // value is necessary in order to fit the above form. 2410 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, 2411 SmallVector<int, 16> Indices, 2412 SelectionDAG &DAG) { 2413 assert ((Indices.size() % 2) == 0); 2414 int WsIdx = 0; 2415 int WtIdx = ResTy.getVectorNumElements(); 2416 2417 for (unsigned i = 0; i < Indices.size(); i += 2) { 2418 if (Indices[i] != -1 && Indices[i] != WsIdx) 2419 return SDValue(); 2420 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2421 return SDValue(); 2422 WsIdx ++; 2423 WtIdx ++; 2424 } 2425 2426 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0), 2427 Op->getOperand(1)); 2428 } 2429 2430 // Lower VECTOR_SHUFFLE into ILVR (if possible). 2431 // 2432 // ILVR interleaves consecutive elements from the right half of each vector. 2433 // 2434 // It is possible to lower into ILVR when the mask takes the form: 2435 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...> 2436 // where n is the number of elements in the vector and x is half n. 2437 // 2438 // When undef's appear in the mask they are treated as if they were whatever 2439 // value is necessary in order to fit the above form. 2440 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, 2441 SmallVector<int, 16> Indices, 2442 SelectionDAG &DAG) { 2443 assert ((Indices.size() % 2) == 0); 2444 unsigned NumElts = ResTy.getVectorNumElements(); 2445 int WsIdx = NumElts / 2; 2446 int WtIdx = NumElts + NumElts / 2; 2447 2448 for (unsigned i = 0; i < Indices.size(); i += 2) { 2449 if (Indices[i] != -1 && Indices[i] != WsIdx) 2450 return SDValue(); 2451 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2452 return SDValue(); 2453 WsIdx ++; 2454 WtIdx ++; 2455 } 2456 2457 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0), 2458 Op->getOperand(1)); 2459 } 2460 2461 // Lower VECTOR_SHUFFLE into PCKEV (if possible). 2462 // 2463 // PCKEV copies the even elements of each vector into the result vector. 2464 // 2465 // It is possible to lower into PCKEV when the mask takes the form: 2466 // <0, 2, 4, ..., n, n+2, n+4, ...> 2467 // where n is the number of elements in the vector. 2468 // 2469 // When undef's appear in the mask they are treated as if they were whatever 2470 // value is necessary in order to fit the above form. 2471 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, 2472 SmallVector<int, 16> Indices, 2473 SelectionDAG &DAG) { 2474 assert ((Indices.size() % 2) == 0); 2475 int Idx = 0; 2476 2477 for (unsigned i = 0; i < Indices.size(); ++i) { 2478 if (Indices[i] != -1 && Indices[i] != Idx) 2479 return SDValue(); 2480 Idx += 2; 2481 } 2482 2483 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0), 2484 Op->getOperand(1)); 2485 } 2486 2487 // Lower VECTOR_SHUFFLE into PCKOD (if possible). 2488 // 2489 // PCKOD copies the odd elements of each vector into the result vector. 2490 // 2491 // It is possible to lower into PCKOD when the mask takes the form: 2492 // <1, 3, 5, ..., n+1, n+3, n+5, ...> 2493 // where n is the number of elements in the vector. 2494 // 2495 // When undef's appear in the mask they are treated as if they were whatever 2496 // value is necessary in order to fit the above form. 2497 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, 2498 SmallVector<int, 16> Indices, 2499 SelectionDAG &DAG) { 2500 assert ((Indices.size() % 2) == 0); 2501 int Idx = 1; 2502 2503 for (unsigned i = 0; i < Indices.size(); ++i) { 2504 if (Indices[i] != -1 && Indices[i] != Idx) 2505 return SDValue(); 2506 Idx += 2; 2507 } 2508 2509 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0), 2510 Op->getOperand(1)); 2511 } 2512 2513 // Lower VECTOR_SHUFFLE into VSHF. 2514 // 2515 // This mostly consists of converting the shuffle indices in Indices into a 2516 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is 2517 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example, 2518 // if the type is v8i16 and all the indices are less than 8 then the second 2519 // operand is unused and can be replaced with anything. We choose to replace it 2520 // with the used operand since this reduces the number of instructions overall. 2521 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, 2522 SmallVector<int, 16> Indices, 2523 SelectionDAG &DAG) { 2524 SmallVector<SDValue, 16> Ops; 2525 SDValue Op0; 2526 SDValue Op1; 2527 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(); 2528 EVT MaskEltTy = MaskVecTy.getVectorElementType(); 2529 bool Using1stVec = false; 2530 bool Using2ndVec = false; 2531 SDLoc DL(Op); 2532 int ResTyNumElts = ResTy.getVectorNumElements(); 2533 2534 for (int i = 0; i < ResTyNumElts; ++i) { 2535 // Idx == -1 means UNDEF 2536 int Idx = Indices[i]; 2537 2538 if (0 <= Idx && Idx < ResTyNumElts) 2539 Using1stVec = true; 2540 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2) 2541 Using2ndVec = true; 2542 } 2543 2544 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); 2545 ++I) 2546 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy)); 2547 2548 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0], 2549 Ops.size()); 2550 2551 if (Using1stVec && Using2ndVec) { 2552 Op0 = Op->getOperand(0); 2553 Op1 = Op->getOperand(1); 2554 } else if (Using1stVec) 2555 Op0 = Op1 = Op->getOperand(0); 2556 else if (Using2ndVec) 2557 Op0 = Op1 = Op->getOperand(1); 2558 else 2559 llvm_unreachable("shuffle vector mask references neither vector operand?"); 2560 2561 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1); 2562 } 2563 2564 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the 2565 // indices in the shuffle. 2566 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op, 2567 SelectionDAG &DAG) const { 2568 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op); 2569 EVT ResTy = Op->getValueType(0); 2570 2571 if (!ResTy.is128BitVector()) 2572 return SDValue(); 2573 2574 int ResTyNumElts = ResTy.getVectorNumElements(); 2575 SmallVector<int, 16> Indices; 2576 2577 for (int i = 0; i < ResTyNumElts; ++i) 2578 Indices.push_back(Node->getMaskElt(i)); 2579 2580 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG); 2581 if (Result.getNode()) 2582 return Result; 2583 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG); 2584 if (Result.getNode()) 2585 return Result; 2586 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG); 2587 if (Result.getNode()) 2588 return Result; 2589 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG); 2590 if (Result.getNode()) 2591 return Result; 2592 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG); 2593 if (Result.getNode()) 2594 return Result; 2595 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG); 2596 if (Result.getNode()) 2597 return Result; 2598 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG); 2599 if (Result.getNode()) 2600 return Result; 2601 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); 2602 } 2603 2604 MachineBasicBlock * MipsSETargetLowering:: 2605 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 2606 // $bb: 2607 // bposge32_pseudo $vr0 2608 // => 2609 // $bb: 2610 // bposge32 $tbb 2611 // $fbb: 2612 // li $vr2, 0 2613 // b $sink 2614 // $tbb: 2615 // li $vr1, 1 2616 // $sink: 2617 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 2618 2619 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2620 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2621 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2622 DebugLoc DL = MI->getDebugLoc(); 2623 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2624 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2625 MachineFunction *F = BB->getParent(); 2626 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2627 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2628 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2629 F->insert(It, FBB); 2630 F->insert(It, TBB); 2631 F->insert(It, Sink); 2632 2633 // Transfer the remainder of BB and its successor edges to Sink. 2634 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2635 BB->end()); 2636 Sink->transferSuccessorsAndUpdatePHIs(BB); 2637 2638 // Add successors. 2639 BB->addSuccessor(FBB); 2640 BB->addSuccessor(TBB); 2641 FBB->addSuccessor(Sink); 2642 TBB->addSuccessor(Sink); 2643 2644 // Insert the real bposge32 instruction to $BB. 2645 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2646 2647 // Fill $FBB. 2648 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2649 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2650 .addReg(Mips::ZERO).addImm(0); 2651 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2652 2653 // Fill $TBB. 2654 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2655 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2656 .addReg(Mips::ZERO).addImm(1); 2657 2658 // Insert phi function to $Sink. 2659 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2660 MI->getOperand(0).getReg()) 2661 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 2662 2663 MI->eraseFromParent(); // The pseudo instruction is gone now. 2664 return Sink; 2665 } 2666 2667 MachineBasicBlock * MipsSETargetLowering:: 2668 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, 2669 unsigned BranchOp) const{ 2670 // $bb: 2671 // vany_nonzero $rd, $ws 2672 // => 2673 // $bb: 2674 // bnz.b $ws, $tbb 2675 // b $fbb 2676 // $fbb: 2677 // li $rd1, 0 2678 // b $sink 2679 // $tbb: 2680 // li $rd2, 1 2681 // $sink: 2682 // $rd = phi($rd1, $fbb, $rd2, $tbb) 2683 2684 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2685 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2686 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2687 DebugLoc DL = MI->getDebugLoc(); 2688 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2689 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2690 MachineFunction *F = BB->getParent(); 2691 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2692 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2693 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2694 F->insert(It, FBB); 2695 F->insert(It, TBB); 2696 F->insert(It, Sink); 2697 2698 // Transfer the remainder of BB and its successor edges to Sink. 2699 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2700 BB->end()); 2701 Sink->transferSuccessorsAndUpdatePHIs(BB); 2702 2703 // Add successors. 2704 BB->addSuccessor(FBB); 2705 BB->addSuccessor(TBB); 2706 FBB->addSuccessor(Sink); 2707 TBB->addSuccessor(Sink); 2708 2709 // Insert the real bnz.b instruction to $BB. 2710 BuildMI(BB, DL, TII->get(BranchOp)) 2711 .addReg(MI->getOperand(1).getReg()) 2712 .addMBB(TBB); 2713 2714 // Fill $FBB. 2715 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2716 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2717 .addReg(Mips::ZERO).addImm(0); 2718 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2719 2720 // Fill $TBB. 2721 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2722 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2723 .addReg(Mips::ZERO).addImm(1); 2724 2725 // Insert phi function to $Sink. 2726 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2727 MI->getOperand(0).getReg()) 2728 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); 2729 2730 MI->eraseFromParent(); // The pseudo instruction is gone now. 2731 return Sink; 2732 } 2733 2734 // Emit the COPY_FW pseudo instruction. 2735 // 2736 // copy_fw_pseudo $fd, $ws, n 2737 // => 2738 // copy_u_w $rt, $ws, $n 2739 // mtc1 $rt, $fd 2740 // 2741 // When n is zero, the equivalent operation can be performed with (potentially) 2742 // zero instructions due to register overlaps. This optimization is never valid 2743 // for lane 1 because it would require FR=0 mode which isn't supported by MSA. 2744 MachineBasicBlock * MipsSETargetLowering:: 2745 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2746 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2747 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2748 DebugLoc DL = MI->getDebugLoc(); 2749 unsigned Fd = MI->getOperand(0).getReg(); 2750 unsigned Ws = MI->getOperand(1).getReg(); 2751 unsigned Lane = MI->getOperand(2).getImm(); 2752 2753 if (Lane == 0) 2754 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); 2755 else { 2756 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2757 2758 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1); 2759 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2760 } 2761 2762 MI->eraseFromParent(); // The pseudo instruction is gone now. 2763 return BB; 2764 } 2765 2766 // Emit the COPY_FD pseudo instruction. 2767 // 2768 // copy_fd_pseudo $fd, $ws, n 2769 // => 2770 // splati.d $wt, $ws, $n 2771 // copy $fd, $wt:sub_64 2772 // 2773 // When n is zero, the equivalent operation can be performed with (potentially) 2774 // zero instructions due to register overlaps. This optimization is always 2775 // valid because FR=1 mode which is the only supported mode in MSA. 2776 MachineBasicBlock * MipsSETargetLowering:: 2777 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2778 assert(Subtarget->isFP64bit()); 2779 2780 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2781 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2782 unsigned Fd = MI->getOperand(0).getReg(); 2783 unsigned Ws = MI->getOperand(1).getReg(); 2784 unsigned Lane = MI->getOperand(2).getImm() * 2; 2785 DebugLoc DL = MI->getDebugLoc(); 2786 2787 if (Lane == 0) 2788 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); 2789 else { 2790 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2791 2792 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); 2793 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); 2794 } 2795 2796 MI->eraseFromParent(); // The pseudo instruction is gone now. 2797 return BB; 2798 } 2799 2800 // Emit the INSERT_FW pseudo instruction. 2801 // 2802 // insert_fw_pseudo $wd, $wd_in, $n, $fs 2803 // => 2804 // subreg_to_reg $wt:sub_lo, $fs 2805 // insve_w $wd[$n], $wd_in, $wt[0] 2806 MachineBasicBlock * 2807 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, 2808 MachineBasicBlock *BB) const { 2809 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2810 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2811 DebugLoc DL = MI->getDebugLoc(); 2812 unsigned Wd = MI->getOperand(0).getReg(); 2813 unsigned Wd_in = MI->getOperand(1).getReg(); 2814 unsigned Lane = MI->getOperand(2).getImm(); 2815 unsigned Fs = MI->getOperand(3).getReg(); 2816 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2817 2818 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2819 .addImm(0) 2820 .addReg(Fs) 2821 .addImm(Mips::sub_lo); 2822 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2823 .addReg(Wd_in) 2824 .addImm(Lane) 2825 .addReg(Wt); 2826 2827 MI->eraseFromParent(); // The pseudo instruction is gone now. 2828 return BB; 2829 } 2830 2831 // Emit the INSERT_FD pseudo instruction. 2832 // 2833 // insert_fd_pseudo $wd, $fs, n 2834 // => 2835 // subreg_to_reg $wt:sub_64, $fs 2836 // insve_d $wd[$n], $wd_in, $wt[0] 2837 MachineBasicBlock * 2838 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, 2839 MachineBasicBlock *BB) const { 2840 assert(Subtarget->isFP64bit()); 2841 2842 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2843 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2844 DebugLoc DL = MI->getDebugLoc(); 2845 unsigned Wd = MI->getOperand(0).getReg(); 2846 unsigned Wd_in = MI->getOperand(1).getReg(); 2847 unsigned Lane = MI->getOperand(2).getImm(); 2848 unsigned Fs = MI->getOperand(3).getReg(); 2849 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2850 2851 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2852 .addImm(0) 2853 .addReg(Fs) 2854 .addImm(Mips::sub_64); 2855 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) 2856 .addReg(Wd_in) 2857 .addImm(Lane) 2858 .addReg(Wt); 2859 2860 MI->eraseFromParent(); // The pseudo instruction is gone now. 2861 return BB; 2862 } 2863 2864 // Emit the FILL_FW pseudo instruction. 2865 // 2866 // fill_fw_pseudo $wd, $fs 2867 // => 2868 // implicit_def $wt1 2869 // insert_subreg $wt2:subreg_lo, $wt1, $fs 2870 // splati.w $wd, $wt2[0] 2871 MachineBasicBlock * 2872 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, 2873 MachineBasicBlock *BB) const { 2874 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2875 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2876 DebugLoc DL = MI->getDebugLoc(); 2877 unsigned Wd = MI->getOperand(0).getReg(); 2878 unsigned Fs = MI->getOperand(1).getReg(); 2879 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2880 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2881 2882 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2883 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2884 .addReg(Wt1) 2885 .addReg(Fs) 2886 .addImm(Mips::sub_lo); 2887 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); 2888 2889 MI->eraseFromParent(); // The pseudo instruction is gone now. 2890 return BB; 2891 } 2892 2893 // Emit the FILL_FD pseudo instruction. 2894 // 2895 // fill_fd_pseudo $wd, $fs 2896 // => 2897 // implicit_def $wt1 2898 // insert_subreg $wt2:subreg_64, $wt1, $fs 2899 // splati.d $wd, $wt2[0] 2900 MachineBasicBlock * 2901 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, 2902 MachineBasicBlock *BB) const { 2903 assert(Subtarget->isFP64bit()); 2904 2905 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2906 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2907 DebugLoc DL = MI->getDebugLoc(); 2908 unsigned Wd = MI->getOperand(0).getReg(); 2909 unsigned Fs = MI->getOperand(1).getReg(); 2910 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2911 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2912 2913 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2914 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2915 .addReg(Wt1) 2916 .addReg(Fs) 2917 .addImm(Mips::sub_64); 2918 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); 2919 2920 MI->eraseFromParent(); // The pseudo instruction is gone now. 2921 return BB; 2922 } 2923 2924 // Emit the FEXP2_W_1 pseudo instructions. 2925 // 2926 // fexp2_w_1_pseudo $wd, $wt 2927 // => 2928 // ldi.w $ws, 1 2929 // fexp2.w $wd, $ws, $wt 2930 MachineBasicBlock * 2931 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, 2932 MachineBasicBlock *BB) const { 2933 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2934 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2935 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; 2936 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 2937 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 2938 DebugLoc DL = MI->getDebugLoc(); 2939 2940 // Splat 1.0 into a vector 2941 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); 2942 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); 2943 2944 // Emit 1.0 * fexp2(Wt) 2945 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg()) 2946 .addReg(Ws2) 2947 .addReg(MI->getOperand(1).getReg()); 2948 2949 MI->eraseFromParent(); // The pseudo instruction is gone now. 2950 return BB; 2951 } 2952 2953 // Emit the FEXP2_D_1 pseudo instructions. 2954 // 2955 // fexp2_d_1_pseudo $wd, $wt 2956 // => 2957 // ldi.d $ws, 1 2958 // fexp2.d $wd, $ws, $wt 2959 MachineBasicBlock * 2960 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, 2961 MachineBasicBlock *BB) const { 2962 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2963 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2964 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; 2965 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 2966 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 2967 DebugLoc DL = MI->getDebugLoc(); 2968 2969 // Splat 1.0 into a vector 2970 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); 2971 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); 2972 2973 // Emit 1.0 * fexp2(Wt) 2974 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg()) 2975 .addReg(Ws2) 2976 .addReg(MI->getOperand(1).getReg()); 2977 2978 MI->eraseFromParent(); // The pseudo instruction is gone now. 2979 return BB; 2980 } 2981