1 //===-- MipsSEISelLowering.cpp - MipsSE DAG Lowering Interface --*- C++ -*-===// 2 // 3 // The LLVM Compiler Infrastructure 4 // 5 // This file is distributed under the University of Illinois Open Source 6 // License. See LICENSE.TXT for details. 7 // 8 //===----------------------------------------------------------------------===// 9 // 10 // Subclass of MipsTargetLowering specialized for mips32/64. 11 // 12 //===----------------------------------------------------------------------===// 13 #define DEBUG_TYPE "mips-isel" 14 #include "MipsSEISelLowering.h" 15 #include "MipsRegisterInfo.h" 16 #include "MipsTargetMachine.h" 17 #include "llvm/CodeGen/MachineInstrBuilder.h" 18 #include "llvm/CodeGen/MachineRegisterInfo.h" 19 #include "llvm/IR/Intrinsics.h" 20 #include "llvm/Support/CommandLine.h" 21 #include "llvm/Support/Debug.h" 22 #include "llvm/Support/raw_ostream.h" 23 #include "llvm/Target/TargetInstrInfo.h" 24 25 using namespace llvm; 26 27 static cl::opt<bool> 28 EnableMipsTailCalls("enable-mips-tail-calls", cl::Hidden, 29 cl::desc("MIPS: Enable tail calls."), cl::init(false)); 30 31 static cl::opt<bool> NoDPLoadStore("mno-ldc1-sdc1", cl::init(false), 32 cl::desc("Expand double precision loads and " 33 "stores to their single precision " 34 "counterparts")); 35 36 MipsSETargetLowering::MipsSETargetLowering(MipsTargetMachine &TM) 37 : MipsTargetLowering(TM) { 38 // Set up the register classes 39 addRegisterClass(MVT::i32, &Mips::GPR32RegClass); 40 41 if (HasMips64) 42 addRegisterClass(MVT::i64, &Mips::GPR64RegClass); 43 44 if (Subtarget->hasDSP() || Subtarget->hasMSA()) { 45 // Expand all truncating stores and extending loads. 46 unsigned FirstVT = (unsigned)MVT::FIRST_VECTOR_VALUETYPE; 47 unsigned LastVT = (unsigned)MVT::LAST_VECTOR_VALUETYPE; 48 49 for (unsigned VT0 = FirstVT; VT0 <= LastVT; ++VT0) { 50 for (unsigned VT1 = FirstVT; VT1 <= LastVT; ++VT1) 51 setTruncStoreAction((MVT::SimpleValueType)VT0, 52 (MVT::SimpleValueType)VT1, Expand); 53 54 setLoadExtAction(ISD::SEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 55 setLoadExtAction(ISD::ZEXTLOAD, (MVT::SimpleValueType)VT0, Expand); 56 setLoadExtAction(ISD::EXTLOAD, (MVT::SimpleValueType)VT0, Expand); 57 } 58 } 59 60 if (Subtarget->hasDSP()) { 61 MVT::SimpleValueType VecTys[2] = {MVT::v2i16, MVT::v4i8}; 62 63 for (unsigned i = 0; i < array_lengthof(VecTys); ++i) { 64 addRegisterClass(VecTys[i], &Mips::DSPRRegClass); 65 66 // Expand all builtin opcodes. 67 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 68 setOperationAction(Opc, VecTys[i], Expand); 69 70 setOperationAction(ISD::ADD, VecTys[i], Legal); 71 setOperationAction(ISD::SUB, VecTys[i], Legal); 72 setOperationAction(ISD::LOAD, VecTys[i], Legal); 73 setOperationAction(ISD::STORE, VecTys[i], Legal); 74 setOperationAction(ISD::BITCAST, VecTys[i], Legal); 75 } 76 77 setTargetDAGCombine(ISD::SHL); 78 setTargetDAGCombine(ISD::SRA); 79 setTargetDAGCombine(ISD::SRL); 80 setTargetDAGCombine(ISD::SETCC); 81 setTargetDAGCombine(ISD::VSELECT); 82 } 83 84 if (Subtarget->hasDSPR2()) 85 setOperationAction(ISD::MUL, MVT::v2i16, Legal); 86 87 if (Subtarget->hasMSA()) { 88 addMSAIntType(MVT::v16i8, &Mips::MSA128BRegClass); 89 addMSAIntType(MVT::v8i16, &Mips::MSA128HRegClass); 90 addMSAIntType(MVT::v4i32, &Mips::MSA128WRegClass); 91 addMSAIntType(MVT::v2i64, &Mips::MSA128DRegClass); 92 addMSAFloatType(MVT::v8f16, &Mips::MSA128HRegClass); 93 addMSAFloatType(MVT::v4f32, &Mips::MSA128WRegClass); 94 addMSAFloatType(MVT::v2f64, &Mips::MSA128DRegClass); 95 96 setTargetDAGCombine(ISD::AND); 97 setTargetDAGCombine(ISD::OR); 98 setTargetDAGCombine(ISD::SRA); 99 setTargetDAGCombine(ISD::VSELECT); 100 setTargetDAGCombine(ISD::XOR); 101 } 102 103 if (!Subtarget->mipsSEUsesSoftFloat()) { 104 addRegisterClass(MVT::f32, &Mips::FGR32RegClass); 105 106 // When dealing with single precision only, use libcalls 107 if (!Subtarget->isSingleFloat()) { 108 if (Subtarget->isFP64bit()) 109 addRegisterClass(MVT::f64, &Mips::FGR64RegClass); 110 else 111 addRegisterClass(MVT::f64, &Mips::AFGR64RegClass); 112 } 113 } 114 115 setOperationAction(ISD::SMUL_LOHI, MVT::i32, Custom); 116 setOperationAction(ISD::UMUL_LOHI, MVT::i32, Custom); 117 setOperationAction(ISD::MULHS, MVT::i32, Custom); 118 setOperationAction(ISD::MULHU, MVT::i32, Custom); 119 120 if (HasMips64) { 121 setOperationAction(ISD::MULHS, MVT::i64, Custom); 122 setOperationAction(ISD::MULHU, MVT::i64, Custom); 123 setOperationAction(ISD::MUL, MVT::i64, Custom); 124 } 125 126 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::i64, Custom); 127 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::i64, Custom); 128 129 setOperationAction(ISD::SDIVREM, MVT::i32, Custom); 130 setOperationAction(ISD::UDIVREM, MVT::i32, Custom); 131 setOperationAction(ISD::SDIVREM, MVT::i64, Custom); 132 setOperationAction(ISD::UDIVREM, MVT::i64, Custom); 133 setOperationAction(ISD::ATOMIC_FENCE, MVT::Other, Custom); 134 setOperationAction(ISD::LOAD, MVT::i32, Custom); 135 setOperationAction(ISD::STORE, MVT::i32, Custom); 136 137 setTargetDAGCombine(ISD::ADDE); 138 setTargetDAGCombine(ISD::SUBE); 139 setTargetDAGCombine(ISD::MUL); 140 141 setOperationAction(ISD::INTRINSIC_WO_CHAIN, MVT::Other, Custom); 142 setOperationAction(ISD::INTRINSIC_W_CHAIN, MVT::Other, Custom); 143 setOperationAction(ISD::INTRINSIC_VOID, MVT::Other, Custom); 144 145 if (NoDPLoadStore) { 146 setOperationAction(ISD::LOAD, MVT::f64, Custom); 147 setOperationAction(ISD::STORE, MVT::f64, Custom); 148 } 149 150 computeRegisterProperties(); 151 } 152 153 const MipsTargetLowering * 154 llvm::createMipsSETargetLowering(MipsTargetMachine &TM) { 155 return new MipsSETargetLowering(TM); 156 } 157 158 // Enable MSA support for the given integer type and Register class. 159 void MipsSETargetLowering:: 160 addMSAIntType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 161 addRegisterClass(Ty, RC); 162 163 // Expand all builtin opcodes. 164 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 165 setOperationAction(Opc, Ty, Expand); 166 167 setOperationAction(ISD::BITCAST, Ty, Legal); 168 setOperationAction(ISD::LOAD, Ty, Legal); 169 setOperationAction(ISD::STORE, Ty, Legal); 170 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Custom); 171 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 172 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 173 174 setOperationAction(ISD::ADD, Ty, Legal); 175 setOperationAction(ISD::AND, Ty, Legal); 176 setOperationAction(ISD::CTLZ, Ty, Legal); 177 setOperationAction(ISD::CTPOP, Ty, Legal); 178 setOperationAction(ISD::MUL, Ty, Legal); 179 setOperationAction(ISD::OR, Ty, Legal); 180 setOperationAction(ISD::SDIV, Ty, Legal); 181 setOperationAction(ISD::SREM, Ty, Legal); 182 setOperationAction(ISD::SHL, Ty, Legal); 183 setOperationAction(ISD::SRA, Ty, Legal); 184 setOperationAction(ISD::SRL, Ty, Legal); 185 setOperationAction(ISD::SUB, Ty, Legal); 186 setOperationAction(ISD::UDIV, Ty, Legal); 187 setOperationAction(ISD::UREM, Ty, Legal); 188 setOperationAction(ISD::VECTOR_SHUFFLE, Ty, Custom); 189 setOperationAction(ISD::VSELECT, Ty, Legal); 190 setOperationAction(ISD::XOR, Ty, Legal); 191 192 if (Ty == MVT::v4i32 || Ty == MVT::v2i64) { 193 setOperationAction(ISD::FP_TO_SINT, Ty, Legal); 194 setOperationAction(ISD::FP_TO_UINT, Ty, Legal); 195 setOperationAction(ISD::SINT_TO_FP, Ty, Legal); 196 setOperationAction(ISD::UINT_TO_FP, Ty, Legal); 197 } 198 199 setOperationAction(ISD::SETCC, Ty, Legal); 200 setCondCodeAction(ISD::SETNE, Ty, Expand); 201 setCondCodeAction(ISD::SETGE, Ty, Expand); 202 setCondCodeAction(ISD::SETGT, Ty, Expand); 203 setCondCodeAction(ISD::SETUGE, Ty, Expand); 204 setCondCodeAction(ISD::SETUGT, Ty, Expand); 205 } 206 207 // Enable MSA support for the given floating-point type and Register class. 208 void MipsSETargetLowering:: 209 addMSAFloatType(MVT::SimpleValueType Ty, const TargetRegisterClass *RC) { 210 addRegisterClass(Ty, RC); 211 212 // Expand all builtin opcodes. 213 for (unsigned Opc = 0; Opc < ISD::BUILTIN_OP_END; ++Opc) 214 setOperationAction(Opc, Ty, Expand); 215 216 setOperationAction(ISD::LOAD, Ty, Legal); 217 setOperationAction(ISD::STORE, Ty, Legal); 218 setOperationAction(ISD::BITCAST, Ty, Legal); 219 setOperationAction(ISD::EXTRACT_VECTOR_ELT, Ty, Legal); 220 setOperationAction(ISD::INSERT_VECTOR_ELT, Ty, Legal); 221 setOperationAction(ISD::BUILD_VECTOR, Ty, Custom); 222 223 if (Ty != MVT::v8f16) { 224 setOperationAction(ISD::FABS, Ty, Legal); 225 setOperationAction(ISD::FADD, Ty, Legal); 226 setOperationAction(ISD::FDIV, Ty, Legal); 227 setOperationAction(ISD::FEXP2, Ty, Legal); 228 setOperationAction(ISD::FLOG2, Ty, Legal); 229 setOperationAction(ISD::FMA, Ty, Legal); 230 setOperationAction(ISD::FMUL, Ty, Legal); 231 setOperationAction(ISD::FRINT, Ty, Legal); 232 setOperationAction(ISD::FSQRT, Ty, Legal); 233 setOperationAction(ISD::FSUB, Ty, Legal); 234 setOperationAction(ISD::VSELECT, Ty, Legal); 235 236 setOperationAction(ISD::SETCC, Ty, Legal); 237 setCondCodeAction(ISD::SETOGE, Ty, Expand); 238 setCondCodeAction(ISD::SETOGT, Ty, Expand); 239 setCondCodeAction(ISD::SETUGE, Ty, Expand); 240 setCondCodeAction(ISD::SETUGT, Ty, Expand); 241 setCondCodeAction(ISD::SETGE, Ty, Expand); 242 setCondCodeAction(ISD::SETGT, Ty, Expand); 243 } 244 } 245 246 bool 247 MipsSETargetLowering::allowsUnalignedMemoryAccesses(EVT VT, bool *Fast) const { 248 MVT::SimpleValueType SVT = VT.getSimpleVT().SimpleTy; 249 250 switch (SVT) { 251 case MVT::i64: 252 case MVT::i32: 253 if (Fast) 254 *Fast = true; 255 return true; 256 default: 257 return false; 258 } 259 } 260 261 SDValue MipsSETargetLowering::LowerOperation(SDValue Op, 262 SelectionDAG &DAG) const { 263 switch(Op.getOpcode()) { 264 case ISD::LOAD: return lowerLOAD(Op, DAG); 265 case ISD::STORE: return lowerSTORE(Op, DAG); 266 case ISD::SMUL_LOHI: return lowerMulDiv(Op, MipsISD::Mult, true, true, DAG); 267 case ISD::UMUL_LOHI: return lowerMulDiv(Op, MipsISD::Multu, true, true, DAG); 268 case ISD::MULHS: return lowerMulDiv(Op, MipsISD::Mult, false, true, DAG); 269 case ISD::MULHU: return lowerMulDiv(Op, MipsISD::Multu, false, true, DAG); 270 case ISD::MUL: return lowerMulDiv(Op, MipsISD::Mult, true, false, DAG); 271 case ISD::SDIVREM: return lowerMulDiv(Op, MipsISD::DivRem, true, true, DAG); 272 case ISD::UDIVREM: return lowerMulDiv(Op, MipsISD::DivRemU, true, true, 273 DAG); 274 case ISD::INTRINSIC_WO_CHAIN: return lowerINTRINSIC_WO_CHAIN(Op, DAG); 275 case ISD::INTRINSIC_W_CHAIN: return lowerINTRINSIC_W_CHAIN(Op, DAG); 276 case ISD::INTRINSIC_VOID: return lowerINTRINSIC_VOID(Op, DAG); 277 case ISD::EXTRACT_VECTOR_ELT: return lowerEXTRACT_VECTOR_ELT(Op, DAG); 278 case ISD::BUILD_VECTOR: return lowerBUILD_VECTOR(Op, DAG); 279 case ISD::VECTOR_SHUFFLE: return lowerVECTOR_SHUFFLE(Op, DAG); 280 } 281 282 return MipsTargetLowering::LowerOperation(Op, DAG); 283 } 284 285 // selectMADD - 286 // Transforms a subgraph in CurDAG if the following pattern is found: 287 // (addc multLo, Lo0), (adde multHi, Hi0), 288 // where, 289 // multHi/Lo: product of multiplication 290 // Lo0: initial value of Lo register 291 // Hi0: initial value of Hi register 292 // Return true if pattern matching was successful. 293 static bool selectMADD(SDNode *ADDENode, SelectionDAG *CurDAG) { 294 // ADDENode's second operand must be a flag output of an ADDC node in order 295 // for the matching to be successful. 296 SDNode *ADDCNode = ADDENode->getOperand(2).getNode(); 297 298 if (ADDCNode->getOpcode() != ISD::ADDC) 299 return false; 300 301 SDValue MultHi = ADDENode->getOperand(0); 302 SDValue MultLo = ADDCNode->getOperand(0); 303 SDNode *MultNode = MultHi.getNode(); 304 unsigned MultOpc = MultHi.getOpcode(); 305 306 // MultHi and MultLo must be generated by the same node, 307 if (MultLo.getNode() != MultNode) 308 return false; 309 310 // and it must be a multiplication. 311 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 312 return false; 313 314 // MultLo amd MultHi must be the first and second output of MultNode 315 // respectively. 316 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 317 return false; 318 319 // Transform this to a MADD only if ADDENode and ADDCNode are the only users 320 // of the values of MultNode, in which case MultNode will be removed in later 321 // phases. 322 // If there exist users other than ADDENode or ADDCNode, this function returns 323 // here, which will result in MultNode being mapped to a single MULT 324 // instruction node rather than a pair of MULT and MADD instructions being 325 // produced. 326 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 327 return false; 328 329 SDLoc DL(ADDENode); 330 331 // Initialize accumulator. 332 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 333 ADDCNode->getOperand(1), 334 ADDENode->getOperand(1)); 335 336 // create MipsMAdd(u) node 337 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MAddu : MipsISD::MAdd; 338 339 SDValue MAdd = CurDAG->getNode(MultOpc, DL, MVT::Untyped, 340 MultNode->getOperand(0),// Factor 0 341 MultNode->getOperand(1),// Factor 1 342 ACCIn); 343 344 // replace uses of adde and addc here 345 if (!SDValue(ADDCNode, 0).use_empty()) { 346 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MAdd); 347 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDCNode, 0), LoOut); 348 } 349 if (!SDValue(ADDENode, 0).use_empty()) { 350 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MAdd); 351 CurDAG->ReplaceAllUsesOfValueWith(SDValue(ADDENode, 0), HiOut); 352 } 353 354 return true; 355 } 356 357 // selectMSUB - 358 // Transforms a subgraph in CurDAG if the following pattern is found: 359 // (addc Lo0, multLo), (sube Hi0, multHi), 360 // where, 361 // multHi/Lo: product of multiplication 362 // Lo0: initial value of Lo register 363 // Hi0: initial value of Hi register 364 // Return true if pattern matching was successful. 365 static bool selectMSUB(SDNode *SUBENode, SelectionDAG *CurDAG) { 366 // SUBENode's second operand must be a flag output of an SUBC node in order 367 // for the matching to be successful. 368 SDNode *SUBCNode = SUBENode->getOperand(2).getNode(); 369 370 if (SUBCNode->getOpcode() != ISD::SUBC) 371 return false; 372 373 SDValue MultHi = SUBENode->getOperand(1); 374 SDValue MultLo = SUBCNode->getOperand(1); 375 SDNode *MultNode = MultHi.getNode(); 376 unsigned MultOpc = MultHi.getOpcode(); 377 378 // MultHi and MultLo must be generated by the same node, 379 if (MultLo.getNode() != MultNode) 380 return false; 381 382 // and it must be a multiplication. 383 if (MultOpc != ISD::SMUL_LOHI && MultOpc != ISD::UMUL_LOHI) 384 return false; 385 386 // MultLo amd MultHi must be the first and second output of MultNode 387 // respectively. 388 if (MultHi.getResNo() != 1 || MultLo.getResNo() != 0) 389 return false; 390 391 // Transform this to a MSUB only if SUBENode and SUBCNode are the only users 392 // of the values of MultNode, in which case MultNode will be removed in later 393 // phases. 394 // If there exist users other than SUBENode or SUBCNode, this function returns 395 // here, which will result in MultNode being mapped to a single MULT 396 // instruction node rather than a pair of MULT and MSUB instructions being 397 // produced. 398 if (!MultHi.hasOneUse() || !MultLo.hasOneUse()) 399 return false; 400 401 SDLoc DL(SUBENode); 402 403 // Initialize accumulator. 404 SDValue ACCIn = CurDAG->getNode(MipsISD::MTLOHI, DL, MVT::Untyped, 405 SUBCNode->getOperand(0), 406 SUBENode->getOperand(0)); 407 408 // create MipsSub(u) node 409 MultOpc = MultOpc == ISD::UMUL_LOHI ? MipsISD::MSubu : MipsISD::MSub; 410 411 SDValue MSub = CurDAG->getNode(MultOpc, DL, MVT::Glue, 412 MultNode->getOperand(0),// Factor 0 413 MultNode->getOperand(1),// Factor 1 414 ACCIn); 415 416 // replace uses of sube and subc here 417 if (!SDValue(SUBCNode, 0).use_empty()) { 418 SDValue LoOut = CurDAG->getNode(MipsISD::MFLO, DL, MVT::i32, MSub); 419 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBCNode, 0), LoOut); 420 } 421 if (!SDValue(SUBENode, 0).use_empty()) { 422 SDValue HiOut = CurDAG->getNode(MipsISD::MFHI, DL, MVT::i32, MSub); 423 CurDAG->ReplaceAllUsesOfValueWith(SDValue(SUBENode, 0), HiOut); 424 } 425 426 return true; 427 } 428 429 static SDValue performADDECombine(SDNode *N, SelectionDAG &DAG, 430 TargetLowering::DAGCombinerInfo &DCI, 431 const MipsSubtarget *Subtarget) { 432 if (DCI.isBeforeLegalize()) 433 return SDValue(); 434 435 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 436 selectMADD(N, &DAG)) 437 return SDValue(N, 0); 438 439 return SDValue(); 440 } 441 442 // Fold zero extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT 443 // 444 // Performs the following transformations: 445 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to zero extension if its 446 // sign/zero-extension is completely overwritten by the new one performed by 447 // the ISD::AND. 448 // - Removes redundant zero extensions performed by an ISD::AND. 449 static SDValue performANDCombine(SDNode *N, SelectionDAG &DAG, 450 TargetLowering::DAGCombinerInfo &DCI, 451 const MipsSubtarget *Subtarget) { 452 if (!Subtarget->hasMSA()) 453 return SDValue(); 454 455 SDValue Op0 = N->getOperand(0); 456 SDValue Op1 = N->getOperand(1); 457 unsigned Op0Opcode = Op0->getOpcode(); 458 459 // (and (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d) 460 // where $d + 1 == 2^n and n == 32 461 // or $d + 1 == 2^n and n <= 32 and ZExt 462 // -> (MipsVExtractZExt $a, $b, $c) 463 if (Op0Opcode == MipsISD::VEXTRACT_SEXT_ELT || 464 Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT) { 465 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Op1); 466 467 if (!Mask) 468 return SDValue(); 469 470 int32_t Log2IfPositive = (Mask->getAPIntValue() + 1).exactLogBase2(); 471 472 if (Log2IfPositive <= 0) 473 return SDValue(); // Mask+1 is not a power of 2 474 475 SDValue Op0Op2 = Op0->getOperand(2); 476 EVT ExtendTy = cast<VTSDNode>(Op0Op2)->getVT(); 477 unsigned ExtendTySize = ExtendTy.getSizeInBits(); 478 unsigned Log2 = Log2IfPositive; 479 480 if ((Op0Opcode == MipsISD::VEXTRACT_ZEXT_ELT && Log2 >= ExtendTySize) || 481 Log2 == ExtendTySize) { 482 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; 483 DAG.MorphNodeTo(Op0.getNode(), MipsISD::VEXTRACT_ZEXT_ELT, 484 Op0->getVTList(), Ops, Op0->getNumOperands()); 485 return Op0; 486 } 487 } 488 489 return SDValue(); 490 } 491 492 // Determine if the specified node is a constant vector splat. 493 // 494 // Returns true and sets Imm if: 495 // * N is a ISD::BUILD_VECTOR representing a constant splat 496 // 497 // This function is quite similar to MipsSEDAGToDAGISel::selectVSplat. The 498 // differences are that it assumes the MSA has already been checked and the 499 // arbitrary requirement for a maximum of 32-bit integers isn't applied (and 500 // must not be in order for binsri.d to be selectable). 501 static bool isVSplat(SDValue N, APInt &Imm, bool IsLittleEndian) { 502 BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N.getNode()); 503 504 if (Node == NULL) 505 return false; 506 507 APInt SplatValue, SplatUndef; 508 unsigned SplatBitSize; 509 bool HasAnyUndefs; 510 511 if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 512 8, !IsLittleEndian)) 513 return false; 514 515 Imm = SplatValue; 516 517 return true; 518 } 519 520 // Test whether the given node is an all-ones build_vector. 521 static bool isVectorAllOnes(SDValue N) { 522 // Look through bitcasts. Endianness doesn't matter because we are looking 523 // for an all-ones value. 524 if (N->getOpcode() == ISD::BITCAST) 525 N = N->getOperand(0); 526 527 BuildVectorSDNode *BVN = dyn_cast<BuildVectorSDNode>(N); 528 529 if (!BVN) 530 return false; 531 532 APInt SplatValue, SplatUndef; 533 unsigned SplatBitSize; 534 bool HasAnyUndefs; 535 536 // Endianness doesn't matter in this context because we are looking for 537 // an all-ones value. 538 if (BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs)) 539 return SplatValue.isAllOnesValue(); 540 541 return false; 542 } 543 544 // Test whether N is the bitwise inverse of OfNode. 545 static bool isBitwiseInverse(SDValue N, SDValue OfNode) { 546 if (N->getOpcode() != ISD::XOR) 547 return false; 548 549 if (isVectorAllOnes(N->getOperand(0))) 550 return N->getOperand(1) == OfNode; 551 552 if (isVectorAllOnes(N->getOperand(1))) 553 return N->getOperand(0) == OfNode; 554 555 return false; 556 } 557 558 // Perform combines where ISD::OR is the root node. 559 // 560 // Performs the following transformations: 561 // - (or (and $a, $mask), (and $b, $inv_mask)) => (vselect $mask, $a, $b) 562 // where $inv_mask is the bitwise inverse of $mask and the 'or' has a 128-bit 563 // vector type. 564 static SDValue performORCombine(SDNode *N, SelectionDAG &DAG, 565 TargetLowering::DAGCombinerInfo &DCI, 566 const MipsSubtarget *Subtarget) { 567 if (!Subtarget->hasMSA()) 568 return SDValue(); 569 570 EVT Ty = N->getValueType(0); 571 572 if (!Ty.is128BitVector()) 573 return SDValue(); 574 575 SDValue Op0 = N->getOperand(0); 576 SDValue Op1 = N->getOperand(1); 577 578 if (Op0->getOpcode() == ISD::AND && Op1->getOpcode() == ISD::AND) { 579 SDValue Op0Op0 = Op0->getOperand(0); 580 SDValue Op0Op1 = Op0->getOperand(1); 581 SDValue Op1Op0 = Op1->getOperand(0); 582 SDValue Op1Op1 = Op1->getOperand(1); 583 bool IsLittleEndian = !Subtarget->isLittle(); 584 585 SDValue IfSet, IfClr, Cond; 586 bool IsConstantMask = false; 587 APInt Mask, InvMask; 588 589 // If Op0Op0 is an appropriate mask, try to find it's inverse in either 590 // Op1Op0, or Op1Op1. Keep track of the Cond, IfSet, and IfClr nodes, while 591 // looking. 592 // IfClr will be set if we find a valid match. 593 if (isVSplat(Op0Op0, Mask, IsLittleEndian)) { 594 Cond = Op0Op0; 595 IfSet = Op0Op1; 596 597 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && 598 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 599 IfClr = Op1Op1; 600 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && 601 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 602 IfClr = Op1Op0; 603 604 IsConstantMask = true; 605 } 606 607 // If IfClr is not yet set, and Op0Op1 is an appropriate mask, try the same 608 // thing again using this mask. 609 // IfClr will be set if we find a valid match. 610 if (!IfClr.getNode() && isVSplat(Op0Op1, Mask, IsLittleEndian)) { 611 Cond = Op0Op1; 612 IfSet = Op0Op0; 613 614 if (isVSplat(Op1Op0, InvMask, IsLittleEndian) && 615 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 616 IfClr = Op1Op1; 617 else if (isVSplat(Op1Op1, InvMask, IsLittleEndian) && 618 Mask.getBitWidth() == InvMask.getBitWidth() && Mask == ~InvMask) 619 IfClr = Op1Op0; 620 621 IsConstantMask = true; 622 } 623 624 // If IfClr is not yet set, try looking for a non-constant match. 625 // IfClr will be set if we find a valid match amongst the eight 626 // possibilities. 627 if (!IfClr.getNode()) { 628 if (isBitwiseInverse(Op0Op0, Op1Op0)) { 629 Cond = Op1Op0; 630 IfSet = Op1Op1; 631 IfClr = Op0Op1; 632 } else if (isBitwiseInverse(Op0Op1, Op1Op0)) { 633 Cond = Op1Op0; 634 IfSet = Op1Op1; 635 IfClr = Op0Op0; 636 } else if (isBitwiseInverse(Op0Op0, Op1Op1)) { 637 Cond = Op1Op1; 638 IfSet = Op1Op0; 639 IfClr = Op0Op1; 640 } else if (isBitwiseInverse(Op0Op1, Op1Op1)) { 641 Cond = Op1Op1; 642 IfSet = Op1Op0; 643 IfClr = Op0Op0; 644 } else if (isBitwiseInverse(Op1Op0, Op0Op0)) { 645 Cond = Op0Op0; 646 IfSet = Op0Op1; 647 IfClr = Op1Op1; 648 } else if (isBitwiseInverse(Op1Op1, Op0Op0)) { 649 Cond = Op0Op0; 650 IfSet = Op0Op1; 651 IfClr = Op1Op0; 652 } else if (isBitwiseInverse(Op1Op0, Op0Op1)) { 653 Cond = Op0Op1; 654 IfSet = Op0Op0; 655 IfClr = Op1Op1; 656 } else if (isBitwiseInverse(Op1Op1, Op0Op1)) { 657 Cond = Op0Op1; 658 IfSet = Op0Op0; 659 IfClr = Op1Op0; 660 } 661 } 662 663 // At this point, IfClr will be set if we have a valid match. 664 if (!IfClr.getNode()) 665 return SDValue(); 666 667 assert(Cond.getNode() && IfSet.getNode()); 668 669 // Fold degenerate cases. 670 if (IsConstantMask) { 671 if (Mask.isAllOnesValue()) 672 return IfSet; 673 else if (Mask == 0) 674 return IfClr; 675 } 676 677 // Transform the DAG into an equivalent VSELECT. 678 return DAG.getNode(ISD::VSELECT, SDLoc(N), Ty, Cond, IfClr, IfSet); 679 } 680 681 return SDValue(); 682 } 683 684 static SDValue performSUBECombine(SDNode *N, SelectionDAG &DAG, 685 TargetLowering::DAGCombinerInfo &DCI, 686 const MipsSubtarget *Subtarget) { 687 if (DCI.isBeforeLegalize()) 688 return SDValue(); 689 690 if (Subtarget->hasMips32() && N->getValueType(0) == MVT::i32 && 691 selectMSUB(N, &DAG)) 692 return SDValue(N, 0); 693 694 return SDValue(); 695 } 696 697 static SDValue genConstMult(SDValue X, uint64_t C, SDLoc DL, EVT VT, 698 EVT ShiftTy, SelectionDAG &DAG) { 699 // Clear the upper (64 - VT.sizeInBits) bits. 700 C &= ((uint64_t)-1) >> (64 - VT.getSizeInBits()); 701 702 // Return 0. 703 if (C == 0) 704 return DAG.getConstant(0, VT); 705 706 // Return x. 707 if (C == 1) 708 return X; 709 710 // If c is power of 2, return (shl x, log2(c)). 711 if (isPowerOf2_64(C)) 712 return DAG.getNode(ISD::SHL, DL, VT, X, 713 DAG.getConstant(Log2_64(C), ShiftTy)); 714 715 unsigned Log2Ceil = Log2_64_Ceil(C); 716 uint64_t Floor = 1LL << Log2_64(C); 717 uint64_t Ceil = Log2Ceil == 64 ? 0LL : 1LL << Log2Ceil; 718 719 // If |c - floor_c| <= |c - ceil_c|, 720 // where floor_c = pow(2, floor(log2(c))) and ceil_c = pow(2, ceil(log2(c))), 721 // return (add constMult(x, floor_c), constMult(x, c - floor_c)). 722 if (C - Floor <= Ceil - C) { 723 SDValue Op0 = genConstMult(X, Floor, DL, VT, ShiftTy, DAG); 724 SDValue Op1 = genConstMult(X, C - Floor, DL, VT, ShiftTy, DAG); 725 return DAG.getNode(ISD::ADD, DL, VT, Op0, Op1); 726 } 727 728 // If |c - floor_c| > |c - ceil_c|, 729 // return (sub constMult(x, ceil_c), constMult(x, ceil_c - c)). 730 SDValue Op0 = genConstMult(X, Ceil, DL, VT, ShiftTy, DAG); 731 SDValue Op1 = genConstMult(X, Ceil - C, DL, VT, ShiftTy, DAG); 732 return DAG.getNode(ISD::SUB, DL, VT, Op0, Op1); 733 } 734 735 static SDValue performMULCombine(SDNode *N, SelectionDAG &DAG, 736 const TargetLowering::DAGCombinerInfo &DCI, 737 const MipsSETargetLowering *TL) { 738 EVT VT = N->getValueType(0); 739 740 if (ConstantSDNode *C = dyn_cast<ConstantSDNode>(N->getOperand(1))) 741 if (!VT.isVector()) 742 return genConstMult(N->getOperand(0), C->getZExtValue(), SDLoc(N), 743 VT, TL->getScalarShiftAmountTy(VT), DAG); 744 745 return SDValue(N, 0); 746 } 747 748 static SDValue performDSPShiftCombine(unsigned Opc, SDNode *N, EVT Ty, 749 SelectionDAG &DAG, 750 const MipsSubtarget *Subtarget) { 751 // See if this is a vector splat immediate node. 752 APInt SplatValue, SplatUndef; 753 unsigned SplatBitSize; 754 bool HasAnyUndefs; 755 unsigned EltSize = Ty.getVectorElementType().getSizeInBits(); 756 BuildVectorSDNode *BV = dyn_cast<BuildVectorSDNode>(N->getOperand(1)); 757 758 if (!Subtarget->hasDSP()) 759 return SDValue(); 760 761 if (!BV || 762 !BV->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, HasAnyUndefs, 763 EltSize, !Subtarget->isLittle()) || 764 (SplatBitSize != EltSize) || 765 (SplatValue.getZExtValue() >= EltSize)) 766 return SDValue(); 767 768 return DAG.getNode(Opc, SDLoc(N), Ty, N->getOperand(0), 769 DAG.getConstant(SplatValue.getZExtValue(), MVT::i32)); 770 } 771 772 static SDValue performSHLCombine(SDNode *N, SelectionDAG &DAG, 773 TargetLowering::DAGCombinerInfo &DCI, 774 const MipsSubtarget *Subtarget) { 775 EVT Ty = N->getValueType(0); 776 777 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 778 return SDValue(); 779 780 return performDSPShiftCombine(MipsISD::SHLL_DSP, N, Ty, DAG, Subtarget); 781 } 782 783 // Fold sign-extensions into MipsISD::VEXTRACT_[SZ]EXT_ELT for MSA and fold 784 // constant splats into MipsISD::SHRA_DSP for DSPr2. 785 // 786 // Performs the following transformations: 787 // - Changes MipsISD::VEXTRACT_[SZ]EXT_ELT to sign extension if its 788 // sign/zero-extension is completely overwritten by the new one performed by 789 // the ISD::SRA and ISD::SHL nodes. 790 // - Removes redundant sign extensions performed by an ISD::SRA and ISD::SHL 791 // sequence. 792 // 793 // See performDSPShiftCombine for more information about the transformation 794 // used for DSPr2. 795 static SDValue performSRACombine(SDNode *N, SelectionDAG &DAG, 796 TargetLowering::DAGCombinerInfo &DCI, 797 const MipsSubtarget *Subtarget) { 798 EVT Ty = N->getValueType(0); 799 800 if (Subtarget->hasMSA()) { 801 SDValue Op0 = N->getOperand(0); 802 SDValue Op1 = N->getOperand(1); 803 804 // (sra (shl (MipsVExtract[SZ]Ext $a, $b, $c), imm:$d), imm:$d) 805 // where $d + sizeof($c) == 32 806 // or $d + sizeof($c) <= 32 and SExt 807 // -> (MipsVExtractSExt $a, $b, $c) 808 if (Op0->getOpcode() == ISD::SHL && Op1 == Op0->getOperand(1)) { 809 SDValue Op0Op0 = Op0->getOperand(0); 810 ConstantSDNode *ShAmount = dyn_cast<ConstantSDNode>(Op1); 811 812 if (!ShAmount) 813 return SDValue(); 814 815 if (Op0Op0->getOpcode() != MipsISD::VEXTRACT_SEXT_ELT && 816 Op0Op0->getOpcode() != MipsISD::VEXTRACT_ZEXT_ELT) 817 return SDValue(); 818 819 EVT ExtendTy = cast<VTSDNode>(Op0Op0->getOperand(2))->getVT(); 820 unsigned TotalBits = ShAmount->getZExtValue() + ExtendTy.getSizeInBits(); 821 822 if (TotalBits == 32 || 823 (Op0Op0->getOpcode() == MipsISD::VEXTRACT_SEXT_ELT && 824 TotalBits <= 32)) { 825 SDValue Ops[] = { Op0Op0->getOperand(0), Op0Op0->getOperand(1), 826 Op0Op0->getOperand(2) }; 827 DAG.MorphNodeTo(Op0Op0.getNode(), MipsISD::VEXTRACT_SEXT_ELT, 828 Op0Op0->getVTList(), Ops, Op0Op0->getNumOperands()); 829 return Op0Op0; 830 } 831 } 832 } 833 834 if ((Ty != MVT::v2i16) && ((Ty != MVT::v4i8) || !Subtarget->hasDSPR2())) 835 return SDValue(); 836 837 return performDSPShiftCombine(MipsISD::SHRA_DSP, N, Ty, DAG, Subtarget); 838 } 839 840 841 static SDValue performSRLCombine(SDNode *N, SelectionDAG &DAG, 842 TargetLowering::DAGCombinerInfo &DCI, 843 const MipsSubtarget *Subtarget) { 844 EVT Ty = N->getValueType(0); 845 846 if (((Ty != MVT::v2i16) || !Subtarget->hasDSPR2()) && (Ty != MVT::v4i8)) 847 return SDValue(); 848 849 return performDSPShiftCombine(MipsISD::SHRL_DSP, N, Ty, DAG, Subtarget); 850 } 851 852 static bool isLegalDSPCondCode(EVT Ty, ISD::CondCode CC) { 853 bool IsV216 = (Ty == MVT::v2i16); 854 855 switch (CC) { 856 case ISD::SETEQ: 857 case ISD::SETNE: return true; 858 case ISD::SETLT: 859 case ISD::SETLE: 860 case ISD::SETGT: 861 case ISD::SETGE: return IsV216; 862 case ISD::SETULT: 863 case ISD::SETULE: 864 case ISD::SETUGT: 865 case ISD::SETUGE: return !IsV216; 866 default: return false; 867 } 868 } 869 870 static SDValue performSETCCCombine(SDNode *N, SelectionDAG &DAG) { 871 EVT Ty = N->getValueType(0); 872 873 if ((Ty != MVT::v2i16) && (Ty != MVT::v4i8)) 874 return SDValue(); 875 876 if (!isLegalDSPCondCode(Ty, cast<CondCodeSDNode>(N->getOperand(2))->get())) 877 return SDValue(); 878 879 return DAG.getNode(MipsISD::SETCC_DSP, SDLoc(N), Ty, N->getOperand(0), 880 N->getOperand(1), N->getOperand(2)); 881 } 882 883 static SDValue performVSELECTCombine(SDNode *N, SelectionDAG &DAG) { 884 EVT Ty = N->getValueType(0); 885 886 if (Ty.is128BitVector() && Ty.isInteger()) { 887 // Try the following combines: 888 // (vselect (setcc $a, $b, SETLT), $b, $a)) -> (vsmax $a, $b) 889 // (vselect (setcc $a, $b, SETLE), $b, $a)) -> (vsmax $a, $b) 890 // (vselect (setcc $a, $b, SETLT), $a, $b)) -> (vsmin $a, $b) 891 // (vselect (setcc $a, $b, SETLE), $a, $b)) -> (vsmin $a, $b) 892 // (vselect (setcc $a, $b, SETULT), $b, $a)) -> (vumax $a, $b) 893 // (vselect (setcc $a, $b, SETULE), $b, $a)) -> (vumax $a, $b) 894 // (vselect (setcc $a, $b, SETULT), $a, $b)) -> (vumin $a, $b) 895 // (vselect (setcc $a, $b, SETULE), $a, $b)) -> (vumin $a, $b) 896 // SETGT/SETGE/SETUGT/SETUGE variants of these will show up initially but 897 // will be expanded to equivalent SETLT/SETLE/SETULT/SETULE versions by the 898 // legalizer. 899 SDValue Op0 = N->getOperand(0); 900 901 if (Op0->getOpcode() != ISD::SETCC) 902 return SDValue(); 903 904 ISD::CondCode CondCode = cast<CondCodeSDNode>(Op0->getOperand(2))->get(); 905 bool Signed; 906 907 if (CondCode == ISD::SETLT || CondCode == ISD::SETLE) 908 Signed = true; 909 else if (CondCode == ISD::SETULT || CondCode == ISD::SETULE) 910 Signed = false; 911 else 912 return SDValue(); 913 914 SDValue Op1 = N->getOperand(1); 915 SDValue Op2 = N->getOperand(2); 916 SDValue Op0Op0 = Op0->getOperand(0); 917 SDValue Op0Op1 = Op0->getOperand(1); 918 919 if (Op1 == Op0Op0 && Op2 == Op0Op1) 920 return DAG.getNode(Signed ? MipsISD::VSMIN : MipsISD::VUMIN, SDLoc(N), 921 Ty, Op1, Op2); 922 else if (Op1 == Op0Op1 && Op2 == Op0Op0) 923 return DAG.getNode(Signed ? MipsISD::VSMAX : MipsISD::VUMAX, SDLoc(N), 924 Ty, Op1, Op2); 925 } else if ((Ty == MVT::v2i16) || (Ty == MVT::v4i8)) { 926 SDValue SetCC = N->getOperand(0); 927 928 if (SetCC.getOpcode() != MipsISD::SETCC_DSP) 929 return SDValue(); 930 931 return DAG.getNode(MipsISD::SELECT_CC_DSP, SDLoc(N), Ty, 932 SetCC.getOperand(0), SetCC.getOperand(1), 933 N->getOperand(1), N->getOperand(2), SetCC.getOperand(2)); 934 } 935 936 return SDValue(); 937 } 938 939 static SDValue performXORCombine(SDNode *N, SelectionDAG &DAG, 940 const MipsSubtarget *Subtarget) { 941 EVT Ty = N->getValueType(0); 942 943 if (Subtarget->hasMSA() && Ty.is128BitVector() && Ty.isInteger()) { 944 // Try the following combines: 945 // (xor (or $a, $b), (build_vector allones)) 946 // (xor (or $a, $b), (bitcast (build_vector allones))) 947 SDValue Op0 = N->getOperand(0); 948 SDValue Op1 = N->getOperand(1); 949 SDValue NotOp; 950 951 if (ISD::isBuildVectorAllOnes(Op0.getNode())) 952 NotOp = Op1; 953 else if (ISD::isBuildVectorAllOnes(Op1.getNode())) 954 NotOp = Op0; 955 else 956 return SDValue(); 957 958 if (NotOp->getOpcode() == ISD::OR) 959 return DAG.getNode(MipsISD::VNOR, SDLoc(N), Ty, NotOp->getOperand(0), 960 NotOp->getOperand(1)); 961 } 962 963 return SDValue(); 964 } 965 966 SDValue 967 MipsSETargetLowering::PerformDAGCombine(SDNode *N, DAGCombinerInfo &DCI) const { 968 SelectionDAG &DAG = DCI.DAG; 969 SDValue Val; 970 971 switch (N->getOpcode()) { 972 case ISD::ADDE: 973 return performADDECombine(N, DAG, DCI, Subtarget); 974 case ISD::AND: 975 Val = performANDCombine(N, DAG, DCI, Subtarget); 976 break; 977 case ISD::OR: 978 Val = performORCombine(N, DAG, DCI, Subtarget); 979 break; 980 case ISD::SUBE: 981 return performSUBECombine(N, DAG, DCI, Subtarget); 982 case ISD::MUL: 983 return performMULCombine(N, DAG, DCI, this); 984 case ISD::SHL: 985 return performSHLCombine(N, DAG, DCI, Subtarget); 986 case ISD::SRA: 987 return performSRACombine(N, DAG, DCI, Subtarget); 988 case ISD::SRL: 989 return performSRLCombine(N, DAG, DCI, Subtarget); 990 case ISD::VSELECT: 991 return performVSELECTCombine(N, DAG); 992 case ISD::XOR: 993 Val = performXORCombine(N, DAG, Subtarget); 994 break; 995 case ISD::SETCC: 996 Val = performSETCCCombine(N, DAG); 997 break; 998 } 999 1000 if (Val.getNode()) { 1001 DEBUG(dbgs() << "\nMipsSE DAG Combine:\n"; 1002 N->printrWithDepth(dbgs(), &DAG); 1003 dbgs() << "\n=> \n"; 1004 Val.getNode()->printrWithDepth(dbgs(), &DAG); 1005 dbgs() << "\n"); 1006 return Val; 1007 } 1008 1009 return MipsTargetLowering::PerformDAGCombine(N, DCI); 1010 } 1011 1012 MachineBasicBlock * 1013 MipsSETargetLowering::EmitInstrWithCustomInserter(MachineInstr *MI, 1014 MachineBasicBlock *BB) const { 1015 switch (MI->getOpcode()) { 1016 default: 1017 return MipsTargetLowering::EmitInstrWithCustomInserter(MI, BB); 1018 case Mips::BPOSGE32_PSEUDO: 1019 return emitBPOSGE32(MI, BB); 1020 case Mips::SNZ_B_PSEUDO: 1021 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_B); 1022 case Mips::SNZ_H_PSEUDO: 1023 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_H); 1024 case Mips::SNZ_W_PSEUDO: 1025 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_W); 1026 case Mips::SNZ_D_PSEUDO: 1027 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_D); 1028 case Mips::SNZ_V_PSEUDO: 1029 return emitMSACBranchPseudo(MI, BB, Mips::BNZ_V); 1030 case Mips::SZ_B_PSEUDO: 1031 return emitMSACBranchPseudo(MI, BB, Mips::BZ_B); 1032 case Mips::SZ_H_PSEUDO: 1033 return emitMSACBranchPseudo(MI, BB, Mips::BZ_H); 1034 case Mips::SZ_W_PSEUDO: 1035 return emitMSACBranchPseudo(MI, BB, Mips::BZ_W); 1036 case Mips::SZ_D_PSEUDO: 1037 return emitMSACBranchPseudo(MI, BB, Mips::BZ_D); 1038 case Mips::SZ_V_PSEUDO: 1039 return emitMSACBranchPseudo(MI, BB, Mips::BZ_V); 1040 case Mips::COPY_FW_PSEUDO: 1041 return emitCOPY_FW(MI, BB); 1042 case Mips::COPY_FD_PSEUDO: 1043 return emitCOPY_FD(MI, BB); 1044 case Mips::INSERT_FW_PSEUDO: 1045 return emitINSERT_FW(MI, BB); 1046 case Mips::INSERT_FD_PSEUDO: 1047 return emitINSERT_FD(MI, BB); 1048 case Mips::FILL_FW_PSEUDO: 1049 return emitFILL_FW(MI, BB); 1050 case Mips::FILL_FD_PSEUDO: 1051 return emitFILL_FD(MI, BB); 1052 case Mips::FEXP2_W_1_PSEUDO: 1053 return emitFEXP2_W_1(MI, BB); 1054 case Mips::FEXP2_D_1_PSEUDO: 1055 return emitFEXP2_D_1(MI, BB); 1056 } 1057 } 1058 1059 bool MipsSETargetLowering:: 1060 isEligibleForTailCallOptimization(const MipsCC &MipsCCInfo, 1061 unsigned NextStackOffset, 1062 const MipsFunctionInfo& FI) const { 1063 if (!EnableMipsTailCalls) 1064 return false; 1065 1066 // Return false if either the callee or caller has a byval argument. 1067 if (MipsCCInfo.hasByValArg() || FI.hasByvalArg()) 1068 return false; 1069 1070 // Return true if the callee's argument area is no larger than the 1071 // caller's. 1072 return NextStackOffset <= FI.getIncomingArgSize(); 1073 } 1074 1075 void MipsSETargetLowering:: 1076 getOpndList(SmallVectorImpl<SDValue> &Ops, 1077 std::deque< std::pair<unsigned, SDValue> > &RegsToPass, 1078 bool IsPICCall, bool GlobalOrExternal, bool InternalLinkage, 1079 CallLoweringInfo &CLI, SDValue Callee, SDValue Chain) const { 1080 Ops.push_back(Callee); 1081 MipsTargetLowering::getOpndList(Ops, RegsToPass, IsPICCall, GlobalOrExternal, 1082 InternalLinkage, CLI, Callee, Chain); 1083 } 1084 1085 SDValue MipsSETargetLowering::lowerLOAD(SDValue Op, SelectionDAG &DAG) const { 1086 LoadSDNode &Nd = *cast<LoadSDNode>(Op); 1087 1088 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 1089 return MipsTargetLowering::lowerLOAD(Op, DAG); 1090 1091 // Replace a double precision load with two i32 loads and a buildpair64. 1092 SDLoc DL(Op); 1093 SDValue Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 1094 EVT PtrVT = Ptr.getValueType(); 1095 1096 // i32 load from lower address. 1097 SDValue Lo = DAG.getLoad(MVT::i32, DL, Chain, Ptr, 1098 MachinePointerInfo(), Nd.isVolatile(), 1099 Nd.isNonTemporal(), Nd.isInvariant(), 1100 Nd.getAlignment()); 1101 1102 // i32 load from higher address. 1103 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 1104 SDValue Hi = DAG.getLoad(MVT::i32, DL, Lo.getValue(1), Ptr, 1105 MachinePointerInfo(), Nd.isVolatile(), 1106 Nd.isNonTemporal(), Nd.isInvariant(), 1107 std::min(Nd.getAlignment(), 4U)); 1108 1109 if (!Subtarget->isLittle()) 1110 std::swap(Lo, Hi); 1111 1112 SDValue BP = DAG.getNode(MipsISD::BuildPairF64, DL, MVT::f64, Lo, Hi); 1113 SDValue Ops[2] = {BP, Hi.getValue(1)}; 1114 return DAG.getMergeValues(Ops, 2, DL); 1115 } 1116 1117 SDValue MipsSETargetLowering::lowerSTORE(SDValue Op, SelectionDAG &DAG) const { 1118 StoreSDNode &Nd = *cast<StoreSDNode>(Op); 1119 1120 if (Nd.getMemoryVT() != MVT::f64 || !NoDPLoadStore) 1121 return MipsTargetLowering::lowerSTORE(Op, DAG); 1122 1123 // Replace a double precision store with two extractelement64s and i32 stores. 1124 SDLoc DL(Op); 1125 SDValue Val = Nd.getValue(), Ptr = Nd.getBasePtr(), Chain = Nd.getChain(); 1126 EVT PtrVT = Ptr.getValueType(); 1127 SDValue Lo = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1128 Val, DAG.getConstant(0, MVT::i32)); 1129 SDValue Hi = DAG.getNode(MipsISD::ExtractElementF64, DL, MVT::i32, 1130 Val, DAG.getConstant(1, MVT::i32)); 1131 1132 if (!Subtarget->isLittle()) 1133 std::swap(Lo, Hi); 1134 1135 // i32 store to lower address. 1136 Chain = DAG.getStore(Chain, DL, Lo, Ptr, MachinePointerInfo(), 1137 Nd.isVolatile(), Nd.isNonTemporal(), Nd.getAlignment(), 1138 Nd.getTBAAInfo()); 1139 1140 // i32 store to higher address. 1141 Ptr = DAG.getNode(ISD::ADD, DL, PtrVT, Ptr, DAG.getConstant(4, PtrVT)); 1142 return DAG.getStore(Chain, DL, Hi, Ptr, MachinePointerInfo(), 1143 Nd.isVolatile(), Nd.isNonTemporal(), 1144 std::min(Nd.getAlignment(), 4U), Nd.getTBAAInfo()); 1145 } 1146 1147 SDValue MipsSETargetLowering::lowerMulDiv(SDValue Op, unsigned NewOpc, 1148 bool HasLo, bool HasHi, 1149 SelectionDAG &DAG) const { 1150 EVT Ty = Op.getOperand(0).getValueType(); 1151 SDLoc DL(Op); 1152 SDValue Mult = DAG.getNode(NewOpc, DL, MVT::Untyped, 1153 Op.getOperand(0), Op.getOperand(1)); 1154 SDValue Lo, Hi; 1155 1156 if (HasLo) 1157 Lo = DAG.getNode(MipsISD::MFLO, DL, Ty, Mult); 1158 if (HasHi) 1159 Hi = DAG.getNode(MipsISD::MFHI, DL, Ty, Mult); 1160 1161 if (!HasLo || !HasHi) 1162 return HasLo ? Lo : Hi; 1163 1164 SDValue Vals[] = { Lo, Hi }; 1165 return DAG.getMergeValues(Vals, 2, DL); 1166 } 1167 1168 1169 static SDValue initAccumulator(SDValue In, SDLoc DL, SelectionDAG &DAG) { 1170 SDValue InLo = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 1171 DAG.getConstant(0, MVT::i32)); 1172 SDValue InHi = DAG.getNode(ISD::EXTRACT_ELEMENT, DL, MVT::i32, In, 1173 DAG.getConstant(1, MVT::i32)); 1174 return DAG.getNode(MipsISD::MTLOHI, DL, MVT::Untyped, InLo, InHi); 1175 } 1176 1177 static SDValue extractLOHI(SDValue Op, SDLoc DL, SelectionDAG &DAG) { 1178 SDValue Lo = DAG.getNode(MipsISD::MFLO, DL, MVT::i32, Op); 1179 SDValue Hi = DAG.getNode(MipsISD::MFHI, DL, MVT::i32, Op); 1180 return DAG.getNode(ISD::BUILD_PAIR, DL, MVT::i64, Lo, Hi); 1181 } 1182 1183 // This function expands mips intrinsic nodes which have 64-bit input operands 1184 // or output values. 1185 // 1186 // out64 = intrinsic-node in64 1187 // => 1188 // lo = copy (extract-element (in64, 0)) 1189 // hi = copy (extract-element (in64, 1)) 1190 // mips-specific-node 1191 // v0 = copy lo 1192 // v1 = copy hi 1193 // out64 = merge-values (v0, v1) 1194 // 1195 static SDValue lowerDSPIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1196 SDLoc DL(Op); 1197 bool HasChainIn = Op->getOperand(0).getValueType() == MVT::Other; 1198 SmallVector<SDValue, 3> Ops; 1199 unsigned OpNo = 0; 1200 1201 // See if Op has a chain input. 1202 if (HasChainIn) 1203 Ops.push_back(Op->getOperand(OpNo++)); 1204 1205 // The next operand is the intrinsic opcode. 1206 assert(Op->getOperand(OpNo).getOpcode() == ISD::TargetConstant); 1207 1208 // See if the next operand has type i64. 1209 SDValue Opnd = Op->getOperand(++OpNo), In64; 1210 1211 if (Opnd.getValueType() == MVT::i64) 1212 In64 = initAccumulator(Opnd, DL, DAG); 1213 else 1214 Ops.push_back(Opnd); 1215 1216 // Push the remaining operands. 1217 for (++OpNo ; OpNo < Op->getNumOperands(); ++OpNo) 1218 Ops.push_back(Op->getOperand(OpNo)); 1219 1220 // Add In64 to the end of the list. 1221 if (In64.getNode()) 1222 Ops.push_back(In64); 1223 1224 // Scan output. 1225 SmallVector<EVT, 2> ResTys; 1226 1227 for (SDNode::value_iterator I = Op->value_begin(), E = Op->value_end(); 1228 I != E; ++I) 1229 ResTys.push_back((*I == MVT::i64) ? MVT::Untyped : *I); 1230 1231 // Create node. 1232 SDValue Val = DAG.getNode(Opc, DL, ResTys, &Ops[0], Ops.size()); 1233 SDValue Out = (ResTys[0] == MVT::Untyped) ? extractLOHI(Val, DL, DAG) : Val; 1234 1235 if (!HasChainIn) 1236 return Out; 1237 1238 assert(Val->getValueType(1) == MVT::Other); 1239 SDValue Vals[] = { Out, SDValue(Val.getNode(), 1) }; 1240 return DAG.getMergeValues(Vals, 2, DL); 1241 } 1242 1243 // Lower an MSA copy intrinsic into the specified SelectionDAG node 1244 static SDValue lowerMSACopyIntr(SDValue Op, SelectionDAG &DAG, unsigned Opc) { 1245 SDLoc DL(Op); 1246 SDValue Vec = Op->getOperand(1); 1247 SDValue Idx = Op->getOperand(2); 1248 EVT ResTy = Op->getValueType(0); 1249 EVT EltTy = Vec->getValueType(0).getVectorElementType(); 1250 1251 SDValue Result = DAG.getNode(Opc, DL, ResTy, Vec, Idx, 1252 DAG.getValueType(EltTy)); 1253 1254 return Result; 1255 } 1256 1257 static SDValue lowerMSASplatZExt(SDValue Op, unsigned OpNr, SelectionDAG &DAG) { 1258 EVT ResVecTy = Op->getValueType(0); 1259 EVT ViaVecTy = ResVecTy; 1260 SDLoc DL(Op); 1261 1262 // When ResVecTy == MVT::v2i64, LaneA is the upper 32 bits of the lane and 1263 // LaneB is the lower 32-bits. Otherwise LaneA and LaneB are alternating 1264 // lanes. 1265 SDValue LaneA; 1266 SDValue LaneB = Op->getOperand(2); 1267 1268 if (ResVecTy == MVT::v2i64) { 1269 LaneA = DAG.getConstant(0, MVT::i32); 1270 ViaVecTy = MVT::v4i32; 1271 } else 1272 LaneA = LaneB; 1273 1274 SDValue Ops[16] = { LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, 1275 LaneA, LaneB, LaneA, LaneB, LaneA, LaneB, LaneA, LaneB }; 1276 1277 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops, 1278 ViaVecTy.getVectorNumElements()); 1279 1280 if (ViaVecTy != ResVecTy) 1281 Result = DAG.getNode(ISD::BITCAST, DL, ResVecTy, Result); 1282 1283 return Result; 1284 } 1285 1286 static SDValue lowerMSASplatImm(SDValue Op, unsigned ImmOp, SelectionDAG &DAG) { 1287 return DAG.getConstant(Op->getConstantOperandVal(ImmOp), Op->getValueType(0)); 1288 } 1289 1290 static SDValue getBuildVectorSplat(EVT VecTy, SDValue SplatValue, 1291 bool BigEndian, SelectionDAG &DAG) { 1292 EVT ViaVecTy = VecTy; 1293 SDValue SplatValueA = SplatValue; 1294 SDValue SplatValueB = SplatValue; 1295 SDLoc DL(SplatValue); 1296 1297 if (VecTy == MVT::v2i64) { 1298 // v2i64 BUILD_VECTOR must be performed via v4i32 so split into i32's. 1299 ViaVecTy = MVT::v4i32; 1300 1301 SplatValueA = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValue); 1302 SplatValueB = DAG.getNode(ISD::SRL, DL, MVT::i64, SplatValue, 1303 DAG.getConstant(32, MVT::i32)); 1304 SplatValueB = DAG.getNode(ISD::TRUNCATE, DL, MVT::i32, SplatValueB); 1305 } 1306 1307 // We currently hold the parts in little endian order. Swap them if 1308 // necessary. 1309 if (BigEndian) 1310 std::swap(SplatValueA, SplatValueB); 1311 1312 SDValue Ops[16] = { SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1313 SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1314 SplatValueA, SplatValueB, SplatValueA, SplatValueB, 1315 SplatValueA, SplatValueB, SplatValueA, SplatValueB }; 1316 1317 SDValue Result = DAG.getNode(ISD::BUILD_VECTOR, DL, ViaVecTy, Ops, 1318 ViaVecTy.getVectorNumElements()); 1319 1320 if (VecTy != ViaVecTy) 1321 Result = DAG.getNode(ISD::BITCAST, DL, VecTy, Result); 1322 1323 return Result; 1324 } 1325 1326 static SDValue lowerMSABinaryBitImmIntr(SDValue Op, SelectionDAG &DAG, 1327 unsigned Opc, SDValue Imm, 1328 bool BigEndian) { 1329 EVT VecTy = Op->getValueType(0); 1330 SDValue Exp2Imm; 1331 SDLoc DL(Op); 1332 1333 // The DAG Combiner can't constant fold bitcasted vectors yet so we must do it 1334 // here for now. 1335 if (VecTy == MVT::v2i64) { 1336 if (ConstantSDNode *CImm = dyn_cast<ConstantSDNode>(Imm)) { 1337 APInt BitImm = APInt(64, 1) << CImm->getAPIntValue(); 1338 1339 SDValue BitImmHiOp = DAG.getConstant(BitImm.lshr(32).trunc(32), MVT::i32); 1340 SDValue BitImmLoOp = DAG.getConstant(BitImm.trunc(32), MVT::i32); 1341 1342 if (BigEndian) 1343 std::swap(BitImmLoOp, BitImmHiOp); 1344 1345 Exp2Imm = 1346 DAG.getNode(ISD::BITCAST, DL, MVT::v2i64, 1347 DAG.getNode(ISD::BUILD_VECTOR, DL, MVT::v4i32, BitImmLoOp, 1348 BitImmHiOp, BitImmLoOp, BitImmHiOp)); 1349 } 1350 } 1351 1352 if (Exp2Imm.getNode() == NULL) { 1353 // We couldnt constant fold, do a vector shift instead 1354 1355 // Extend i32 to i64 if necessary. Sign or zero extend doesn't matter since 1356 // only values 0-63 are valid. 1357 if (VecTy == MVT::v2i64) 1358 Imm = DAG.getNode(ISD::ZERO_EXTEND, DL, MVT::i64, Imm); 1359 1360 Exp2Imm = getBuildVectorSplat(VecTy, Imm, BigEndian, DAG); 1361 1362 Exp2Imm = 1363 DAG.getNode(ISD::SHL, DL, VecTy, DAG.getConstant(1, VecTy), Exp2Imm); 1364 } 1365 1366 return DAG.getNode(Opc, DL, VecTy, Op->getOperand(1), Exp2Imm); 1367 } 1368 1369 static SDValue lowerMSABitClear(SDValue Op, SelectionDAG &DAG) { 1370 EVT ResTy = Op->getValueType(0); 1371 SDLoc DL(Op); 1372 SDValue One = DAG.getConstant(1, ResTy); 1373 SDValue Bit = DAG.getNode(ISD::SHL, DL, ResTy, One, Op->getOperand(2)); 1374 1375 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), 1376 DAG.getNOT(DL, Bit, ResTy)); 1377 } 1378 1379 static SDValue lowerMSABitClearImm(SDValue Op, SelectionDAG &DAG) { 1380 SDLoc DL(Op); 1381 EVT ResTy = Op->getValueType(0); 1382 APInt BitImm = APInt(ResTy.getVectorElementType().getSizeInBits(), 1) 1383 << cast<ConstantSDNode>(Op->getOperand(2))->getAPIntValue(); 1384 SDValue BitMask = DAG.getConstant(~BitImm, ResTy); 1385 1386 return DAG.getNode(ISD::AND, DL, ResTy, Op->getOperand(1), BitMask); 1387 } 1388 1389 SDValue MipsSETargetLowering::lowerINTRINSIC_WO_CHAIN(SDValue Op, 1390 SelectionDAG &DAG) const { 1391 SDLoc DL(Op); 1392 1393 switch (cast<ConstantSDNode>(Op->getOperand(0))->getZExtValue()) { 1394 default: 1395 return SDValue(); 1396 case Intrinsic::mips_shilo: 1397 return lowerDSPIntr(Op, DAG, MipsISD::SHILO); 1398 case Intrinsic::mips_dpau_h_qbl: 1399 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBL); 1400 case Intrinsic::mips_dpau_h_qbr: 1401 return lowerDSPIntr(Op, DAG, MipsISD::DPAU_H_QBR); 1402 case Intrinsic::mips_dpsu_h_qbl: 1403 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBL); 1404 case Intrinsic::mips_dpsu_h_qbr: 1405 return lowerDSPIntr(Op, DAG, MipsISD::DPSU_H_QBR); 1406 case Intrinsic::mips_dpa_w_ph: 1407 return lowerDSPIntr(Op, DAG, MipsISD::DPA_W_PH); 1408 case Intrinsic::mips_dps_w_ph: 1409 return lowerDSPIntr(Op, DAG, MipsISD::DPS_W_PH); 1410 case Intrinsic::mips_dpax_w_ph: 1411 return lowerDSPIntr(Op, DAG, MipsISD::DPAX_W_PH); 1412 case Intrinsic::mips_dpsx_w_ph: 1413 return lowerDSPIntr(Op, DAG, MipsISD::DPSX_W_PH); 1414 case Intrinsic::mips_mulsa_w_ph: 1415 return lowerDSPIntr(Op, DAG, MipsISD::MULSA_W_PH); 1416 case Intrinsic::mips_mult: 1417 return lowerDSPIntr(Op, DAG, MipsISD::Mult); 1418 case Intrinsic::mips_multu: 1419 return lowerDSPIntr(Op, DAG, MipsISD::Multu); 1420 case Intrinsic::mips_madd: 1421 return lowerDSPIntr(Op, DAG, MipsISD::MAdd); 1422 case Intrinsic::mips_maddu: 1423 return lowerDSPIntr(Op, DAG, MipsISD::MAddu); 1424 case Intrinsic::mips_msub: 1425 return lowerDSPIntr(Op, DAG, MipsISD::MSub); 1426 case Intrinsic::mips_msubu: 1427 return lowerDSPIntr(Op, DAG, MipsISD::MSubu); 1428 case Intrinsic::mips_addv_b: 1429 case Intrinsic::mips_addv_h: 1430 case Intrinsic::mips_addv_w: 1431 case Intrinsic::mips_addv_d: 1432 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1433 Op->getOperand(2)); 1434 case Intrinsic::mips_addvi_b: 1435 case Intrinsic::mips_addvi_h: 1436 case Intrinsic::mips_addvi_w: 1437 case Intrinsic::mips_addvi_d: 1438 return DAG.getNode(ISD::ADD, DL, Op->getValueType(0), Op->getOperand(1), 1439 lowerMSASplatImm(Op, 2, DAG)); 1440 case Intrinsic::mips_and_v: 1441 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1442 Op->getOperand(2)); 1443 case Intrinsic::mips_andi_b: 1444 return DAG.getNode(ISD::AND, DL, Op->getValueType(0), Op->getOperand(1), 1445 lowerMSASplatImm(Op, 2, DAG)); 1446 case Intrinsic::mips_bclr_b: 1447 case Intrinsic::mips_bclr_h: 1448 case Intrinsic::mips_bclr_w: 1449 case Intrinsic::mips_bclr_d: 1450 return lowerMSABitClear(Op, DAG); 1451 case Intrinsic::mips_bclri_b: 1452 case Intrinsic::mips_bclri_h: 1453 case Intrinsic::mips_bclri_w: 1454 case Intrinsic::mips_bclri_d: 1455 return lowerMSABitClearImm(Op, DAG); 1456 case Intrinsic::mips_binsli_b: 1457 case Intrinsic::mips_binsli_h: 1458 case Intrinsic::mips_binsli_w: 1459 case Intrinsic::mips_binsli_d: { 1460 EVT VecTy = Op->getValueType(0); 1461 EVT EltTy = VecTy.getVectorElementType(); 1462 APInt Mask = APInt::getHighBitsSet(EltTy.getSizeInBits(), 1463 Op->getConstantOperandVal(3)); 1464 return DAG.getNode(ISD::VSELECT, DL, VecTy, 1465 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1), 1466 Op->getOperand(2)); 1467 } 1468 case Intrinsic::mips_binsri_b: 1469 case Intrinsic::mips_binsri_h: 1470 case Intrinsic::mips_binsri_w: 1471 case Intrinsic::mips_binsri_d: { 1472 EVT VecTy = Op->getValueType(0); 1473 EVT EltTy = VecTy.getVectorElementType(); 1474 APInt Mask = APInt::getLowBitsSet(EltTy.getSizeInBits(), 1475 Op->getConstantOperandVal(3)); 1476 return DAG.getNode(ISD::VSELECT, DL, VecTy, 1477 DAG.getConstant(Mask, VecTy, true), Op->getOperand(1), 1478 Op->getOperand(2)); 1479 } 1480 case Intrinsic::mips_bmnz_v: 1481 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), 1482 Op->getOperand(2), Op->getOperand(1)); 1483 case Intrinsic::mips_bmnzi_b: 1484 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1485 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(2), 1486 Op->getOperand(1)); 1487 case Intrinsic::mips_bmz_v: 1488 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), Op->getOperand(3), 1489 Op->getOperand(1), Op->getOperand(2)); 1490 case Intrinsic::mips_bmzi_b: 1491 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1492 lowerMSASplatImm(Op, 3, DAG), Op->getOperand(1), 1493 Op->getOperand(2)); 1494 case Intrinsic::mips_bneg_b: 1495 case Intrinsic::mips_bneg_h: 1496 case Intrinsic::mips_bneg_w: 1497 case Intrinsic::mips_bneg_d: { 1498 EVT VecTy = Op->getValueType(0); 1499 SDValue One = DAG.getConstant(1, VecTy); 1500 1501 return DAG.getNode(ISD::XOR, DL, VecTy, Op->getOperand(1), 1502 DAG.getNode(ISD::SHL, DL, VecTy, One, 1503 Op->getOperand(2))); 1504 } 1505 case Intrinsic::mips_bnegi_b: 1506 case Intrinsic::mips_bnegi_h: 1507 case Intrinsic::mips_bnegi_w: 1508 case Intrinsic::mips_bnegi_d: 1509 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::XOR, Op->getOperand(2), 1510 !Subtarget->isLittle()); 1511 case Intrinsic::mips_bnz_b: 1512 case Intrinsic::mips_bnz_h: 1513 case Intrinsic::mips_bnz_w: 1514 case Intrinsic::mips_bnz_d: 1515 return DAG.getNode(MipsISD::VALL_NONZERO, DL, Op->getValueType(0), 1516 Op->getOperand(1)); 1517 case Intrinsic::mips_bnz_v: 1518 return DAG.getNode(MipsISD::VANY_NONZERO, DL, Op->getValueType(0), 1519 Op->getOperand(1)); 1520 case Intrinsic::mips_bsel_v: 1521 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1522 Op->getOperand(1), Op->getOperand(2), 1523 Op->getOperand(3)); 1524 case Intrinsic::mips_bseli_b: 1525 return DAG.getNode(ISD::VSELECT, DL, Op->getValueType(0), 1526 Op->getOperand(1), Op->getOperand(2), 1527 lowerMSASplatImm(Op, 3, DAG)); 1528 case Intrinsic::mips_bset_b: 1529 case Intrinsic::mips_bset_h: 1530 case Intrinsic::mips_bset_w: 1531 case Intrinsic::mips_bset_d: { 1532 EVT VecTy = Op->getValueType(0); 1533 SDValue One = DAG.getConstant(1, VecTy); 1534 1535 return DAG.getNode(ISD::OR, DL, VecTy, Op->getOperand(1), 1536 DAG.getNode(ISD::SHL, DL, VecTy, One, 1537 Op->getOperand(2))); 1538 } 1539 case Intrinsic::mips_bseti_b: 1540 case Intrinsic::mips_bseti_h: 1541 case Intrinsic::mips_bseti_w: 1542 case Intrinsic::mips_bseti_d: 1543 return lowerMSABinaryBitImmIntr(Op, DAG, ISD::OR, Op->getOperand(2), 1544 !Subtarget->isLittle()); 1545 case Intrinsic::mips_bz_b: 1546 case Intrinsic::mips_bz_h: 1547 case Intrinsic::mips_bz_w: 1548 case Intrinsic::mips_bz_d: 1549 return DAG.getNode(MipsISD::VALL_ZERO, DL, Op->getValueType(0), 1550 Op->getOperand(1)); 1551 case Intrinsic::mips_bz_v: 1552 return DAG.getNode(MipsISD::VANY_ZERO, DL, Op->getValueType(0), 1553 Op->getOperand(1)); 1554 case Intrinsic::mips_ceq_b: 1555 case Intrinsic::mips_ceq_h: 1556 case Intrinsic::mips_ceq_w: 1557 case Intrinsic::mips_ceq_d: 1558 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1559 Op->getOperand(2), ISD::SETEQ); 1560 case Intrinsic::mips_ceqi_b: 1561 case Intrinsic::mips_ceqi_h: 1562 case Intrinsic::mips_ceqi_w: 1563 case Intrinsic::mips_ceqi_d: 1564 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1565 lowerMSASplatImm(Op, 2, DAG), ISD::SETEQ); 1566 case Intrinsic::mips_cle_s_b: 1567 case Intrinsic::mips_cle_s_h: 1568 case Intrinsic::mips_cle_s_w: 1569 case Intrinsic::mips_cle_s_d: 1570 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1571 Op->getOperand(2), ISD::SETLE); 1572 case Intrinsic::mips_clei_s_b: 1573 case Intrinsic::mips_clei_s_h: 1574 case Intrinsic::mips_clei_s_w: 1575 case Intrinsic::mips_clei_s_d: 1576 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1577 lowerMSASplatImm(Op, 2, DAG), ISD::SETLE); 1578 case Intrinsic::mips_cle_u_b: 1579 case Intrinsic::mips_cle_u_h: 1580 case Intrinsic::mips_cle_u_w: 1581 case Intrinsic::mips_cle_u_d: 1582 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1583 Op->getOperand(2), ISD::SETULE); 1584 case Intrinsic::mips_clei_u_b: 1585 case Intrinsic::mips_clei_u_h: 1586 case Intrinsic::mips_clei_u_w: 1587 case Intrinsic::mips_clei_u_d: 1588 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1589 lowerMSASplatImm(Op, 2, DAG), ISD::SETULE); 1590 case Intrinsic::mips_clt_s_b: 1591 case Intrinsic::mips_clt_s_h: 1592 case Intrinsic::mips_clt_s_w: 1593 case Intrinsic::mips_clt_s_d: 1594 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1595 Op->getOperand(2), ISD::SETLT); 1596 case Intrinsic::mips_clti_s_b: 1597 case Intrinsic::mips_clti_s_h: 1598 case Intrinsic::mips_clti_s_w: 1599 case Intrinsic::mips_clti_s_d: 1600 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1601 lowerMSASplatImm(Op, 2, DAG), ISD::SETLT); 1602 case Intrinsic::mips_clt_u_b: 1603 case Intrinsic::mips_clt_u_h: 1604 case Intrinsic::mips_clt_u_w: 1605 case Intrinsic::mips_clt_u_d: 1606 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1607 Op->getOperand(2), ISD::SETULT); 1608 case Intrinsic::mips_clti_u_b: 1609 case Intrinsic::mips_clti_u_h: 1610 case Intrinsic::mips_clti_u_w: 1611 case Intrinsic::mips_clti_u_d: 1612 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1613 lowerMSASplatImm(Op, 2, DAG), ISD::SETULT); 1614 case Intrinsic::mips_copy_s_b: 1615 case Intrinsic::mips_copy_s_h: 1616 case Intrinsic::mips_copy_s_w: 1617 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_SEXT_ELT); 1618 case Intrinsic::mips_copy_s_d: 1619 // Don't lower directly into VEXTRACT_SEXT_ELT since i64 might be illegal. 1620 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1621 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1622 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1623 Op->getOperand(1), Op->getOperand(2)); 1624 case Intrinsic::mips_copy_u_b: 1625 case Intrinsic::mips_copy_u_h: 1626 case Intrinsic::mips_copy_u_w: 1627 return lowerMSACopyIntr(Op, DAG, MipsISD::VEXTRACT_ZEXT_ELT); 1628 case Intrinsic::mips_copy_u_d: 1629 // Don't lower directly into VEXTRACT_ZEXT_ELT since i64 might be illegal. 1630 // Instead lower to the generic EXTRACT_VECTOR_ELT node and let the type 1631 // legalizer and EXTRACT_VECTOR_ELT lowering sort it out. 1632 // 1633 // Note: When i64 is illegal, this results in copy_s.w instructions instead 1634 // of copy_u.w instructions. This makes no difference to the behaviour 1635 // since i64 is only illegal when the register file is 32-bit. 1636 return DAG.getNode(ISD::EXTRACT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1637 Op->getOperand(1), Op->getOperand(2)); 1638 case Intrinsic::mips_div_s_b: 1639 case Intrinsic::mips_div_s_h: 1640 case Intrinsic::mips_div_s_w: 1641 case Intrinsic::mips_div_s_d: 1642 return DAG.getNode(ISD::SDIV, DL, Op->getValueType(0), Op->getOperand(1), 1643 Op->getOperand(2)); 1644 case Intrinsic::mips_div_u_b: 1645 case Intrinsic::mips_div_u_h: 1646 case Intrinsic::mips_div_u_w: 1647 case Intrinsic::mips_div_u_d: 1648 return DAG.getNode(ISD::UDIV, DL, Op->getValueType(0), Op->getOperand(1), 1649 Op->getOperand(2)); 1650 case Intrinsic::mips_fadd_w: 1651 case Intrinsic::mips_fadd_d: 1652 return DAG.getNode(ISD::FADD, DL, Op->getValueType(0), Op->getOperand(1), 1653 Op->getOperand(2)); 1654 // Don't lower mips_fcaf_[wd] since LLVM folds SETFALSE condcodes away 1655 case Intrinsic::mips_fceq_w: 1656 case Intrinsic::mips_fceq_d: 1657 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1658 Op->getOperand(2), ISD::SETOEQ); 1659 case Intrinsic::mips_fcle_w: 1660 case Intrinsic::mips_fcle_d: 1661 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1662 Op->getOperand(2), ISD::SETOLE); 1663 case Intrinsic::mips_fclt_w: 1664 case Intrinsic::mips_fclt_d: 1665 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1666 Op->getOperand(2), ISD::SETOLT); 1667 case Intrinsic::mips_fcne_w: 1668 case Intrinsic::mips_fcne_d: 1669 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1670 Op->getOperand(2), ISD::SETONE); 1671 case Intrinsic::mips_fcor_w: 1672 case Intrinsic::mips_fcor_d: 1673 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1674 Op->getOperand(2), ISD::SETO); 1675 case Intrinsic::mips_fcueq_w: 1676 case Intrinsic::mips_fcueq_d: 1677 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1678 Op->getOperand(2), ISD::SETUEQ); 1679 case Intrinsic::mips_fcule_w: 1680 case Intrinsic::mips_fcule_d: 1681 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1682 Op->getOperand(2), ISD::SETULE); 1683 case Intrinsic::mips_fcult_w: 1684 case Intrinsic::mips_fcult_d: 1685 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1686 Op->getOperand(2), ISD::SETULT); 1687 case Intrinsic::mips_fcun_w: 1688 case Intrinsic::mips_fcun_d: 1689 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1690 Op->getOperand(2), ISD::SETUO); 1691 case Intrinsic::mips_fcune_w: 1692 case Intrinsic::mips_fcune_d: 1693 return DAG.getSetCC(DL, Op->getValueType(0), Op->getOperand(1), 1694 Op->getOperand(2), ISD::SETUNE); 1695 case Intrinsic::mips_fdiv_w: 1696 case Intrinsic::mips_fdiv_d: 1697 return DAG.getNode(ISD::FDIV, DL, Op->getValueType(0), Op->getOperand(1), 1698 Op->getOperand(2)); 1699 case Intrinsic::mips_ffint_u_w: 1700 case Intrinsic::mips_ffint_u_d: 1701 return DAG.getNode(ISD::UINT_TO_FP, DL, Op->getValueType(0), 1702 Op->getOperand(1)); 1703 case Intrinsic::mips_ffint_s_w: 1704 case Intrinsic::mips_ffint_s_d: 1705 return DAG.getNode(ISD::SINT_TO_FP, DL, Op->getValueType(0), 1706 Op->getOperand(1)); 1707 case Intrinsic::mips_fill_b: 1708 case Intrinsic::mips_fill_h: 1709 case Intrinsic::mips_fill_w: 1710 case Intrinsic::mips_fill_d: { 1711 SmallVector<SDValue, 16> Ops; 1712 EVT ResTy = Op->getValueType(0); 1713 1714 for (unsigned i = 0; i < ResTy.getVectorNumElements(); ++i) 1715 Ops.push_back(Op->getOperand(1)); 1716 1717 // If ResTy is v2i64 then the type legalizer will break this node down into 1718 // an equivalent v4i32. 1719 return DAG.getNode(ISD::BUILD_VECTOR, DL, ResTy, &Ops[0], Ops.size()); 1720 } 1721 case Intrinsic::mips_fexp2_w: 1722 case Intrinsic::mips_fexp2_d: { 1723 EVT ResTy = Op->getValueType(0); 1724 return DAG.getNode( 1725 ISD::FMUL, SDLoc(Op), ResTy, Op->getOperand(1), 1726 DAG.getNode(ISD::FEXP2, SDLoc(Op), ResTy, Op->getOperand(2))); 1727 } 1728 case Intrinsic::mips_flog2_w: 1729 case Intrinsic::mips_flog2_d: 1730 return DAG.getNode(ISD::FLOG2, DL, Op->getValueType(0), Op->getOperand(1)); 1731 case Intrinsic::mips_fmadd_w: 1732 case Intrinsic::mips_fmadd_d: 1733 return DAG.getNode(ISD::FMA, SDLoc(Op), Op->getValueType(0), 1734 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 1735 case Intrinsic::mips_fmul_w: 1736 case Intrinsic::mips_fmul_d: 1737 return DAG.getNode(ISD::FMUL, DL, Op->getValueType(0), Op->getOperand(1), 1738 Op->getOperand(2)); 1739 case Intrinsic::mips_fmsub_w: 1740 case Intrinsic::mips_fmsub_d: { 1741 EVT ResTy = Op->getValueType(0); 1742 return DAG.getNode(ISD::FSUB, SDLoc(Op), ResTy, Op->getOperand(1), 1743 DAG.getNode(ISD::FMUL, SDLoc(Op), ResTy, 1744 Op->getOperand(2), Op->getOperand(3))); 1745 } 1746 case Intrinsic::mips_frint_w: 1747 case Intrinsic::mips_frint_d: 1748 return DAG.getNode(ISD::FRINT, DL, Op->getValueType(0), Op->getOperand(1)); 1749 case Intrinsic::mips_fsqrt_w: 1750 case Intrinsic::mips_fsqrt_d: 1751 return DAG.getNode(ISD::FSQRT, DL, Op->getValueType(0), Op->getOperand(1)); 1752 case Intrinsic::mips_fsub_w: 1753 case Intrinsic::mips_fsub_d: 1754 return DAG.getNode(ISD::FSUB, DL, Op->getValueType(0), Op->getOperand(1), 1755 Op->getOperand(2)); 1756 case Intrinsic::mips_ftrunc_u_w: 1757 case Intrinsic::mips_ftrunc_u_d: 1758 return DAG.getNode(ISD::FP_TO_UINT, DL, Op->getValueType(0), 1759 Op->getOperand(1)); 1760 case Intrinsic::mips_ftrunc_s_w: 1761 case Intrinsic::mips_ftrunc_s_d: 1762 return DAG.getNode(ISD::FP_TO_SINT, DL, Op->getValueType(0), 1763 Op->getOperand(1)); 1764 case Intrinsic::mips_ilvev_b: 1765 case Intrinsic::mips_ilvev_h: 1766 case Intrinsic::mips_ilvev_w: 1767 case Intrinsic::mips_ilvev_d: 1768 return DAG.getNode(MipsISD::ILVEV, DL, Op->getValueType(0), 1769 Op->getOperand(1), Op->getOperand(2)); 1770 case Intrinsic::mips_ilvl_b: 1771 case Intrinsic::mips_ilvl_h: 1772 case Intrinsic::mips_ilvl_w: 1773 case Intrinsic::mips_ilvl_d: 1774 return DAG.getNode(MipsISD::ILVL, DL, Op->getValueType(0), 1775 Op->getOperand(1), Op->getOperand(2)); 1776 case Intrinsic::mips_ilvod_b: 1777 case Intrinsic::mips_ilvod_h: 1778 case Intrinsic::mips_ilvod_w: 1779 case Intrinsic::mips_ilvod_d: 1780 return DAG.getNode(MipsISD::ILVOD, DL, Op->getValueType(0), 1781 Op->getOperand(1), Op->getOperand(2)); 1782 case Intrinsic::mips_ilvr_b: 1783 case Intrinsic::mips_ilvr_h: 1784 case Intrinsic::mips_ilvr_w: 1785 case Intrinsic::mips_ilvr_d: 1786 return DAG.getNode(MipsISD::ILVR, DL, Op->getValueType(0), 1787 Op->getOperand(1), Op->getOperand(2)); 1788 case Intrinsic::mips_insert_b: 1789 case Intrinsic::mips_insert_h: 1790 case Intrinsic::mips_insert_w: 1791 case Intrinsic::mips_insert_d: 1792 return DAG.getNode(ISD::INSERT_VECTOR_ELT, SDLoc(Op), Op->getValueType(0), 1793 Op->getOperand(1), Op->getOperand(3), Op->getOperand(2)); 1794 case Intrinsic::mips_ldi_b: 1795 case Intrinsic::mips_ldi_h: 1796 case Intrinsic::mips_ldi_w: 1797 case Intrinsic::mips_ldi_d: 1798 return lowerMSASplatImm(Op, 1, DAG); 1799 case Intrinsic::mips_lsa: { 1800 EVT ResTy = Op->getValueType(0); 1801 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1802 DAG.getNode(ISD::SHL, SDLoc(Op), ResTy, 1803 Op->getOperand(2), Op->getOperand(3))); 1804 } 1805 case Intrinsic::mips_maddv_b: 1806 case Intrinsic::mips_maddv_h: 1807 case Intrinsic::mips_maddv_w: 1808 case Intrinsic::mips_maddv_d: { 1809 EVT ResTy = Op->getValueType(0); 1810 return DAG.getNode(ISD::ADD, SDLoc(Op), ResTy, Op->getOperand(1), 1811 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1812 Op->getOperand(2), Op->getOperand(3))); 1813 } 1814 case Intrinsic::mips_max_s_b: 1815 case Intrinsic::mips_max_s_h: 1816 case Intrinsic::mips_max_s_w: 1817 case Intrinsic::mips_max_s_d: 1818 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1819 Op->getOperand(1), Op->getOperand(2)); 1820 case Intrinsic::mips_max_u_b: 1821 case Intrinsic::mips_max_u_h: 1822 case Intrinsic::mips_max_u_w: 1823 case Intrinsic::mips_max_u_d: 1824 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1825 Op->getOperand(1), Op->getOperand(2)); 1826 case Intrinsic::mips_maxi_s_b: 1827 case Intrinsic::mips_maxi_s_h: 1828 case Intrinsic::mips_maxi_s_w: 1829 case Intrinsic::mips_maxi_s_d: 1830 return DAG.getNode(MipsISD::VSMAX, DL, Op->getValueType(0), 1831 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1832 case Intrinsic::mips_maxi_u_b: 1833 case Intrinsic::mips_maxi_u_h: 1834 case Intrinsic::mips_maxi_u_w: 1835 case Intrinsic::mips_maxi_u_d: 1836 return DAG.getNode(MipsISD::VUMAX, DL, Op->getValueType(0), 1837 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1838 case Intrinsic::mips_min_s_b: 1839 case Intrinsic::mips_min_s_h: 1840 case Intrinsic::mips_min_s_w: 1841 case Intrinsic::mips_min_s_d: 1842 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1843 Op->getOperand(1), Op->getOperand(2)); 1844 case Intrinsic::mips_min_u_b: 1845 case Intrinsic::mips_min_u_h: 1846 case Intrinsic::mips_min_u_w: 1847 case Intrinsic::mips_min_u_d: 1848 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1849 Op->getOperand(1), Op->getOperand(2)); 1850 case Intrinsic::mips_mini_s_b: 1851 case Intrinsic::mips_mini_s_h: 1852 case Intrinsic::mips_mini_s_w: 1853 case Intrinsic::mips_mini_s_d: 1854 return DAG.getNode(MipsISD::VSMIN, DL, Op->getValueType(0), 1855 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1856 case Intrinsic::mips_mini_u_b: 1857 case Intrinsic::mips_mini_u_h: 1858 case Intrinsic::mips_mini_u_w: 1859 case Intrinsic::mips_mini_u_d: 1860 return DAG.getNode(MipsISD::VUMIN, DL, Op->getValueType(0), 1861 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1862 case Intrinsic::mips_mod_s_b: 1863 case Intrinsic::mips_mod_s_h: 1864 case Intrinsic::mips_mod_s_w: 1865 case Intrinsic::mips_mod_s_d: 1866 return DAG.getNode(ISD::SREM, DL, Op->getValueType(0), Op->getOperand(1), 1867 Op->getOperand(2)); 1868 case Intrinsic::mips_mod_u_b: 1869 case Intrinsic::mips_mod_u_h: 1870 case Intrinsic::mips_mod_u_w: 1871 case Intrinsic::mips_mod_u_d: 1872 return DAG.getNode(ISD::UREM, DL, Op->getValueType(0), Op->getOperand(1), 1873 Op->getOperand(2)); 1874 case Intrinsic::mips_mulv_b: 1875 case Intrinsic::mips_mulv_h: 1876 case Intrinsic::mips_mulv_w: 1877 case Intrinsic::mips_mulv_d: 1878 return DAG.getNode(ISD::MUL, DL, Op->getValueType(0), Op->getOperand(1), 1879 Op->getOperand(2)); 1880 case Intrinsic::mips_msubv_b: 1881 case Intrinsic::mips_msubv_h: 1882 case Intrinsic::mips_msubv_w: 1883 case Intrinsic::mips_msubv_d: { 1884 EVT ResTy = Op->getValueType(0); 1885 return DAG.getNode(ISD::SUB, SDLoc(Op), ResTy, Op->getOperand(1), 1886 DAG.getNode(ISD::MUL, SDLoc(Op), ResTy, 1887 Op->getOperand(2), Op->getOperand(3))); 1888 } 1889 case Intrinsic::mips_nlzc_b: 1890 case Intrinsic::mips_nlzc_h: 1891 case Intrinsic::mips_nlzc_w: 1892 case Intrinsic::mips_nlzc_d: 1893 return DAG.getNode(ISD::CTLZ, DL, Op->getValueType(0), Op->getOperand(1)); 1894 case Intrinsic::mips_nor_v: { 1895 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1896 Op->getOperand(1), Op->getOperand(2)); 1897 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1898 } 1899 case Intrinsic::mips_nori_b: { 1900 SDValue Res = DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1901 Op->getOperand(1), 1902 lowerMSASplatImm(Op, 2, DAG)); 1903 return DAG.getNOT(DL, Res, Res->getValueType(0)); 1904 } 1905 case Intrinsic::mips_or_v: 1906 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), Op->getOperand(1), 1907 Op->getOperand(2)); 1908 case Intrinsic::mips_ori_b: 1909 return DAG.getNode(ISD::OR, DL, Op->getValueType(0), 1910 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1911 case Intrinsic::mips_pckev_b: 1912 case Intrinsic::mips_pckev_h: 1913 case Intrinsic::mips_pckev_w: 1914 case Intrinsic::mips_pckev_d: 1915 return DAG.getNode(MipsISD::PCKEV, DL, Op->getValueType(0), 1916 Op->getOperand(1), Op->getOperand(2)); 1917 case Intrinsic::mips_pckod_b: 1918 case Intrinsic::mips_pckod_h: 1919 case Intrinsic::mips_pckod_w: 1920 case Intrinsic::mips_pckod_d: 1921 return DAG.getNode(MipsISD::PCKOD, DL, Op->getValueType(0), 1922 Op->getOperand(1), Op->getOperand(2)); 1923 case Intrinsic::mips_pcnt_b: 1924 case Intrinsic::mips_pcnt_h: 1925 case Intrinsic::mips_pcnt_w: 1926 case Intrinsic::mips_pcnt_d: 1927 return DAG.getNode(ISD::CTPOP, DL, Op->getValueType(0), Op->getOperand(1)); 1928 case Intrinsic::mips_shf_b: 1929 case Intrinsic::mips_shf_h: 1930 case Intrinsic::mips_shf_w: 1931 return DAG.getNode(MipsISD::SHF, DL, Op->getValueType(0), 1932 Op->getOperand(2), Op->getOperand(1)); 1933 case Intrinsic::mips_sll_b: 1934 case Intrinsic::mips_sll_h: 1935 case Intrinsic::mips_sll_w: 1936 case Intrinsic::mips_sll_d: 1937 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), Op->getOperand(1), 1938 Op->getOperand(2)); 1939 case Intrinsic::mips_slli_b: 1940 case Intrinsic::mips_slli_h: 1941 case Intrinsic::mips_slli_w: 1942 case Intrinsic::mips_slli_d: 1943 return DAG.getNode(ISD::SHL, DL, Op->getValueType(0), 1944 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1945 case Intrinsic::mips_splat_b: 1946 case Intrinsic::mips_splat_h: 1947 case Intrinsic::mips_splat_w: 1948 case Intrinsic::mips_splat_d: 1949 // We can't lower via VECTOR_SHUFFLE because it requires constant shuffle 1950 // masks, nor can we lower via BUILD_VECTOR & EXTRACT_VECTOR_ELT because 1951 // EXTRACT_VECTOR_ELT can't extract i64's on MIPS32. 1952 // Instead we lower to MipsISD::VSHF and match from there. 1953 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1954 lowerMSASplatZExt(Op, 2, DAG), Op->getOperand(1), 1955 Op->getOperand(1)); 1956 case Intrinsic::mips_splati_b: 1957 case Intrinsic::mips_splati_h: 1958 case Intrinsic::mips_splati_w: 1959 case Intrinsic::mips_splati_d: 1960 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 1961 lowerMSASplatImm(Op, 2, DAG), Op->getOperand(1), 1962 Op->getOperand(1)); 1963 case Intrinsic::mips_sra_b: 1964 case Intrinsic::mips_sra_h: 1965 case Intrinsic::mips_sra_w: 1966 case Intrinsic::mips_sra_d: 1967 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), Op->getOperand(1), 1968 Op->getOperand(2)); 1969 case Intrinsic::mips_srai_b: 1970 case Intrinsic::mips_srai_h: 1971 case Intrinsic::mips_srai_w: 1972 case Intrinsic::mips_srai_d: 1973 return DAG.getNode(ISD::SRA, DL, Op->getValueType(0), 1974 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1975 case Intrinsic::mips_srl_b: 1976 case Intrinsic::mips_srl_h: 1977 case Intrinsic::mips_srl_w: 1978 case Intrinsic::mips_srl_d: 1979 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), Op->getOperand(1), 1980 Op->getOperand(2)); 1981 case Intrinsic::mips_srli_b: 1982 case Intrinsic::mips_srli_h: 1983 case Intrinsic::mips_srli_w: 1984 case Intrinsic::mips_srli_d: 1985 return DAG.getNode(ISD::SRL, DL, Op->getValueType(0), 1986 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1987 case Intrinsic::mips_subv_b: 1988 case Intrinsic::mips_subv_h: 1989 case Intrinsic::mips_subv_w: 1990 case Intrinsic::mips_subv_d: 1991 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), Op->getOperand(1), 1992 Op->getOperand(2)); 1993 case Intrinsic::mips_subvi_b: 1994 case Intrinsic::mips_subvi_h: 1995 case Intrinsic::mips_subvi_w: 1996 case Intrinsic::mips_subvi_d: 1997 return DAG.getNode(ISD::SUB, DL, Op->getValueType(0), 1998 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 1999 case Intrinsic::mips_vshf_b: 2000 case Intrinsic::mips_vshf_h: 2001 case Intrinsic::mips_vshf_w: 2002 case Intrinsic::mips_vshf_d: 2003 return DAG.getNode(MipsISD::VSHF, DL, Op->getValueType(0), 2004 Op->getOperand(1), Op->getOperand(2), Op->getOperand(3)); 2005 case Intrinsic::mips_xor_v: 2006 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), Op->getOperand(1), 2007 Op->getOperand(2)); 2008 case Intrinsic::mips_xori_b: 2009 return DAG.getNode(ISD::XOR, DL, Op->getValueType(0), 2010 Op->getOperand(1), lowerMSASplatImm(Op, 2, DAG)); 2011 } 2012 } 2013 2014 static SDValue lowerMSALoadIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 2015 SDLoc DL(Op); 2016 SDValue ChainIn = Op->getOperand(0); 2017 SDValue Address = Op->getOperand(2); 2018 SDValue Offset = Op->getOperand(3); 2019 EVT ResTy = Op->getValueType(0); 2020 EVT PtrTy = Address->getValueType(0); 2021 2022 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 2023 2024 return DAG.getLoad(ResTy, DL, ChainIn, Address, MachinePointerInfo(), false, 2025 false, false, 16); 2026 } 2027 2028 SDValue MipsSETargetLowering::lowerINTRINSIC_W_CHAIN(SDValue Op, 2029 SelectionDAG &DAG) const { 2030 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 2031 switch (Intr) { 2032 default: 2033 return SDValue(); 2034 case Intrinsic::mips_extp: 2035 return lowerDSPIntr(Op, DAG, MipsISD::EXTP); 2036 case Intrinsic::mips_extpdp: 2037 return lowerDSPIntr(Op, DAG, MipsISD::EXTPDP); 2038 case Intrinsic::mips_extr_w: 2039 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_W); 2040 case Intrinsic::mips_extr_r_w: 2041 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_R_W); 2042 case Intrinsic::mips_extr_rs_w: 2043 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_RS_W); 2044 case Intrinsic::mips_extr_s_h: 2045 return lowerDSPIntr(Op, DAG, MipsISD::EXTR_S_H); 2046 case Intrinsic::mips_mthlip: 2047 return lowerDSPIntr(Op, DAG, MipsISD::MTHLIP); 2048 case Intrinsic::mips_mulsaq_s_w_ph: 2049 return lowerDSPIntr(Op, DAG, MipsISD::MULSAQ_S_W_PH); 2050 case Intrinsic::mips_maq_s_w_phl: 2051 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHL); 2052 case Intrinsic::mips_maq_s_w_phr: 2053 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_S_W_PHR); 2054 case Intrinsic::mips_maq_sa_w_phl: 2055 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHL); 2056 case Intrinsic::mips_maq_sa_w_phr: 2057 return lowerDSPIntr(Op, DAG, MipsISD::MAQ_SA_W_PHR); 2058 case Intrinsic::mips_dpaq_s_w_ph: 2059 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_S_W_PH); 2060 case Intrinsic::mips_dpsq_s_w_ph: 2061 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_S_W_PH); 2062 case Intrinsic::mips_dpaq_sa_l_w: 2063 return lowerDSPIntr(Op, DAG, MipsISD::DPAQ_SA_L_W); 2064 case Intrinsic::mips_dpsq_sa_l_w: 2065 return lowerDSPIntr(Op, DAG, MipsISD::DPSQ_SA_L_W); 2066 case Intrinsic::mips_dpaqx_s_w_ph: 2067 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_S_W_PH); 2068 case Intrinsic::mips_dpaqx_sa_w_ph: 2069 return lowerDSPIntr(Op, DAG, MipsISD::DPAQX_SA_W_PH); 2070 case Intrinsic::mips_dpsqx_s_w_ph: 2071 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_S_W_PH); 2072 case Intrinsic::mips_dpsqx_sa_w_ph: 2073 return lowerDSPIntr(Op, DAG, MipsISD::DPSQX_SA_W_PH); 2074 case Intrinsic::mips_ld_b: 2075 case Intrinsic::mips_ld_h: 2076 case Intrinsic::mips_ld_w: 2077 case Intrinsic::mips_ld_d: 2078 return lowerMSALoadIntr(Op, DAG, Intr); 2079 } 2080 } 2081 2082 static SDValue lowerMSAStoreIntr(SDValue Op, SelectionDAG &DAG, unsigned Intr) { 2083 SDLoc DL(Op); 2084 SDValue ChainIn = Op->getOperand(0); 2085 SDValue Value = Op->getOperand(2); 2086 SDValue Address = Op->getOperand(3); 2087 SDValue Offset = Op->getOperand(4); 2088 EVT PtrTy = Address->getValueType(0); 2089 2090 Address = DAG.getNode(ISD::ADD, DL, PtrTy, Address, Offset); 2091 2092 return DAG.getStore(ChainIn, DL, Value, Address, MachinePointerInfo(), false, 2093 false, 16); 2094 } 2095 2096 SDValue MipsSETargetLowering::lowerINTRINSIC_VOID(SDValue Op, 2097 SelectionDAG &DAG) const { 2098 unsigned Intr = cast<ConstantSDNode>(Op->getOperand(1))->getZExtValue(); 2099 switch (Intr) { 2100 default: 2101 return SDValue(); 2102 case Intrinsic::mips_st_b: 2103 case Intrinsic::mips_st_h: 2104 case Intrinsic::mips_st_w: 2105 case Intrinsic::mips_st_d: 2106 return lowerMSAStoreIntr(Op, DAG, Intr); 2107 } 2108 } 2109 2110 /// \brief Check if the given BuildVectorSDNode is a splat. 2111 /// This method currently relies on DAG nodes being reused when equivalent, 2112 /// so it's possible for this to return false even when isConstantSplat returns 2113 /// true. 2114 static bool isSplatVector(const BuildVectorSDNode *N) { 2115 unsigned int nOps = N->getNumOperands(); 2116 assert(nOps > 1 && "isSplatVector has 0 or 1 sized build vector"); 2117 2118 SDValue Operand0 = N->getOperand(0); 2119 2120 for (unsigned int i = 1; i < nOps; ++i) { 2121 if (N->getOperand(i) != Operand0) 2122 return false; 2123 } 2124 2125 return true; 2126 } 2127 2128 // Lower ISD::EXTRACT_VECTOR_ELT into MipsISD::VEXTRACT_SEXT_ELT. 2129 // 2130 // The non-value bits resulting from ISD::EXTRACT_VECTOR_ELT are undefined. We 2131 // choose to sign-extend but we could have equally chosen zero-extend. The 2132 // DAGCombiner will fold any sign/zero extension of the ISD::EXTRACT_VECTOR_ELT 2133 // result into this node later (possibly changing it to a zero-extend in the 2134 // process). 2135 SDValue MipsSETargetLowering:: 2136 lowerEXTRACT_VECTOR_ELT(SDValue Op, SelectionDAG &DAG) const { 2137 SDLoc DL(Op); 2138 EVT ResTy = Op->getValueType(0); 2139 SDValue Op0 = Op->getOperand(0); 2140 EVT VecTy = Op0->getValueType(0); 2141 2142 if (!VecTy.is128BitVector()) 2143 return SDValue(); 2144 2145 if (ResTy.isInteger()) { 2146 SDValue Op1 = Op->getOperand(1); 2147 EVT EltTy = VecTy.getVectorElementType(); 2148 return DAG.getNode(MipsISD::VEXTRACT_SEXT_ELT, DL, ResTy, Op0, Op1, 2149 DAG.getValueType(EltTy)); 2150 } 2151 2152 return Op; 2153 } 2154 2155 static bool isConstantOrUndef(const SDValue Op) { 2156 if (Op->getOpcode() == ISD::UNDEF) 2157 return true; 2158 if (dyn_cast<ConstantSDNode>(Op)) 2159 return true; 2160 if (dyn_cast<ConstantFPSDNode>(Op)) 2161 return true; 2162 return false; 2163 } 2164 2165 static bool isConstantOrUndefBUILD_VECTOR(const BuildVectorSDNode *Op) { 2166 for (unsigned i = 0; i < Op->getNumOperands(); ++i) 2167 if (isConstantOrUndef(Op->getOperand(i))) 2168 return true; 2169 return false; 2170 } 2171 2172 // Lowers ISD::BUILD_VECTOR into appropriate SelectionDAG nodes for the 2173 // backend. 2174 // 2175 // Lowers according to the following rules: 2176 // - Constant splats are legal as-is as long as the SplatBitSize is a power of 2177 // 2 less than or equal to 64 and the value fits into a signed 10-bit 2178 // immediate 2179 // - Constant splats are lowered to bitconverted BUILD_VECTORs if SplatBitSize 2180 // is a power of 2 less than or equal to 64 and the value does not fit into a 2181 // signed 10-bit immediate 2182 // - Non-constant splats are legal as-is. 2183 // - Non-constant non-splats are lowered to sequences of INSERT_VECTOR_ELT. 2184 // - All others are illegal and must be expanded. 2185 SDValue MipsSETargetLowering::lowerBUILD_VECTOR(SDValue Op, 2186 SelectionDAG &DAG) const { 2187 BuildVectorSDNode *Node = cast<BuildVectorSDNode>(Op); 2188 EVT ResTy = Op->getValueType(0); 2189 SDLoc DL(Op); 2190 APInt SplatValue, SplatUndef; 2191 unsigned SplatBitSize; 2192 bool HasAnyUndefs; 2193 2194 if (!Subtarget->hasMSA() || !ResTy.is128BitVector()) 2195 return SDValue(); 2196 2197 if (Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize, 2198 HasAnyUndefs, 8, 2199 !Subtarget->isLittle()) && SplatBitSize <= 64) { 2200 // We can only cope with 8, 16, 32, or 64-bit elements 2201 if (SplatBitSize != 8 && SplatBitSize != 16 && SplatBitSize != 32 && 2202 SplatBitSize != 64) 2203 return SDValue(); 2204 2205 // If the value fits into a simm10 then we can use ldi.[bhwd] 2206 // However, if it isn't an integer type we will have to bitcast from an 2207 // integer type first. Also, if there are any undefs, we must lower them 2208 // to defined values first. 2209 if (ResTy.isInteger() && !HasAnyUndefs && SplatValue.isSignedIntN(10)) 2210 return Op; 2211 2212 EVT ViaVecTy; 2213 2214 switch (SplatBitSize) { 2215 default: 2216 return SDValue(); 2217 case 8: 2218 ViaVecTy = MVT::v16i8; 2219 break; 2220 case 16: 2221 ViaVecTy = MVT::v8i16; 2222 break; 2223 case 32: 2224 ViaVecTy = MVT::v4i32; 2225 break; 2226 case 64: 2227 // There's no fill.d to fall back on for 64-bit values 2228 return SDValue(); 2229 } 2230 2231 // SelectionDAG::getConstant will promote SplatValue appropriately. 2232 SDValue Result = DAG.getConstant(SplatValue, ViaVecTy); 2233 2234 // Bitcast to the type we originally wanted 2235 if (ViaVecTy != ResTy) 2236 Result = DAG.getNode(ISD::BITCAST, SDLoc(Node), ResTy, Result); 2237 2238 return Result; 2239 } else if (isSplatVector(Node)) 2240 return Op; 2241 else if (!isConstantOrUndefBUILD_VECTOR(Node)) { 2242 // Use INSERT_VECTOR_ELT operations rather than expand to stores. 2243 // The resulting code is the same length as the expansion, but it doesn't 2244 // use memory operations 2245 EVT ResTy = Node->getValueType(0); 2246 2247 assert(ResTy.isVector()); 2248 2249 unsigned NumElts = ResTy.getVectorNumElements(); 2250 SDValue Vector = DAG.getUNDEF(ResTy); 2251 for (unsigned i = 0; i < NumElts; ++i) { 2252 Vector = DAG.getNode(ISD::INSERT_VECTOR_ELT, DL, ResTy, Vector, 2253 Node->getOperand(i), 2254 DAG.getConstant(i, MVT::i32)); 2255 } 2256 return Vector; 2257 } 2258 2259 return SDValue(); 2260 } 2261 2262 // Lower VECTOR_SHUFFLE into SHF (if possible). 2263 // 2264 // SHF splits the vector into blocks of four elements, then shuffles these 2265 // elements according to a <4 x i2> constant (encoded as an integer immediate). 2266 // 2267 // It is therefore possible to lower into SHF when the mask takes the form: 2268 // <a, b, c, d, a+4, b+4, c+4, d+4, a+8, b+8, c+8, d+8, ...> 2269 // When undef's appear they are treated as if they were whatever value is 2270 // necessary in order to fit the above form. 2271 // 2272 // For example: 2273 // %2 = shufflevector <8 x i16> %0, <8 x i16> undef, 2274 // <8 x i32> <i32 3, i32 2, i32 1, i32 0, 2275 // i32 7, i32 6, i32 5, i32 4> 2276 // is lowered to: 2277 // (SHF_H $w0, $w1, 27) 2278 // where the 27 comes from: 2279 // 3 + (2 << 2) + (1 << 4) + (0 << 6) 2280 static SDValue lowerVECTOR_SHUFFLE_SHF(SDValue Op, EVT ResTy, 2281 SmallVector<int, 16> Indices, 2282 SelectionDAG &DAG) { 2283 int SHFIndices[4] = { -1, -1, -1, -1 }; 2284 2285 if (Indices.size() < 4) 2286 return SDValue(); 2287 2288 for (unsigned i = 0; i < 4; ++i) { 2289 for (unsigned j = i; j < Indices.size(); j += 4) { 2290 int Idx = Indices[j]; 2291 2292 // Convert from vector index to 4-element subvector index 2293 // If an index refers to an element outside of the subvector then give up 2294 if (Idx != -1) { 2295 Idx -= 4 * (j / 4); 2296 if (Idx < 0 || Idx >= 4) 2297 return SDValue(); 2298 } 2299 2300 // If the mask has an undef, replace it with the current index. 2301 // Note that it might still be undef if the current index is also undef 2302 if (SHFIndices[i] == -1) 2303 SHFIndices[i] = Idx; 2304 2305 // Check that non-undef values are the same as in the mask. If they 2306 // aren't then give up 2307 if (!(Idx == -1 || Idx == SHFIndices[i])) 2308 return SDValue(); 2309 } 2310 } 2311 2312 // Calculate the immediate. Replace any remaining undefs with zero 2313 APInt Imm(32, 0); 2314 for (int i = 3; i >= 0; --i) { 2315 int Idx = SHFIndices[i]; 2316 2317 if (Idx == -1) 2318 Idx = 0; 2319 2320 Imm <<= 2; 2321 Imm |= Idx & 0x3; 2322 } 2323 2324 return DAG.getNode(MipsISD::SHF, SDLoc(Op), ResTy, 2325 DAG.getConstant(Imm, MVT::i32), Op->getOperand(0)); 2326 } 2327 2328 // Lower VECTOR_SHUFFLE into ILVEV (if possible). 2329 // 2330 // ILVEV interleaves the even elements from each vector. 2331 // 2332 // It is possible to lower into ILVEV when the mask takes the form: 2333 // <0, n, 2, n+2, 4, n+4, ...> 2334 // where n is the number of elements in the vector. 2335 // 2336 // When undef's appear in the mask they are treated as if they were whatever 2337 // value is necessary in order to fit the above form. 2338 static SDValue lowerVECTOR_SHUFFLE_ILVEV(SDValue Op, EVT ResTy, 2339 SmallVector<int, 16> Indices, 2340 SelectionDAG &DAG) { 2341 assert ((Indices.size() % 2) == 0); 2342 int WsIdx = 0; 2343 int WtIdx = ResTy.getVectorNumElements(); 2344 2345 for (unsigned i = 0; i < Indices.size(); i += 2) { 2346 if (Indices[i] != -1 && Indices[i] != WsIdx) 2347 return SDValue(); 2348 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2349 return SDValue(); 2350 WsIdx += 2; 2351 WtIdx += 2; 2352 } 2353 2354 return DAG.getNode(MipsISD::ILVEV, SDLoc(Op), ResTy, Op->getOperand(0), 2355 Op->getOperand(1)); 2356 } 2357 2358 // Lower VECTOR_SHUFFLE into ILVOD (if possible). 2359 // 2360 // ILVOD interleaves the odd elements from each vector. 2361 // 2362 // It is possible to lower into ILVOD when the mask takes the form: 2363 // <1, n+1, 3, n+3, 5, n+5, ...> 2364 // where n is the number of elements in the vector. 2365 // 2366 // When undef's appear in the mask they are treated as if they were whatever 2367 // value is necessary in order to fit the above form. 2368 static SDValue lowerVECTOR_SHUFFLE_ILVOD(SDValue Op, EVT ResTy, 2369 SmallVector<int, 16> Indices, 2370 SelectionDAG &DAG) { 2371 assert ((Indices.size() % 2) == 0); 2372 int WsIdx = 1; 2373 int WtIdx = ResTy.getVectorNumElements() + 1; 2374 2375 for (unsigned i = 0; i < Indices.size(); i += 2) { 2376 if (Indices[i] != -1 && Indices[i] != WsIdx) 2377 return SDValue(); 2378 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2379 return SDValue(); 2380 WsIdx += 2; 2381 WtIdx += 2; 2382 } 2383 2384 return DAG.getNode(MipsISD::ILVOD, SDLoc(Op), ResTy, Op->getOperand(0), 2385 Op->getOperand(1)); 2386 } 2387 2388 // Lower VECTOR_SHUFFLE into ILVL (if possible). 2389 // 2390 // ILVL interleaves consecutive elements from the left half of each vector. 2391 // 2392 // It is possible to lower into ILVL when the mask takes the form: 2393 // <0, n, 1, n+1, 2, n+2, ...> 2394 // where n is the number of elements in the vector. 2395 // 2396 // When undef's appear in the mask they are treated as if they were whatever 2397 // value is necessary in order to fit the above form. 2398 static SDValue lowerVECTOR_SHUFFLE_ILVL(SDValue Op, EVT ResTy, 2399 SmallVector<int, 16> Indices, 2400 SelectionDAG &DAG) { 2401 assert ((Indices.size() % 2) == 0); 2402 int WsIdx = 0; 2403 int WtIdx = ResTy.getVectorNumElements(); 2404 2405 for (unsigned i = 0; i < Indices.size(); i += 2) { 2406 if (Indices[i] != -1 && Indices[i] != WsIdx) 2407 return SDValue(); 2408 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2409 return SDValue(); 2410 WsIdx ++; 2411 WtIdx ++; 2412 } 2413 2414 return DAG.getNode(MipsISD::ILVL, SDLoc(Op), ResTy, Op->getOperand(0), 2415 Op->getOperand(1)); 2416 } 2417 2418 // Lower VECTOR_SHUFFLE into ILVR (if possible). 2419 // 2420 // ILVR interleaves consecutive elements from the right half of each vector. 2421 // 2422 // It is possible to lower into ILVR when the mask takes the form: 2423 // <x, n+x, x+1, n+x+1, x+2, n+x+2, ...> 2424 // where n is the number of elements in the vector and x is half n. 2425 // 2426 // When undef's appear in the mask they are treated as if they were whatever 2427 // value is necessary in order to fit the above form. 2428 static SDValue lowerVECTOR_SHUFFLE_ILVR(SDValue Op, EVT ResTy, 2429 SmallVector<int, 16> Indices, 2430 SelectionDAG &DAG) { 2431 assert ((Indices.size() % 2) == 0); 2432 unsigned NumElts = ResTy.getVectorNumElements(); 2433 int WsIdx = NumElts / 2; 2434 int WtIdx = NumElts + NumElts / 2; 2435 2436 for (unsigned i = 0; i < Indices.size(); i += 2) { 2437 if (Indices[i] != -1 && Indices[i] != WsIdx) 2438 return SDValue(); 2439 if (Indices[i+1] != -1 && Indices[i+1] != WtIdx) 2440 return SDValue(); 2441 WsIdx ++; 2442 WtIdx ++; 2443 } 2444 2445 return DAG.getNode(MipsISD::ILVR, SDLoc(Op), ResTy, Op->getOperand(0), 2446 Op->getOperand(1)); 2447 } 2448 2449 // Lower VECTOR_SHUFFLE into PCKEV (if possible). 2450 // 2451 // PCKEV copies the even elements of each vector into the result vector. 2452 // 2453 // It is possible to lower into PCKEV when the mask takes the form: 2454 // <0, 2, 4, ..., n, n+2, n+4, ...> 2455 // where n is the number of elements in the vector. 2456 // 2457 // When undef's appear in the mask they are treated as if they were whatever 2458 // value is necessary in order to fit the above form. 2459 static SDValue lowerVECTOR_SHUFFLE_PCKEV(SDValue Op, EVT ResTy, 2460 SmallVector<int, 16> Indices, 2461 SelectionDAG &DAG) { 2462 assert ((Indices.size() % 2) == 0); 2463 int Idx = 0; 2464 2465 for (unsigned i = 0; i < Indices.size(); ++i) { 2466 if (Indices[i] != -1 && Indices[i] != Idx) 2467 return SDValue(); 2468 Idx += 2; 2469 } 2470 2471 return DAG.getNode(MipsISD::PCKEV, SDLoc(Op), ResTy, Op->getOperand(0), 2472 Op->getOperand(1)); 2473 } 2474 2475 // Lower VECTOR_SHUFFLE into PCKOD (if possible). 2476 // 2477 // PCKOD copies the odd elements of each vector into the result vector. 2478 // 2479 // It is possible to lower into PCKOD when the mask takes the form: 2480 // <1, 3, 5, ..., n+1, n+3, n+5, ...> 2481 // where n is the number of elements in the vector. 2482 // 2483 // When undef's appear in the mask they are treated as if they were whatever 2484 // value is necessary in order to fit the above form. 2485 static SDValue lowerVECTOR_SHUFFLE_PCKOD(SDValue Op, EVT ResTy, 2486 SmallVector<int, 16> Indices, 2487 SelectionDAG &DAG) { 2488 assert ((Indices.size() % 2) == 0); 2489 int Idx = 1; 2490 2491 for (unsigned i = 0; i < Indices.size(); ++i) { 2492 if (Indices[i] != -1 && Indices[i] != Idx) 2493 return SDValue(); 2494 Idx += 2; 2495 } 2496 2497 return DAG.getNode(MipsISD::PCKOD, SDLoc(Op), ResTy, Op->getOperand(0), 2498 Op->getOperand(1)); 2499 } 2500 2501 // Lower VECTOR_SHUFFLE into VSHF. 2502 // 2503 // This mostly consists of converting the shuffle indices in Indices into a 2504 // BUILD_VECTOR and adding it as an operand to the resulting VSHF. There is 2505 // also code to eliminate unused operands of the VECTOR_SHUFFLE. For example, 2506 // if the type is v8i16 and all the indices are less than 8 then the second 2507 // operand is unused and can be replaced with anything. We choose to replace it 2508 // with the used operand since this reduces the number of instructions overall. 2509 static SDValue lowerVECTOR_SHUFFLE_VSHF(SDValue Op, EVT ResTy, 2510 SmallVector<int, 16> Indices, 2511 SelectionDAG &DAG) { 2512 SmallVector<SDValue, 16> Ops; 2513 SDValue Op0; 2514 SDValue Op1; 2515 EVT MaskVecTy = ResTy.changeVectorElementTypeToInteger(); 2516 EVT MaskEltTy = MaskVecTy.getVectorElementType(); 2517 bool Using1stVec = false; 2518 bool Using2ndVec = false; 2519 SDLoc DL(Op); 2520 int ResTyNumElts = ResTy.getVectorNumElements(); 2521 2522 for (int i = 0; i < ResTyNumElts; ++i) { 2523 // Idx == -1 means UNDEF 2524 int Idx = Indices[i]; 2525 2526 if (0 <= Idx && Idx < ResTyNumElts) 2527 Using1stVec = true; 2528 if (ResTyNumElts <= Idx && Idx < ResTyNumElts * 2) 2529 Using2ndVec = true; 2530 } 2531 2532 for (SmallVector<int, 16>::iterator I = Indices.begin(); I != Indices.end(); 2533 ++I) 2534 Ops.push_back(DAG.getTargetConstant(*I, MaskEltTy)); 2535 2536 SDValue MaskVec = DAG.getNode(ISD::BUILD_VECTOR, DL, MaskVecTy, &Ops[0], 2537 Ops.size()); 2538 2539 if (Using1stVec && Using2ndVec) { 2540 Op0 = Op->getOperand(0); 2541 Op1 = Op->getOperand(1); 2542 } else if (Using1stVec) 2543 Op0 = Op1 = Op->getOperand(0); 2544 else if (Using2ndVec) 2545 Op0 = Op1 = Op->getOperand(1); 2546 else 2547 llvm_unreachable("shuffle vector mask references neither vector operand?"); 2548 2549 return DAG.getNode(MipsISD::VSHF, DL, ResTy, MaskVec, Op0, Op1); 2550 } 2551 2552 // Lower VECTOR_SHUFFLE into one of a number of instructions depending on the 2553 // indices in the shuffle. 2554 SDValue MipsSETargetLowering::lowerVECTOR_SHUFFLE(SDValue Op, 2555 SelectionDAG &DAG) const { 2556 ShuffleVectorSDNode *Node = cast<ShuffleVectorSDNode>(Op); 2557 EVT ResTy = Op->getValueType(0); 2558 2559 if (!ResTy.is128BitVector()) 2560 return SDValue(); 2561 2562 int ResTyNumElts = ResTy.getVectorNumElements(); 2563 SmallVector<int, 16> Indices; 2564 2565 for (int i = 0; i < ResTyNumElts; ++i) 2566 Indices.push_back(Node->getMaskElt(i)); 2567 2568 SDValue Result = lowerVECTOR_SHUFFLE_SHF(Op, ResTy, Indices, DAG); 2569 if (Result.getNode()) 2570 return Result; 2571 Result = lowerVECTOR_SHUFFLE_ILVEV(Op, ResTy, Indices, DAG); 2572 if (Result.getNode()) 2573 return Result; 2574 Result = lowerVECTOR_SHUFFLE_ILVOD(Op, ResTy, Indices, DAG); 2575 if (Result.getNode()) 2576 return Result; 2577 Result = lowerVECTOR_SHUFFLE_ILVL(Op, ResTy, Indices, DAG); 2578 if (Result.getNode()) 2579 return Result; 2580 Result = lowerVECTOR_SHUFFLE_ILVR(Op, ResTy, Indices, DAG); 2581 if (Result.getNode()) 2582 return Result; 2583 Result = lowerVECTOR_SHUFFLE_PCKEV(Op, ResTy, Indices, DAG); 2584 if (Result.getNode()) 2585 return Result; 2586 Result = lowerVECTOR_SHUFFLE_PCKOD(Op, ResTy, Indices, DAG); 2587 if (Result.getNode()) 2588 return Result; 2589 return lowerVECTOR_SHUFFLE_VSHF(Op, ResTy, Indices, DAG); 2590 } 2591 2592 MachineBasicBlock * MipsSETargetLowering:: 2593 emitBPOSGE32(MachineInstr *MI, MachineBasicBlock *BB) const{ 2594 // $bb: 2595 // bposge32_pseudo $vr0 2596 // => 2597 // $bb: 2598 // bposge32 $tbb 2599 // $fbb: 2600 // li $vr2, 0 2601 // b $sink 2602 // $tbb: 2603 // li $vr1, 1 2604 // $sink: 2605 // $vr0 = phi($vr2, $fbb, $vr1, $tbb) 2606 2607 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2608 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2609 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2610 DebugLoc DL = MI->getDebugLoc(); 2611 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2612 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2613 MachineFunction *F = BB->getParent(); 2614 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2615 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2616 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2617 F->insert(It, FBB); 2618 F->insert(It, TBB); 2619 F->insert(It, Sink); 2620 2621 // Transfer the remainder of BB and its successor edges to Sink. 2622 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2623 BB->end()); 2624 Sink->transferSuccessorsAndUpdatePHIs(BB); 2625 2626 // Add successors. 2627 BB->addSuccessor(FBB); 2628 BB->addSuccessor(TBB); 2629 FBB->addSuccessor(Sink); 2630 TBB->addSuccessor(Sink); 2631 2632 // Insert the real bposge32 instruction to $BB. 2633 BuildMI(BB, DL, TII->get(Mips::BPOSGE32)).addMBB(TBB); 2634 2635 // Fill $FBB. 2636 unsigned VR2 = RegInfo.createVirtualRegister(RC); 2637 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), VR2) 2638 .addReg(Mips::ZERO).addImm(0); 2639 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2640 2641 // Fill $TBB. 2642 unsigned VR1 = RegInfo.createVirtualRegister(RC); 2643 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), VR1) 2644 .addReg(Mips::ZERO).addImm(1); 2645 2646 // Insert phi function to $Sink. 2647 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2648 MI->getOperand(0).getReg()) 2649 .addReg(VR2).addMBB(FBB).addReg(VR1).addMBB(TBB); 2650 2651 MI->eraseFromParent(); // The pseudo instruction is gone now. 2652 return Sink; 2653 } 2654 2655 MachineBasicBlock * MipsSETargetLowering:: 2656 emitMSACBranchPseudo(MachineInstr *MI, MachineBasicBlock *BB, 2657 unsigned BranchOp) const{ 2658 // $bb: 2659 // vany_nonzero $rd, $ws 2660 // => 2661 // $bb: 2662 // bnz.b $ws, $tbb 2663 // b $fbb 2664 // $fbb: 2665 // li $rd1, 0 2666 // b $sink 2667 // $tbb: 2668 // li $rd2, 1 2669 // $sink: 2670 // $rd = phi($rd1, $fbb, $rd2, $tbb) 2671 2672 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2673 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2674 const TargetRegisterClass *RC = &Mips::GPR32RegClass; 2675 DebugLoc DL = MI->getDebugLoc(); 2676 const BasicBlock *LLVM_BB = BB->getBasicBlock(); 2677 MachineFunction::iterator It = llvm::next(MachineFunction::iterator(BB)); 2678 MachineFunction *F = BB->getParent(); 2679 MachineBasicBlock *FBB = F->CreateMachineBasicBlock(LLVM_BB); 2680 MachineBasicBlock *TBB = F->CreateMachineBasicBlock(LLVM_BB); 2681 MachineBasicBlock *Sink = F->CreateMachineBasicBlock(LLVM_BB); 2682 F->insert(It, FBB); 2683 F->insert(It, TBB); 2684 F->insert(It, Sink); 2685 2686 // Transfer the remainder of BB and its successor edges to Sink. 2687 Sink->splice(Sink->begin(), BB, llvm::next(MachineBasicBlock::iterator(MI)), 2688 BB->end()); 2689 Sink->transferSuccessorsAndUpdatePHIs(BB); 2690 2691 // Add successors. 2692 BB->addSuccessor(FBB); 2693 BB->addSuccessor(TBB); 2694 FBB->addSuccessor(Sink); 2695 TBB->addSuccessor(Sink); 2696 2697 // Insert the real bnz.b instruction to $BB. 2698 BuildMI(BB, DL, TII->get(BranchOp)) 2699 .addReg(MI->getOperand(1).getReg()) 2700 .addMBB(TBB); 2701 2702 // Fill $FBB. 2703 unsigned RD1 = RegInfo.createVirtualRegister(RC); 2704 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::ADDiu), RD1) 2705 .addReg(Mips::ZERO).addImm(0); 2706 BuildMI(*FBB, FBB->end(), DL, TII->get(Mips::B)).addMBB(Sink); 2707 2708 // Fill $TBB. 2709 unsigned RD2 = RegInfo.createVirtualRegister(RC); 2710 BuildMI(*TBB, TBB->end(), DL, TII->get(Mips::ADDiu), RD2) 2711 .addReg(Mips::ZERO).addImm(1); 2712 2713 // Insert phi function to $Sink. 2714 BuildMI(*Sink, Sink->begin(), DL, TII->get(Mips::PHI), 2715 MI->getOperand(0).getReg()) 2716 .addReg(RD1).addMBB(FBB).addReg(RD2).addMBB(TBB); 2717 2718 MI->eraseFromParent(); // The pseudo instruction is gone now. 2719 return Sink; 2720 } 2721 2722 // Emit the COPY_FW pseudo instruction. 2723 // 2724 // copy_fw_pseudo $fd, $ws, n 2725 // => 2726 // copy_u_w $rt, $ws, $n 2727 // mtc1 $rt, $fd 2728 // 2729 // When n is zero, the equivalent operation can be performed with (potentially) 2730 // zero instructions due to register overlaps. This optimization is never valid 2731 // for lane 1 because it would require FR=0 mode which isn't supported by MSA. 2732 MachineBasicBlock * MipsSETargetLowering:: 2733 emitCOPY_FW(MachineInstr *MI, MachineBasicBlock *BB) const{ 2734 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2735 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2736 DebugLoc DL = MI->getDebugLoc(); 2737 unsigned Fd = MI->getOperand(0).getReg(); 2738 unsigned Ws = MI->getOperand(1).getReg(); 2739 unsigned Lane = MI->getOperand(2).getImm(); 2740 2741 if (Lane == 0) 2742 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_lo); 2743 else { 2744 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2745 2746 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wt).addReg(Ws).addImm(1); 2747 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_lo); 2748 } 2749 2750 MI->eraseFromParent(); // The pseudo instruction is gone now. 2751 return BB; 2752 } 2753 2754 // Emit the COPY_FD pseudo instruction. 2755 // 2756 // copy_fd_pseudo $fd, $ws, n 2757 // => 2758 // splati.d $wt, $ws, $n 2759 // copy $fd, $wt:sub_64 2760 // 2761 // When n is zero, the equivalent operation can be performed with (potentially) 2762 // zero instructions due to register overlaps. This optimization is always 2763 // valid because FR=1 mode which is the only supported mode in MSA. 2764 MachineBasicBlock * MipsSETargetLowering:: 2765 emitCOPY_FD(MachineInstr *MI, MachineBasicBlock *BB) const{ 2766 assert(Subtarget->isFP64bit()); 2767 2768 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2769 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2770 unsigned Fd = MI->getOperand(0).getReg(); 2771 unsigned Ws = MI->getOperand(1).getReg(); 2772 unsigned Lane = MI->getOperand(2).getImm() * 2; 2773 DebugLoc DL = MI->getDebugLoc(); 2774 2775 if (Lane == 0) 2776 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Ws, 0, Mips::sub_64); 2777 else { 2778 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2779 2780 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wt).addReg(Ws).addImm(1); 2781 BuildMI(*BB, MI, DL, TII->get(Mips::COPY), Fd).addReg(Wt, 0, Mips::sub_64); 2782 } 2783 2784 MI->eraseFromParent(); // The pseudo instruction is gone now. 2785 return BB; 2786 } 2787 2788 // Emit the INSERT_FW pseudo instruction. 2789 // 2790 // insert_fw_pseudo $wd, $wd_in, $n, $fs 2791 // => 2792 // subreg_to_reg $wt:sub_lo, $fs 2793 // insve_w $wd[$n], $wd_in, $wt[0] 2794 MachineBasicBlock * 2795 MipsSETargetLowering::emitINSERT_FW(MachineInstr *MI, 2796 MachineBasicBlock *BB) const { 2797 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2798 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2799 DebugLoc DL = MI->getDebugLoc(); 2800 unsigned Wd = MI->getOperand(0).getReg(); 2801 unsigned Wd_in = MI->getOperand(1).getReg(); 2802 unsigned Lane = MI->getOperand(2).getImm(); 2803 unsigned Fs = MI->getOperand(3).getReg(); 2804 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2805 2806 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2807 .addImm(0) 2808 .addReg(Fs) 2809 .addImm(Mips::sub_lo); 2810 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_W), Wd) 2811 .addReg(Wd_in) 2812 .addImm(Lane) 2813 .addReg(Wt); 2814 2815 MI->eraseFromParent(); // The pseudo instruction is gone now. 2816 return BB; 2817 } 2818 2819 // Emit the INSERT_FD pseudo instruction. 2820 // 2821 // insert_fd_pseudo $wd, $fs, n 2822 // => 2823 // subreg_to_reg $wt:sub_64, $fs 2824 // insve_d $wd[$n], $wd_in, $wt[0] 2825 MachineBasicBlock * 2826 MipsSETargetLowering::emitINSERT_FD(MachineInstr *MI, 2827 MachineBasicBlock *BB) const { 2828 assert(Subtarget->isFP64bit()); 2829 2830 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2831 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2832 DebugLoc DL = MI->getDebugLoc(); 2833 unsigned Wd = MI->getOperand(0).getReg(); 2834 unsigned Wd_in = MI->getOperand(1).getReg(); 2835 unsigned Lane = MI->getOperand(2).getImm(); 2836 unsigned Fs = MI->getOperand(3).getReg(); 2837 unsigned Wt = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2838 2839 BuildMI(*BB, MI, DL, TII->get(Mips::SUBREG_TO_REG), Wt) 2840 .addImm(0) 2841 .addReg(Fs) 2842 .addImm(Mips::sub_64); 2843 BuildMI(*BB, MI, DL, TII->get(Mips::INSVE_D), Wd) 2844 .addReg(Wd_in) 2845 .addImm(Lane) 2846 .addReg(Wt); 2847 2848 MI->eraseFromParent(); // The pseudo instruction is gone now. 2849 return BB; 2850 } 2851 2852 // Emit the FILL_FW pseudo instruction. 2853 // 2854 // fill_fw_pseudo $wd, $fs 2855 // => 2856 // implicit_def $wt1 2857 // insert_subreg $wt2:subreg_lo, $wt1, $fs 2858 // splati.w $wd, $wt2[0] 2859 MachineBasicBlock * 2860 MipsSETargetLowering::emitFILL_FW(MachineInstr *MI, 2861 MachineBasicBlock *BB) const { 2862 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2863 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2864 DebugLoc DL = MI->getDebugLoc(); 2865 unsigned Wd = MI->getOperand(0).getReg(); 2866 unsigned Fs = MI->getOperand(1).getReg(); 2867 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2868 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128WRegClass); 2869 2870 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2871 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2872 .addReg(Wt1) 2873 .addReg(Fs) 2874 .addImm(Mips::sub_lo); 2875 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_W), Wd).addReg(Wt2).addImm(0); 2876 2877 MI->eraseFromParent(); // The pseudo instruction is gone now. 2878 return BB; 2879 } 2880 2881 // Emit the FILL_FD pseudo instruction. 2882 // 2883 // fill_fd_pseudo $wd, $fs 2884 // => 2885 // implicit_def $wt1 2886 // insert_subreg $wt2:subreg_64, $wt1, $fs 2887 // splati.d $wd, $wt2[0] 2888 MachineBasicBlock * 2889 MipsSETargetLowering::emitFILL_FD(MachineInstr *MI, 2890 MachineBasicBlock *BB) const { 2891 assert(Subtarget->isFP64bit()); 2892 2893 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2894 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2895 DebugLoc DL = MI->getDebugLoc(); 2896 unsigned Wd = MI->getOperand(0).getReg(); 2897 unsigned Fs = MI->getOperand(1).getReg(); 2898 unsigned Wt1 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2899 unsigned Wt2 = RegInfo.createVirtualRegister(&Mips::MSA128DRegClass); 2900 2901 BuildMI(*BB, MI, DL, TII->get(Mips::IMPLICIT_DEF), Wt1); 2902 BuildMI(*BB, MI, DL, TII->get(Mips::INSERT_SUBREG), Wt2) 2903 .addReg(Wt1) 2904 .addReg(Fs) 2905 .addImm(Mips::sub_64); 2906 BuildMI(*BB, MI, DL, TII->get(Mips::SPLATI_D), Wd).addReg(Wt2).addImm(0); 2907 2908 MI->eraseFromParent(); // The pseudo instruction is gone now. 2909 return BB; 2910 } 2911 2912 // Emit the FEXP2_W_1 pseudo instructions. 2913 // 2914 // fexp2_w_1_pseudo $wd, $wt 2915 // => 2916 // ldi.w $ws, 1 2917 // fexp2.w $wd, $ws, $wt 2918 MachineBasicBlock * 2919 MipsSETargetLowering::emitFEXP2_W_1(MachineInstr *MI, 2920 MachineBasicBlock *BB) const { 2921 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2922 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2923 const TargetRegisterClass *RC = &Mips::MSA128WRegClass; 2924 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 2925 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 2926 DebugLoc DL = MI->getDebugLoc(); 2927 2928 // Splat 1.0 into a vector 2929 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_W), Ws1).addImm(1); 2930 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_W), Ws2).addReg(Ws1); 2931 2932 // Emit 1.0 * fexp2(Wt) 2933 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_W), MI->getOperand(0).getReg()) 2934 .addReg(Ws2) 2935 .addReg(MI->getOperand(1).getReg()); 2936 2937 MI->eraseFromParent(); // The pseudo instruction is gone now. 2938 return BB; 2939 } 2940 2941 // Emit the FEXP2_D_1 pseudo instructions. 2942 // 2943 // fexp2_d_1_pseudo $wd, $wt 2944 // => 2945 // ldi.d $ws, 1 2946 // fexp2.d $wd, $ws, $wt 2947 MachineBasicBlock * 2948 MipsSETargetLowering::emitFEXP2_D_1(MachineInstr *MI, 2949 MachineBasicBlock *BB) const { 2950 const TargetInstrInfo *TII = getTargetMachine().getInstrInfo(); 2951 MachineRegisterInfo &RegInfo = BB->getParent()->getRegInfo(); 2952 const TargetRegisterClass *RC = &Mips::MSA128DRegClass; 2953 unsigned Ws1 = RegInfo.createVirtualRegister(RC); 2954 unsigned Ws2 = RegInfo.createVirtualRegister(RC); 2955 DebugLoc DL = MI->getDebugLoc(); 2956 2957 // Splat 1.0 into a vector 2958 BuildMI(*BB, MI, DL, TII->get(Mips::LDI_D), Ws1).addImm(1); 2959 BuildMI(*BB, MI, DL, TII->get(Mips::FFINT_U_D), Ws2).addReg(Ws1); 2960 2961 // Emit 1.0 * fexp2(Wt) 2962 BuildMI(*BB, MI, DL, TII->get(Mips::FEXP2_D), MI->getOperand(0).getReg()) 2963 .addReg(Ws2) 2964 .addReg(MI->getOperand(1).getReg()); 2965 2966 MI->eraseFromParent(); // The pseudo instruction is gone now. 2967 return BB; 2968 } 2969