1 //===-- MipsSEISelDAGToDAG.cpp - A Dag to Dag Inst Selector for MipsSE ----===//
2 //
3 //                     The LLVM Compiler Infrastructure
4 //
5 // This file is distributed under the University of Illinois Open Source
6 // License. See LICENSE.TXT for details.
7 //
8 //===----------------------------------------------------------------------===//
9 //
10 // Subclass of MipsDAGToDAGISel specialized for mips32/64.
11 //
12 //===----------------------------------------------------------------------===//
13 
14 #include "MipsSEISelDAGToDAG.h"
15 #include "MCTargetDesc/MipsBaseInfo.h"
16 #include "Mips.h"
17 #include "MipsAnalyzeImmediate.h"
18 #include "MipsMachineFunction.h"
19 #include "MipsRegisterInfo.h"
20 #include "llvm/CodeGen/MachineConstantPool.h"
21 #include "llvm/CodeGen/MachineFrameInfo.h"
22 #include "llvm/CodeGen/MachineFunction.h"
23 #include "llvm/CodeGen/MachineInstrBuilder.h"
24 #include "llvm/CodeGen/MachineRegisterInfo.h"
25 #include "llvm/CodeGen/SelectionDAGNodes.h"
26 #include "llvm/IR/CFG.h"
27 #include "llvm/IR/GlobalValue.h"
28 #include "llvm/IR/Instructions.h"
29 #include "llvm/IR/Intrinsics.h"
30 #include "llvm/IR/Type.h"
31 #include "llvm/Support/Debug.h"
32 #include "llvm/Support/ErrorHandling.h"
33 #include "llvm/Support/raw_ostream.h"
34 #include "llvm/Target/TargetMachine.h"
35 using namespace llvm;
36 
37 #define DEBUG_TYPE "mips-isel"
38 
39 bool MipsSEDAGToDAGISel::runOnMachineFunction(MachineFunction &MF) {
40   Subtarget = &TM.getSubtarget<MipsSubtarget>();
41   if (Subtarget->inMips16Mode())
42     return false;
43   return MipsDAGToDAGISel::runOnMachineFunction(MF);
44 }
45 
46 void MipsSEDAGToDAGISel::addDSPCtrlRegOperands(bool IsDef, MachineInstr &MI,
47                                                MachineFunction &MF) {
48   MachineInstrBuilder MIB(MF, &MI);
49   unsigned Mask = MI.getOperand(1).getImm();
50   unsigned Flag = IsDef ? RegState::ImplicitDefine : RegState::Implicit;
51 
52   if (Mask & 1)
53     MIB.addReg(Mips::DSPPos, Flag);
54 
55   if (Mask & 2)
56     MIB.addReg(Mips::DSPSCount, Flag);
57 
58   if (Mask & 4)
59     MIB.addReg(Mips::DSPCarry, Flag);
60 
61   if (Mask & 8)
62     MIB.addReg(Mips::DSPOutFlag, Flag);
63 
64   if (Mask & 16)
65     MIB.addReg(Mips::DSPCCond, Flag);
66 
67   if (Mask & 32)
68     MIB.addReg(Mips::DSPEFI, Flag);
69 }
70 
71 unsigned MipsSEDAGToDAGISel::getMSACtrlReg(const SDValue RegIdx) const {
72   switch (cast<ConstantSDNode>(RegIdx)->getZExtValue()) {
73   default:
74     llvm_unreachable("Could not map int to register");
75   case 0: return Mips::MSAIR;
76   case 1: return Mips::MSACSR;
77   case 2: return Mips::MSAAccess;
78   case 3: return Mips::MSASave;
79   case 4: return Mips::MSAModify;
80   case 5: return Mips::MSARequest;
81   case 6: return Mips::MSAMap;
82   case 7: return Mips::MSAUnmap;
83   }
84 }
85 
86 bool MipsSEDAGToDAGISel::replaceUsesWithZeroReg(MachineRegisterInfo *MRI,
87                                                 const MachineInstr& MI) {
88   unsigned DstReg = 0, ZeroReg = 0;
89 
90   // Check if MI is "addiu $dst, $zero, 0" or "daddiu $dst, $zero, 0".
91   if ((MI.getOpcode() == Mips::ADDiu) &&
92       (MI.getOperand(1).getReg() == Mips::ZERO) &&
93       (MI.getOperand(2).getImm() == 0)) {
94     DstReg = MI.getOperand(0).getReg();
95     ZeroReg = Mips::ZERO;
96   } else if ((MI.getOpcode() == Mips::DADDiu) &&
97              (MI.getOperand(1).getReg() == Mips::ZERO_64) &&
98              (MI.getOperand(2).getImm() == 0)) {
99     DstReg = MI.getOperand(0).getReg();
100     ZeroReg = Mips::ZERO_64;
101   }
102 
103   if (!DstReg)
104     return false;
105 
106   // Replace uses with ZeroReg.
107   for (MachineRegisterInfo::use_iterator U = MRI->use_begin(DstReg),
108        E = MRI->use_end(); U != E;) {
109     MachineOperand &MO = *U;
110     unsigned OpNo = U.getOperandNo();
111     MachineInstr *MI = MO.getParent();
112     ++U;
113 
114     // Do not replace if it is a phi's operand or is tied to def operand.
115     if (MI->isPHI() || MI->isRegTiedToDefOperand(OpNo) || MI->isPseudo())
116       continue;
117 
118     MO.setReg(ZeroReg);
119   }
120 
121   return true;
122 }
123 
124 void MipsSEDAGToDAGISel::initGlobalBaseReg(MachineFunction &MF) {
125   MipsFunctionInfo *MipsFI = MF.getInfo<MipsFunctionInfo>();
126 
127   if (!MipsFI->globalBaseRegSet())
128     return;
129 
130   MachineBasicBlock &MBB = MF.front();
131   MachineBasicBlock::iterator I = MBB.begin();
132   MachineRegisterInfo &RegInfo = MF.getRegInfo();
133   const TargetInstrInfo &TII = *MF.getSubtarget().getInstrInfo();
134   DebugLoc DL = I != MBB.end() ? I->getDebugLoc() : DebugLoc();
135   unsigned V0, V1, GlobalBaseReg = MipsFI->getGlobalBaseReg();
136   const TargetRegisterClass *RC;
137 
138   if (Subtarget->isABI_N64())
139     RC = (const TargetRegisterClass*)&Mips::GPR64RegClass;
140   else
141     RC = (const TargetRegisterClass*)&Mips::GPR32RegClass;
142 
143   V0 = RegInfo.createVirtualRegister(RC);
144   V1 = RegInfo.createVirtualRegister(RC);
145 
146   if (Subtarget->isABI_N64()) {
147     MF.getRegInfo().addLiveIn(Mips::T9_64);
148     MBB.addLiveIn(Mips::T9_64);
149 
150     // lui $v0, %hi(%neg(%gp_rel(fname)))
151     // daddu $v1, $v0, $t9
152     // daddiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
153     const GlobalValue *FName = MF.getFunction();
154     BuildMI(MBB, I, DL, TII.get(Mips::LUi64), V0)
155       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
156     BuildMI(MBB, I, DL, TII.get(Mips::DADDu), V1).addReg(V0)
157       .addReg(Mips::T9_64);
158     BuildMI(MBB, I, DL, TII.get(Mips::DADDiu), GlobalBaseReg).addReg(V1)
159       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
160     return;
161   }
162 
163   if (MF.getTarget().getRelocationModel() == Reloc::Static) {
164     // Set global register to __gnu_local_gp.
165     //
166     // lui   $v0, %hi(__gnu_local_gp)
167     // addiu $globalbasereg, $v0, %lo(__gnu_local_gp)
168     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
169       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_HI);
170     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V0)
171       .addExternalSymbol("__gnu_local_gp", MipsII::MO_ABS_LO);
172     return;
173   }
174 
175   MF.getRegInfo().addLiveIn(Mips::T9);
176   MBB.addLiveIn(Mips::T9);
177 
178   if (Subtarget->isABI_N32()) {
179     // lui $v0, %hi(%neg(%gp_rel(fname)))
180     // addu $v1, $v0, $t9
181     // addiu $globalbasereg, $v1, %lo(%neg(%gp_rel(fname)))
182     const GlobalValue *FName = MF.getFunction();
183     BuildMI(MBB, I, DL, TII.get(Mips::LUi), V0)
184       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_HI);
185     BuildMI(MBB, I, DL, TII.get(Mips::ADDu), V1).addReg(V0).addReg(Mips::T9);
186     BuildMI(MBB, I, DL, TII.get(Mips::ADDiu), GlobalBaseReg).addReg(V1)
187       .addGlobalAddress(FName, 0, MipsII::MO_GPOFF_LO);
188     return;
189   }
190 
191   assert(Subtarget->isABI_O32());
192 
193   // For O32 ABI, the following instruction sequence is emitted to initialize
194   // the global base register:
195   //
196   //  0. lui   $2, %hi(_gp_disp)
197   //  1. addiu $2, $2, %lo(_gp_disp)
198   //  2. addu  $globalbasereg, $2, $t9
199   //
200   // We emit only the last instruction here.
201   //
202   // GNU linker requires that the first two instructions appear at the beginning
203   // of a function and no instructions be inserted before or between them.
204   // The two instructions are emitted during lowering to MC layer in order to
205   // avoid any reordering.
206   //
207   // Register $2 (Mips::V0) is added to the list of live-in registers to ensure
208   // the value instruction 1 (addiu) defines is valid when instruction 2 (addu)
209   // reads it.
210   MF.getRegInfo().addLiveIn(Mips::V0);
211   MBB.addLiveIn(Mips::V0);
212   BuildMI(MBB, I, DL, TII.get(Mips::ADDu), GlobalBaseReg)
213     .addReg(Mips::V0).addReg(Mips::T9);
214 }
215 
216 void MipsSEDAGToDAGISel::processFunctionAfterISel(MachineFunction &MF) {
217   initGlobalBaseReg(MF);
218 
219   MachineRegisterInfo *MRI = &MF.getRegInfo();
220 
221   for (MachineFunction::iterator MFI = MF.begin(), MFE = MF.end(); MFI != MFE;
222        ++MFI)
223     for (MachineBasicBlock::iterator I = MFI->begin(); I != MFI->end(); ++I) {
224       if (I->getOpcode() == Mips::RDDSP)
225         addDSPCtrlRegOperands(false, *I, MF);
226       else if (I->getOpcode() == Mips::WRDSP)
227         addDSPCtrlRegOperands(true, *I, MF);
228       else
229         replaceUsesWithZeroReg(MRI, *I);
230     }
231 }
232 
233 SDNode *MipsSEDAGToDAGISel::selectAddESubE(unsigned MOp, SDValue InFlag,
234                                            SDValue CmpLHS, SDLoc DL,
235                                            SDNode *Node) const {
236   unsigned Opc = InFlag.getOpcode(); (void)Opc;
237 
238   assert(((Opc == ISD::ADDC || Opc == ISD::ADDE) ||
239           (Opc == ISD::SUBC || Opc == ISD::SUBE)) &&
240          "(ADD|SUB)E flag operand must come from (ADD|SUB)C/E insn");
241 
242   SDValue Ops[] = { CmpLHS, InFlag.getOperand(1) };
243   SDValue LHS = Node->getOperand(0), RHS = Node->getOperand(1);
244   EVT VT = LHS.getValueType();
245 
246   SDNode *Carry = CurDAG->getMachineNode(Mips::SLTu, DL, VT, Ops);
247   SDNode *AddCarry = CurDAG->getMachineNode(Mips::ADDu, DL, VT,
248                                             SDValue(Carry, 0), RHS);
249   return CurDAG->SelectNodeTo(Node, MOp, VT, MVT::Glue, LHS,
250                               SDValue(AddCarry, 0));
251 }
252 
253 /// Match frameindex
254 bool MipsSEDAGToDAGISel::selectAddrFrameIndex(SDValue Addr, SDValue &Base,
255                                               SDValue &Offset) const {
256   if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>(Addr)) {
257     EVT ValTy = Addr.getValueType();
258 
259     Base   = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
260     Offset = CurDAG->getTargetConstant(0, ValTy);
261     return true;
262   }
263   return false;
264 }
265 
266 /// Match frameindex+offset and frameindex|offset
267 bool MipsSEDAGToDAGISel::selectAddrFrameIndexOffset(SDValue Addr, SDValue &Base,
268                                                     SDValue &Offset,
269                                                     unsigned OffsetBits) const {
270   if (CurDAG->isBaseWithConstantOffset(Addr)) {
271     ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1));
272     if (isIntN(OffsetBits, CN->getSExtValue())) {
273       EVT ValTy = Addr.getValueType();
274 
275       // If the first operand is a FI, get the TargetFI Node
276       if (FrameIndexSDNode *FIN = dyn_cast<FrameIndexSDNode>
277                                   (Addr.getOperand(0)))
278         Base = CurDAG->getTargetFrameIndex(FIN->getIndex(), ValTy);
279       else
280         Base = Addr.getOperand(0);
281 
282       Offset = CurDAG->getTargetConstant(CN->getZExtValue(), ValTy);
283       return true;
284     }
285   }
286   return false;
287 }
288 
289 /// ComplexPattern used on MipsInstrInfo
290 /// Used on Mips Load/Store instructions
291 bool MipsSEDAGToDAGISel::selectAddrRegImm(SDValue Addr, SDValue &Base,
292                                           SDValue &Offset) const {
293   // if Address is FI, get the TargetFrameIndex.
294   if (selectAddrFrameIndex(Addr, Base, Offset))
295     return true;
296 
297   // on PIC code Load GA
298   if (Addr.getOpcode() == MipsISD::Wrapper) {
299     Base   = Addr.getOperand(0);
300     Offset = Addr.getOperand(1);
301     return true;
302   }
303 
304   if (TM.getRelocationModel() != Reloc::PIC_) {
305     if ((Addr.getOpcode() == ISD::TargetExternalSymbol ||
306         Addr.getOpcode() == ISD::TargetGlobalAddress))
307       return false;
308   }
309 
310   // Addresses of the form FI+const or FI|const
311   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 16))
312     return true;
313 
314   // Operand is a result from an ADD.
315   if (Addr.getOpcode() == ISD::ADD) {
316     // When loading from constant pools, load the lower address part in
317     // the instruction itself. Example, instead of:
318     //  lui $2, %hi($CPI1_0)
319     //  addiu $2, $2, %lo($CPI1_0)
320     //  lwc1 $f0, 0($2)
321     // Generate:
322     //  lui $2, %hi($CPI1_0)
323     //  lwc1 $f0, %lo($CPI1_0)($2)
324     if (Addr.getOperand(1).getOpcode() == MipsISD::Lo ||
325         Addr.getOperand(1).getOpcode() == MipsISD::GPRel) {
326       SDValue Opnd0 = Addr.getOperand(1).getOperand(0);
327       if (isa<ConstantPoolSDNode>(Opnd0) || isa<GlobalAddressSDNode>(Opnd0) ||
328           isa<JumpTableSDNode>(Opnd0)) {
329         Base = Addr.getOperand(0);
330         Offset = Opnd0;
331         return true;
332       }
333     }
334   }
335 
336   return false;
337 }
338 
339 /// ComplexPattern used on MipsInstrInfo
340 /// Used on Mips Load/Store instructions
341 bool MipsSEDAGToDAGISel::selectAddrRegReg(SDValue Addr, SDValue &Base,
342                                           SDValue &Offset) const {
343   // Operand is a result from an ADD.
344   if (Addr.getOpcode() == ISD::ADD) {
345     Base = Addr.getOperand(0);
346     Offset = Addr.getOperand(1);
347     return true;
348   }
349 
350   return false;
351 }
352 
353 bool MipsSEDAGToDAGISel::selectAddrDefault(SDValue Addr, SDValue &Base,
354                                            SDValue &Offset) const {
355   Base = Addr;
356   Offset = CurDAG->getTargetConstant(0, Addr.getValueType());
357   return true;
358 }
359 
360 bool MipsSEDAGToDAGISel::selectIntAddr(SDValue Addr, SDValue &Base,
361                                        SDValue &Offset) const {
362   return selectAddrRegImm(Addr, Base, Offset) ||
363     selectAddrDefault(Addr, Base, Offset);
364 }
365 
366 bool MipsSEDAGToDAGISel::selectAddrRegImm10(SDValue Addr, SDValue &Base,
367                                             SDValue &Offset) const {
368   if (selectAddrFrameIndex(Addr, Base, Offset))
369     return true;
370 
371   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 10))
372     return true;
373 
374   return false;
375 }
376 
377 /// Used on microMIPS Load/Store unaligned instructions (12-bit offset)
378 bool MipsSEDAGToDAGISel::selectAddrRegImm12(SDValue Addr, SDValue &Base,
379                                             SDValue &Offset) const {
380   if (selectAddrFrameIndex(Addr, Base, Offset))
381     return true;
382 
383   if (selectAddrFrameIndexOffset(Addr, Base, Offset, 12))
384     return true;
385 
386   return false;
387 }
388 
389 bool MipsSEDAGToDAGISel::selectIntAddrMM(SDValue Addr, SDValue &Base,
390                                          SDValue &Offset) const {
391   return selectAddrRegImm12(Addr, Base, Offset) ||
392     selectAddrDefault(Addr, Base, Offset);
393 }
394 
395 bool MipsSEDAGToDAGISel::selectIntAddrMSA(SDValue Addr, SDValue &Base,
396                                           SDValue &Offset) const {
397   if (selectAddrRegImm10(Addr, Base, Offset))
398     return true;
399 
400   if (selectAddrDefault(Addr, Base, Offset))
401     return true;
402 
403   return false;
404 }
405 
406 // Select constant vector splats.
407 //
408 // Returns true and sets Imm if:
409 // * MSA is enabled
410 // * N is a ISD::BUILD_VECTOR representing a constant splat
411 bool MipsSEDAGToDAGISel::selectVSplat(SDNode *N, APInt &Imm) const {
412   if (!Subtarget->hasMSA())
413     return false;
414 
415   BuildVectorSDNode *Node = dyn_cast<BuildVectorSDNode>(N);
416 
417   if (!Node)
418     return false;
419 
420   APInt SplatValue, SplatUndef;
421   unsigned SplatBitSize;
422   bool HasAnyUndefs;
423 
424   if (!Node->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
425                              HasAnyUndefs, 8,
426                              !Subtarget->isLittle()))
427     return false;
428 
429   Imm = SplatValue;
430 
431   return true;
432 }
433 
434 // Select constant vector splats.
435 //
436 // In addition to the requirements of selectVSplat(), this function returns
437 // true and sets Imm if:
438 // * The splat value is the same width as the elements of the vector
439 // * The splat value fits in an integer with the specified signed-ness and
440 //   width.
441 //
442 // This function looks through ISD::BITCAST nodes.
443 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
444 //       sometimes a shuffle in big-endian mode.
445 //
446 // It's worth noting that this function is not used as part of the selection
447 // of ldi.[bhwd] since it does not permit using the wrong-typed ldi.[bhwd]
448 // instruction to achieve the desired bit pattern. ldi.[bhwd] is selected in
449 // MipsSEDAGToDAGISel::selectNode.
450 bool MipsSEDAGToDAGISel::
451 selectVSplatCommon(SDValue N, SDValue &Imm, bool Signed,
452                    unsigned ImmBitSize) const {
453   APInt ImmValue;
454   EVT EltTy = N->getValueType(0).getVectorElementType();
455 
456   if (N->getOpcode() == ISD::BITCAST)
457     N = N->getOperand(0);
458 
459   if (selectVSplat (N.getNode(), ImmValue) &&
460       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
461     if (( Signed && ImmValue.isSignedIntN(ImmBitSize)) ||
462         (!Signed && ImmValue.isIntN(ImmBitSize))) {
463       Imm = CurDAG->getTargetConstant(ImmValue, EltTy);
464       return true;
465     }
466   }
467 
468   return false;
469 }
470 
471 // Select constant vector splats.
472 bool MipsSEDAGToDAGISel::
473 selectVSplatUimm1(SDValue N, SDValue &Imm) const {
474   return selectVSplatCommon(N, Imm, false, 1);
475 }
476 
477 bool MipsSEDAGToDAGISel::
478 selectVSplatUimm2(SDValue N, SDValue &Imm) const {
479   return selectVSplatCommon(N, Imm, false, 2);
480 }
481 
482 bool MipsSEDAGToDAGISel::
483 selectVSplatUimm3(SDValue N, SDValue &Imm) const {
484   return selectVSplatCommon(N, Imm, false, 3);
485 }
486 
487 // Select constant vector splats.
488 bool MipsSEDAGToDAGISel::
489 selectVSplatUimm4(SDValue N, SDValue &Imm) const {
490   return selectVSplatCommon(N, Imm, false, 4);
491 }
492 
493 // Select constant vector splats.
494 bool MipsSEDAGToDAGISel::
495 selectVSplatUimm5(SDValue N, SDValue &Imm) const {
496   return selectVSplatCommon(N, Imm, false, 5);
497 }
498 
499 // Select constant vector splats.
500 bool MipsSEDAGToDAGISel::
501 selectVSplatUimm6(SDValue N, SDValue &Imm) const {
502   return selectVSplatCommon(N, Imm, false, 6);
503 }
504 
505 // Select constant vector splats.
506 bool MipsSEDAGToDAGISel::
507 selectVSplatUimm8(SDValue N, SDValue &Imm) const {
508   return selectVSplatCommon(N, Imm, false, 8);
509 }
510 
511 // Select constant vector splats.
512 bool MipsSEDAGToDAGISel::
513 selectVSplatSimm5(SDValue N, SDValue &Imm) const {
514   return selectVSplatCommon(N, Imm, true, 5);
515 }
516 
517 // Select constant vector splats whose value is a power of 2.
518 //
519 // In addition to the requirements of selectVSplat(), this function returns
520 // true and sets Imm if:
521 // * The splat value is the same width as the elements of the vector
522 // * The splat value is a power of two.
523 //
524 // This function looks through ISD::BITCAST nodes.
525 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
526 //       sometimes a shuffle in big-endian mode.
527 bool MipsSEDAGToDAGISel::selectVSplatUimmPow2(SDValue N, SDValue &Imm) const {
528   APInt ImmValue;
529   EVT EltTy = N->getValueType(0).getVectorElementType();
530 
531   if (N->getOpcode() == ISD::BITCAST)
532     N = N->getOperand(0);
533 
534   if (selectVSplat (N.getNode(), ImmValue) &&
535       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
536     int32_t Log2 = ImmValue.exactLogBase2();
537 
538     if (Log2 != -1) {
539       Imm = CurDAG->getTargetConstant(Log2, EltTy);
540       return true;
541     }
542   }
543 
544   return false;
545 }
546 
547 // Select constant vector splats whose value only has a consecutive sequence
548 // of left-most bits set (e.g. 0b11...1100...00).
549 //
550 // In addition to the requirements of selectVSplat(), this function returns
551 // true and sets Imm if:
552 // * The splat value is the same width as the elements of the vector
553 // * The splat value is a consecutive sequence of left-most bits.
554 //
555 // This function looks through ISD::BITCAST nodes.
556 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
557 //       sometimes a shuffle in big-endian mode.
558 bool MipsSEDAGToDAGISel::selectVSplatMaskL(SDValue N, SDValue &Imm) const {
559   APInt ImmValue;
560   EVT EltTy = N->getValueType(0).getVectorElementType();
561 
562   if (N->getOpcode() == ISD::BITCAST)
563     N = N->getOperand(0);
564 
565   if (selectVSplat(N.getNode(), ImmValue) &&
566       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
567     // Extract the run of set bits starting with bit zero from the bitwise
568     // inverse of ImmValue, and test that the inverse of this is the same
569     // as the original value.
570     if (ImmValue == ~(~ImmValue & ~(~ImmValue + 1))) {
571 
572       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
573       return true;
574     }
575   }
576 
577   return false;
578 }
579 
580 // Select constant vector splats whose value only has a consecutive sequence
581 // of right-most bits set (e.g. 0b00...0011...11).
582 //
583 // In addition to the requirements of selectVSplat(), this function returns
584 // true and sets Imm if:
585 // * The splat value is the same width as the elements of the vector
586 // * The splat value is a consecutive sequence of right-most bits.
587 //
588 // This function looks through ISD::BITCAST nodes.
589 // TODO: This might not be appropriate for big-endian MSA since BITCAST is
590 //       sometimes a shuffle in big-endian mode.
591 bool MipsSEDAGToDAGISel::selectVSplatMaskR(SDValue N, SDValue &Imm) const {
592   APInt ImmValue;
593   EVT EltTy = N->getValueType(0).getVectorElementType();
594 
595   if (N->getOpcode() == ISD::BITCAST)
596     N = N->getOperand(0);
597 
598   if (selectVSplat(N.getNode(), ImmValue) &&
599       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
600     // Extract the run of set bits starting with bit zero, and test that the
601     // result is the same as the original value
602     if (ImmValue == (ImmValue & ~(ImmValue + 1))) {
603       Imm = CurDAG->getTargetConstant(ImmValue.countPopulation(), EltTy);
604       return true;
605     }
606   }
607 
608   return false;
609 }
610 
611 bool MipsSEDAGToDAGISel::selectVSplatUimmInvPow2(SDValue N,
612                                                  SDValue &Imm) const {
613   APInt ImmValue;
614   EVT EltTy = N->getValueType(0).getVectorElementType();
615 
616   if (N->getOpcode() == ISD::BITCAST)
617     N = N->getOperand(0);
618 
619   if (selectVSplat(N.getNode(), ImmValue) &&
620       ImmValue.getBitWidth() == EltTy.getSizeInBits()) {
621     int32_t Log2 = (~ImmValue).exactLogBase2();
622 
623     if (Log2 != -1) {
624       Imm = CurDAG->getTargetConstant(Log2, EltTy);
625       return true;
626     }
627   }
628 
629   return false;
630 }
631 
632 std::pair<bool, SDNode*> MipsSEDAGToDAGISel::selectNode(SDNode *Node) {
633   unsigned Opcode = Node->getOpcode();
634   SDLoc DL(Node);
635 
636   ///
637   // Instruction Selection not handled by the auto-generated
638   // tablegen selection should be handled here.
639   ///
640   SDNode *Result;
641 
642   switch(Opcode) {
643   default: break;
644 
645   case ISD::SUBE: {
646     SDValue InFlag = Node->getOperand(2);
647     Result = selectAddESubE(Mips::SUBu, InFlag, InFlag.getOperand(0), DL, Node);
648     return std::make_pair(true, Result);
649   }
650 
651   case ISD::ADDE: {
652     if (Subtarget->hasDSP()) // Select DSP instructions, ADDSC and ADDWC.
653       break;
654     SDValue InFlag = Node->getOperand(2);
655     Result = selectAddESubE(Mips::ADDu, InFlag, InFlag.getValue(0), DL, Node);
656     return std::make_pair(true, Result);
657   }
658 
659   case ISD::ConstantFP: {
660     ConstantFPSDNode *CN = dyn_cast<ConstantFPSDNode>(Node);
661     if (Node->getValueType(0) == MVT::f64 && CN->isExactlyValue(+0.0)) {
662       if (Subtarget->isGP64bit()) {
663         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
664                                               Mips::ZERO_64, MVT::i64);
665         Result = CurDAG->getMachineNode(Mips::DMTC1, DL, MVT::f64, Zero);
666       } else if (Subtarget->isFP64bit()) {
667         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
668                                               Mips::ZERO, MVT::i32);
669         Result = CurDAG->getMachineNode(Mips::BuildPairF64_64, DL, MVT::f64,
670                                         Zero, Zero);
671       } else {
672         SDValue Zero = CurDAG->getCopyFromReg(CurDAG->getEntryNode(), DL,
673                                               Mips::ZERO, MVT::i32);
674         Result = CurDAG->getMachineNode(Mips::BuildPairF64, DL, MVT::f64, Zero,
675                                         Zero);
676       }
677 
678       return std::make_pair(true, Result);
679     }
680     break;
681   }
682 
683   case ISD::Constant: {
684     const ConstantSDNode *CN = dyn_cast<ConstantSDNode>(Node);
685     unsigned Size = CN->getValueSizeInBits(0);
686 
687     if (Size == 32)
688       break;
689 
690     MipsAnalyzeImmediate AnalyzeImm;
691     int64_t Imm = CN->getSExtValue();
692 
693     const MipsAnalyzeImmediate::InstSeq &Seq =
694       AnalyzeImm.Analyze(Imm, Size, false);
695 
696     MipsAnalyzeImmediate::InstSeq::const_iterator Inst = Seq.begin();
697     SDLoc DL(CN);
698     SDNode *RegOpnd;
699     SDValue ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
700                                                 MVT::i64);
701 
702     // The first instruction can be a LUi which is different from other
703     // instructions (ADDiu, ORI and SLL) in that it does not have a register
704     // operand.
705     if (Inst->Opc == Mips::LUi64)
706       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64, ImmOpnd);
707     else
708       RegOpnd =
709         CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
710                                CurDAG->getRegister(Mips::ZERO_64, MVT::i64),
711                                ImmOpnd);
712 
713     // The remaining instructions in the sequence are handled here.
714     for (++Inst; Inst != Seq.end(); ++Inst) {
715       ImmOpnd = CurDAG->getTargetConstant(SignExtend64<16>(Inst->ImmOpnd),
716                                           MVT::i64);
717       RegOpnd = CurDAG->getMachineNode(Inst->Opc, DL, MVT::i64,
718                                        SDValue(RegOpnd, 0), ImmOpnd);
719     }
720 
721     return std::make_pair(true, RegOpnd);
722   }
723 
724   case ISD::INTRINSIC_W_CHAIN: {
725     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
726     default:
727       break;
728 
729     case Intrinsic::mips_cfcmsa: {
730       SDValue ChainIn = Node->getOperand(0);
731       SDValue RegIdx = Node->getOperand(2);
732       SDValue Reg = CurDAG->getCopyFromReg(ChainIn, DL,
733                                            getMSACtrlReg(RegIdx), MVT::i32);
734       return std::make_pair(true, Reg.getNode());
735     }
736     }
737     break;
738   }
739 
740   case ISD::INTRINSIC_WO_CHAIN: {
741     switch (cast<ConstantSDNode>(Node->getOperand(0))->getZExtValue()) {
742     default:
743       break;
744 
745     case Intrinsic::mips_move_v:
746       // Like an assignment but will always produce a move.v even if
747       // unnecessary.
748       return std::make_pair(true,
749                             CurDAG->getMachineNode(Mips::MOVE_V, DL,
750                                                    Node->getValueType(0),
751                                                    Node->getOperand(1)));
752     }
753     break;
754   }
755 
756   case ISD::INTRINSIC_VOID: {
757     switch (cast<ConstantSDNode>(Node->getOperand(1))->getZExtValue()) {
758     default:
759       break;
760 
761     case Intrinsic::mips_ctcmsa: {
762       SDValue ChainIn = Node->getOperand(0);
763       SDValue RegIdx  = Node->getOperand(2);
764       SDValue Value   = Node->getOperand(3);
765       SDValue ChainOut = CurDAG->getCopyToReg(ChainIn, DL,
766                                               getMSACtrlReg(RegIdx), Value);
767       return std::make_pair(true, ChainOut.getNode());
768     }
769     }
770     break;
771   }
772 
773   case MipsISD::ThreadPointer: {
774     EVT PtrVT = getTargetLowering()->getPointerTy();
775     unsigned RdhwrOpc, DestReg;
776 
777     if (PtrVT == MVT::i32) {
778       RdhwrOpc = Mips::RDHWR;
779       DestReg = Mips::V1;
780     } else {
781       RdhwrOpc = Mips::RDHWR64;
782       DestReg = Mips::V1_64;
783     }
784 
785     SDNode *Rdhwr =
786       CurDAG->getMachineNode(RdhwrOpc, SDLoc(Node),
787                              Node->getValueType(0),
788                              CurDAG->getRegister(Mips::HWR29, MVT::i32));
789     SDValue Chain = CurDAG->getCopyToReg(CurDAG->getEntryNode(), DL, DestReg,
790                                          SDValue(Rdhwr, 0));
791     SDValue ResNode = CurDAG->getCopyFromReg(Chain, DL, DestReg, PtrVT);
792     ReplaceUses(SDValue(Node, 0), ResNode);
793     return std::make_pair(true, ResNode.getNode());
794   }
795 
796   case ISD::BUILD_VECTOR: {
797     // Select appropriate ldi.[bhwd] instructions for constant splats of
798     // 128-bit when MSA is enabled. Fixup any register class mismatches that
799     // occur as a result.
800     //
801     // This allows the compiler to use a wider range of immediates than would
802     // otherwise be allowed. If, for example, v4i32 could only use ldi.h then
803     // it would not be possible to load { 0x01010101, 0x01010101, 0x01010101,
804     // 0x01010101 } without using a constant pool. This would be sub-optimal
805     // when // 'ldi.b wd, 1' is capable of producing that bit-pattern in the
806     // same set/ of registers. Similarly, ldi.h isn't capable of producing {
807     // 0x00000000, 0x00000001, 0x00000000, 0x00000001 } but 'ldi.d wd, 1' can.
808 
809     BuildVectorSDNode *BVN = cast<BuildVectorSDNode>(Node);
810     APInt SplatValue, SplatUndef;
811     unsigned SplatBitSize;
812     bool HasAnyUndefs;
813     unsigned LdiOp;
814     EVT ResVecTy = BVN->getValueType(0);
815     EVT ViaVecTy;
816 
817     if (!Subtarget->hasMSA() || !BVN->getValueType(0).is128BitVector())
818       return std::make_pair(false, nullptr);
819 
820     if (!BVN->isConstantSplat(SplatValue, SplatUndef, SplatBitSize,
821                               HasAnyUndefs, 8,
822                               !Subtarget->isLittle()))
823       return std::make_pair(false, nullptr);
824 
825     switch (SplatBitSize) {
826     default:
827       return std::make_pair(false, nullptr);
828     case 8:
829       LdiOp = Mips::LDI_B;
830       ViaVecTy = MVT::v16i8;
831       break;
832     case 16:
833       LdiOp = Mips::LDI_H;
834       ViaVecTy = MVT::v8i16;
835       break;
836     case 32:
837       LdiOp = Mips::LDI_W;
838       ViaVecTy = MVT::v4i32;
839       break;
840     case 64:
841       LdiOp = Mips::LDI_D;
842       ViaVecTy = MVT::v2i64;
843       break;
844     }
845 
846     if (!SplatValue.isSignedIntN(10))
847       return std::make_pair(false, nullptr);
848 
849     SDValue Imm = CurDAG->getTargetConstant(SplatValue,
850                                             ViaVecTy.getVectorElementType());
851 
852     SDNode *Res = CurDAG->getMachineNode(LdiOp, SDLoc(Node), ViaVecTy, Imm);
853 
854     if (ResVecTy != ViaVecTy) {
855       // If LdiOp is writing to a different register class to ResVecTy, then
856       // fix it up here. This COPY_TO_REGCLASS should never cause a move.v
857       // since the source and destination register sets contain the same
858       // registers.
859       const TargetLowering *TLI = getTargetLowering();
860       MVT ResVecTySimple = ResVecTy.getSimpleVT();
861       const TargetRegisterClass *RC = TLI->getRegClassFor(ResVecTySimple);
862       Res = CurDAG->getMachineNode(Mips::COPY_TO_REGCLASS, SDLoc(Node),
863                                    ResVecTy, SDValue(Res, 0),
864                                    CurDAG->getTargetConstant(RC->getID(),
865                                                              MVT::i32));
866     }
867 
868     return std::make_pair(true, Res);
869   }
870 
871   }
872 
873   return std::make_pair(false, nullptr);
874 }
875 
876 FunctionPass *llvm::createMipsSEISelDag(MipsTargetMachine &TM) {
877   return new MipsSEDAGToDAGISel(TM);
878 }
879